[−][src]Module lpc55s6x_pac::usart0::fifointenset
FIFO interrupt enable set (enable) and read register.
Structs
| RXERR_W | Write proxy for field |
| RXLVL_W | Write proxy for field |
| TXERR_W | Write proxy for field |
| TXLVL_W | Write proxy for field |
Enums
| RXERR_A | Determines whether an interrupt occurs when a receive error occurs, based on the RXERR flag in the FIFOSTAT register. |
| RXLVL_A | Determines whether an interrupt occurs when a the receive FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. |
| TXERR_A | Determines whether an interrupt occurs when a transmit error occurs, based on the TXERR flag in the FIFOSTAT register. |
| TXLVL_A | Determines whether an interrupt occurs when a the transmit FIFO reaches the level specified by the TXLVL field in the FIFOTRIG register. |
Type Definitions
| R | Reader of register FIFOINTENSET |
| RXERR_R | Reader of field |
| RXLVL_R | Reader of field |
| TXERR_R | Reader of field |
| TXLVL_R | Reader of field |
| W | Writer for register FIFOINTENSET |