[][src]Module lpc55s6x_pac::i2s0

I2S interface

Modules

cfg1

Configuration register 1 for the primary channel pair.

cfg2

Configuration register 2 for the primary channel pair.

div

Clock divider, used by all channel pairs.

fifocfg

FIFO configuration and enable register.

fifointenclr

FIFO interrupt enable clear (disable) and read register.

fifointenset

FIFO interrupt enable set (enable) and read register.

fifointstat

FIFO interrupt status register.

fiford

FIFO read data.

fiford48h

FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.

fiford48hnopop

FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.

fifordnopop

FIFO data read with no FIFO pop.

fifostat

FIFO status register.

fifotrig

FIFO trigger settings for interrupt and DMA request.

fifowr

FIFO write data.

fifowr48h

FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.

id

I2S Module identification

stat

Status register for the primary channel pair.

Structs

RegisterBlock

Register block

Type Definitions

CFG1

Configuration register 1 for the primary channel pair.

CFG2

Configuration register 2 for the primary channel pair.

DIV

Clock divider, used by all channel pairs.

FIFOCFG

FIFO configuration and enable register.

FIFOINTENCLR

FIFO interrupt enable clear (disable) and read register.

FIFOINTENSET

FIFO interrupt enable set (enable) and read register.

FIFOINTSTAT

FIFO interrupt status register.

FIFORD

FIFO read data.

FIFORD48H

FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.

FIFORD48HNOPOP

FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.

FIFORDNOPOP

FIFO data read with no FIFO pop.

FIFOSTAT

FIFO status register.

FIFOTRIG

FIFO trigger settings for interrupt and DMA request.

FIFOWR

FIFO write data.

FIFOWR48H

FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA.

ID

I2S Module identification

STAT

Status register for the primary channel pair.