Module lpc55_pac::usbphy::pll_sic_clr
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USB PHY PLL Control/Status Register
Structs
Field PLL_DIV_SEL reader - This field controls the USB PLL feedback loop divider
Field PLL_DIV_SEL writer - This field controls the USB PLL feedback loop divider
Field PLL_ENABLE reader - Enables the clock output from the USB PLL
Field PLL_ENABLE writer - Enables the clock output from the USB PLL
Field PLL_EN_USB_CLKS reader - Enables the USB clock from PLL to USB PHY
Field PLL_EN_USB_CLKS writer - Enables the USB clock from PLL to USB PHY
Field PLL_LOCK reader - USB PLL lock status indicator
Field PLL_POWER reader - Power up the USB PLL
Field PLL_POWER writer - Power up the USB PLL
Field PLL_PREDIV reader - This is selection between /1 or /2 to expand the range of ref input clock.
Field PLL_PREDIV writer - This is selection between /1 or /2 to expand the range of ref input clock.
Field PLL_REG_ENABLE reader - This field controls the USB PLL regulator, set to enable the regulator
Field PLL_REG_ENABLE writer - This field controls the USB PLL regulator, set to enable the regulator
USB PHY PLL Control/Status Register
Register PLL_SIC_CLR reader
Field REFBIAS_PWD reader - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
Field REFBIAS_PWD_SEL reader - Reference bias power down select.
Field REFBIAS_PWD_SEL writer - Reference bias power down select.
Field REFBIAS_PWD writer - Power down the reference bias This bit is only used when REFBIAS_PWD_SEL is set to 1.
Register PLL_SIC_CLR writer
Enums
This field controls the USB PLL feedback loop divider
USB PLL lock status indicator
Reference bias power down select.