Expand description
FIFO configuration and enable register.
Structs
Field DMARX reader - DMA configuration for receive.
Field DMARX writer - DMA configuration for receive.
Field DMATX reader - DMA configuration for transmit.
Field DMATX writer - DMA configuration for transmit.
Field EMPTYRX reader - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
Field EMPTYRX writer - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
Field EMPTYTX reader - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
Field EMPTYTX writer - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
Field ENABLERX reader - Enable the receive FIFO.
Field ENABLERX writer - Enable the receive FIFO.
Field ENABLETX reader - Enable the transmit FIFO.
Field ENABLETX writer - Enable the transmit FIFO.
FIFO configuration and enable register.
Register FIFOCFG reader
Field SIZE reader - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
Register FIFOCFG writer
Field WAKERX reader - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Field WAKERX writer - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Field WAKETX reader - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Field WAKETX writer - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Enums
DMA configuration for receive.
DMA configuration for transmit.
Enable the receive FIFO.
Enable the transmit FIFO.
Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.