Module lpc55_pac::syscon::ahbclkctrl0
source · [−]Expand description
AHB Clock control 0
Structs
Field ADC reader - Enables the clock for the ADC.
Field ADC writer - Enables the clock for the ADC.
AHB Clock control 0
Field CRCGEN reader - Enables the clock for the CRCGEN.
Field CRCGEN writer - Enables the clock for the CRCGEN.
Field DMA0 reader - Enables the clock for the DMA0.
Field DMA0 writer - Enables the clock for the DMA0.
Field FLASH reader - Enables the clock for the Flash controller.
Field FLASH writer - Enables the clock for the Flash controller.
Field FMC reader - Enables the clock for the FMC controller.
Field FMC writer - Enables the clock for the FMC controller.
Field GINT reader - Enables the clock for the Group interrupt (GINT).
Field GINT writer - Enables the clock for the Group interrupt (GINT).
Field GPIO0 reader - Enables the clock for the GPIO0.
Field GPIO0 writer - Enables the clock for the GPIO0.
Field GPIO1 reader - Enables the clock for the GPIO1.
Field GPIO1 writer - Enables the clock for the GPIO1.
Field GPIO2 reader - Enables the clock for the GPIO2.
Field GPIO2 writer - Enables the clock for the GPIO2.
Field GPIO3 reader - Enables the clock for the GPIO3.
Field GPIO3 writer - Enables the clock for the GPIO3.
Field IOCON reader - Enables the clock for the I/O controller.
Field IOCON writer - Enables the clock for the I/O controller.
Field MAILBOX reader - Enables the clock for the Inter CPU communication Mailbox.
Field MAILBOX writer - Enables the clock for the Inter CPU communication Mailbox.
Field MUX reader - Enables the clock for the Input Mux.
Field MUX writer - Enables the clock for the Input Mux.
Field PINT reader - Enables the clock for the Pin interrupt (PINT).
Field PINT writer - Enables the clock for the Pin interrupt (PINT).
Register AHBCLKCTRL0 reader
Field ROM reader - Enables the clock for the ROM.
Field ROM writer - Enables the clock for the ROM.
Field RTC reader - Enables the clock for the Real Time Clock (RTC).
Field RTC writer - Enables the clock for the Real Time Clock (RTC).
Field SRAM_CTRL1 reader - Enables the clock for the SRAM Controller 1.
Field SRAM_CTRL1 writer - Enables the clock for the SRAM Controller 1.
Field SRAM_CTRL2 reader - Enables the clock for the SRAM Controller 2.
Field SRAM_CTRL2 writer - Enables the clock for the SRAM Controller 2.
Field SRAM_CTRL3 reader - Enables the clock for the SRAM Controller 3.
Field SRAM_CTRL3 writer - Enables the clock for the SRAM Controller 3.
Field SRAM_CTRL4 reader - Enables the clock for the SRAM Controller 4.
Field SRAM_CTRL4 writer - Enables the clock for the SRAM Controller 4.
Register AHBCLKCTRL0 writer
Field WWDT reader - Enables the clock for the Watchdog Timer.
Field WWDT writer - Enables the clock for the Watchdog Timer.
Enums
Enables the clock for the ADC.
Enables the clock for the CRCGEN.
Enables the clock for the DMA0.
Enables the clock for the Flash controller.
Enables the clock for the FMC controller.
Enables the clock for the Group interrupt (GINT).
Enables the clock for the GPIO0.
Enables the clock for the GPIO1.
Enables the clock for the GPIO2.
Enables the clock for the GPIO3.
Enables the clock for the I/O controller.
Enables the clock for the Inter CPU communication Mailbox.
Enables the clock for the Input Mux.
Enables the clock for the Pin interrupt (PINT).
Enables the clock for the ROM.
Enables the clock for the Real Time Clock (RTC).
Enables the clock for the SRAM Controller 1.
Enables the clock for the SRAM Controller 2.
Enables the clock for the SRAM Controller 3.
Enables the clock for the SRAM Controller 4.
Enables the clock for the Watchdog Timer.