Expand description
PRINCE
Modules
Base Address for region 0 register
Base Address for region 1 register
Base Address for region 2 register
Encryption Enable register
Initial Vector register for region 0, Least Significant Bits
Initial Vector register for region 1, Least Significant Bits
Initial Vector register for region 2, Least Significant Bits
Initial Vector register for region 0, Most Significant Bits
Initial Vector register for region 1, Most Significant Bits
Initial Vector register for region 2, Most Significant Bits
Lock register
Data Mask register, 32 Least Significant Bits
Data Mask register, 32 Most Significant Bits
Sub-Region Enable register for region 0
Sub-Region Enable register for region 1
Sub-Region Enable register for region 2
Structs
Register block
Type Definitions
BASE_ADDR0 register accessor: an alias for Reg<BASE_ADDR0_SPEC>
BASE_ADDR1 register accessor: an alias for Reg<BASE_ADDR1_SPEC>
BASE_ADDR2 register accessor: an alias for Reg<BASE_ADDR2_SPEC>
ENC_ENABLE register accessor: an alias for Reg<ENC_ENABLE_SPEC>
IV_LSB0 register accessor: an alias for Reg<IV_LSB0_SPEC>
IV_LSB1 register accessor: an alias for Reg<IV_LSB1_SPEC>
IV_LSB2 register accessor: an alias for Reg<IV_LSB2_SPEC>
IV_MSB0 register accessor: an alias for Reg<IV_MSB0_SPEC>
IV_MSB1 register accessor: an alias for Reg<IV_MSB1_SPEC>
IV_MSB2 register accessor: an alias for Reg<IV_MSB2_SPEC>
LOCK register accessor: an alias for Reg<LOCK_SPEC>
MASK_LSB register accessor: an alias for Reg<MASK_LSB_SPEC>
MASK_MSB register accessor: an alias for Reg<MASK_MSB_SPEC>
SR_ENABLE0 register accessor: an alias for Reg<SR_ENABLE0_SPEC>
SR_ENABLE1 register accessor: an alias for Reg<SR_ENABLE1_SPEC>
SR_ENABLE2 register accessor: an alias for Reg<SR_ENABLE2_SPEC>