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#[doc = "Register `DLY` reader"] pub struct R(crate::R<DLY_SPEC>); impl core::ops::Deref for R { type Target = crate::R<DLY_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::convert::From<crate::R<DLY_SPEC>> for R { fn from(reader: crate::R<DLY_SPEC>) -> Self { R(reader) } } #[doc = "Register `DLY` writer"] pub struct W(crate::W<DLY_SPEC>); impl core::ops::Deref for W { type Target = crate::W<DLY_SPEC>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } impl core::ops::DerefMut for W { #[inline(always)] fn deref_mut(&mut self) -> &mut Self::Target { &mut self.0 } } impl core::convert::From<crate::W<DLY_SPEC>> for W { fn from(writer: crate::W<DLY_SPEC>) -> Self { W(writer) } } #[doc = "Field `PRE_DELAY` reader - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] pub struct PRE_DELAY_R(crate::FieldReader<u8, u8>); impl PRE_DELAY_R { pub(crate) fn new(bits: u8) -> Self { PRE_DELAY_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for PRE_DELAY_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `PRE_DELAY` writer - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] pub struct PRE_DELAY_W<'a> { w: &'a mut W, } impl<'a> PRE_DELAY_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f); self.w } } #[doc = "Field `POST_DELAY` reader - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] pub struct POST_DELAY_R(crate::FieldReader<u8, u8>); impl POST_DELAY_R { pub(crate) fn new(bits: u8) -> Self { POST_DELAY_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for POST_DELAY_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `POST_DELAY` writer - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] pub struct POST_DELAY_W<'a> { w: &'a mut W, } impl<'a> POST_DELAY_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 4)) | ((value as u32 & 0x0f) << 4); self.w } } #[doc = "Field `FRAME_DELAY` reader - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] pub struct FRAME_DELAY_R(crate::FieldReader<u8, u8>); impl FRAME_DELAY_R { pub(crate) fn new(bits: u8) -> Self { FRAME_DELAY_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for FRAME_DELAY_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `FRAME_DELAY` writer - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] pub struct FRAME_DELAY_W<'a> { w: &'a mut W, } impl<'a> FRAME_DELAY_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 8)) | ((value as u32 & 0x0f) << 8); self.w } } #[doc = "Field `TRANSFER_DELAY` reader - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."] pub struct TRANSFER_DELAY_R(crate::FieldReader<u8, u8>); impl TRANSFER_DELAY_R { pub(crate) fn new(bits: u8) -> Self { TRANSFER_DELAY_R(crate::FieldReader::new(bits)) } } impl core::ops::Deref for TRANSFER_DELAY_R { type Target = crate::FieldReader<u8, u8>; #[inline(always)] fn deref(&self) -> &Self::Target { &self.0 } } #[doc = "Field `TRANSFER_DELAY` writer - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."] pub struct TRANSFER_DELAY_W<'a> { w: &'a mut W, } impl<'a> TRANSFER_DELAY_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 12)) | ((value as u32 & 0x0f) << 12); self.w } } impl R { #[doc = "Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] #[inline(always)] pub fn pre_delay(&self) -> PRE_DELAY_R { PRE_DELAY_R::new((self.bits & 0x0f) as u8) } #[doc = "Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] #[inline(always)] pub fn post_delay(&self) -> POST_DELAY_R { POST_DELAY_R::new(((self.bits >> 4) & 0x0f) as u8) } #[doc = "Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] #[inline(always)] pub fn frame_delay(&self) -> FRAME_DELAY_R { FRAME_DELAY_R::new(((self.bits >> 8) & 0x0f) as u8) } #[doc = "Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."] #[inline(always)] pub fn transfer_delay(&self) -> TRANSFER_DELAY_R { TRANSFER_DELAY_R::new(((self.bits >> 12) & 0x0f) as u8) } } impl W { #[doc = "Bits 0:3 - Controls the amount of time between SSEL assertion and the beginning of a data transfer. There is always one SPI clock time between SSEL assertion and the first clock edge. This is not considered part of the pre-delay. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] #[inline(always)] pub fn pre_delay(&mut self) -> PRE_DELAY_W { PRE_DELAY_W { w: self } } #[doc = "Bits 4:7 - Controls the amount of time between the end of a data transfer and SSEL deassertion. 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] #[inline(always)] pub fn post_delay(&mut self) -> POST_DELAY_W { POST_DELAY_W { w: self } } #[doc = "Bits 8:11 - If the EOF flag is set, controls the minimum amount of time between the current frame and the next frame (or SSEL deassertion if EOT). 0x0 = No additional time is inserted. 0x1 = 1 SPI clock time is inserted. 0x2 = 2 SPI clock times are inserted. 0xF = 15 SPI clock times are inserted."] #[inline(always)] pub fn frame_delay(&mut self) -> FRAME_DELAY_W { FRAME_DELAY_W { w: self } } #[doc = "Bits 12:15 - Controls the minimum amount of time that the SSEL is deasserted between transfers. 0x0 = The minimum time that SSEL is deasserted is 1 SPI clock time. (Zero added time.) 0x1 = The minimum time that SSEL is deasserted is 2 SPI clock times. 0x2 = The minimum time that SSEL is deasserted is 3 SPI clock times. 0xF = The minimum time that SSEL is deasserted is 16 SPI clock times."] #[inline(always)] pub fn transfer_delay(&mut self) -> TRANSFER_DELAY_W { TRANSFER_DELAY_W { w: self } } #[doc = "Writes raw bits to the register."] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.0.bits(bits); self } } #[doc = "SPI Delay register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dly](index.html) module"] pub struct DLY_SPEC; impl crate::RegisterSpec for DLY_SPEC { type Ux = u32; } #[doc = "`read()` method returns [dly::R](R) reader structure"] impl crate::Readable for DLY_SPEC { type Reader = R; } #[doc = "`write(|w| ..)` method takes [dly::W](W) writer structure"] impl crate::Writable for DLY_SPEC { type Writer = W; } #[doc = "`reset()` method sets DLY to value 0"] impl crate::Resettable for DLY_SPEC { #[inline(always)] fn reset_value() -> Self::Ux { 0 } }