| DMARX_R | Field DMARX reader - DMA configuration for receive.
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| DMARX_W | Field DMARX writer - DMA configuration for receive.
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| DMATX_R | Field DMATX reader - DMA configuration for transmit.
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| DMATX_W | Field DMATX writer - DMA configuration for transmit.
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| EMPTYRX_R | Field EMPTYRX reader - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
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| EMPTYRX_W | Field EMPTYRX writer - Empty command for the receive FIFO. When a 1 is written to this bit, the RX FIFO is emptied.
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| EMPTYTX_R | Field EMPTYTX reader - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
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| EMPTYTX_W | Field EMPTYTX writer - Empty command for the transmit FIFO. When a 1 is written to this bit, the TX FIFO is emptied.
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| ENABLERX_R | Field ENABLERX reader - Enable the receive FIFO.
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| ENABLERX_W | Field ENABLERX writer - Enable the receive FIFO.
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| ENABLETX_R | Field ENABLETX reader - Enable the transmit FIFO.
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| ENABLETX_W | Field ENABLETX writer - Enable the transmit FIFO.
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| FIFOCFG_SPEC | FIFO configuration and enable register.
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| PACK48_R | Field PACK48 reader - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
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| PACK48_W | Field PACK48 writer - Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
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| R | Register FIFOCFG reader
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| SIZE_R | Field SIZE reader - FIFO size configuration. This is a read-only field. 0x0 = FIFO is configured as 16 entries of 8 bits. 0x1, 0x2, 0x3 = not applicable to USART.
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| TXI2SE0_R | Field TXI2SE0 reader - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.
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| TXI2SE0_W | Field TXI2SE0 writer - Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.
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| W | Register FIFOCFG writer
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| WAKERX_R | Field WAKERX reader - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
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| WAKERX_W | Field WAKERX writer - Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
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| WAKETX_R | Field WAKETX reader - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
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| WAKETX_W | Field WAKETX writer - Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
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| DMARX_A | DMA configuration for receive.
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| DMATX_A | DMA configuration for transmit.
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| ENABLERX_A | Enable the receive FIFO.
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| ENABLETX_A | Enable the transmit FIFO.
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| PACK48_A | Packing format for 48-bit data. This relates to how data is entered into or taken from the FIFO by software or DMA.
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| TXI2SE0_A | Transmit I2S empty 0. Determines the value sent by the I2S in transmit mode if the TX FIFO becomes empty. This value is sent repeatedly until the I2S is paused, the error is cleared, new data is provided, and the I2S is un-paused.
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| WAKERX_A | Wake-up for receive FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
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| WAKETX_A | Wake-up for transmit FIFO level. This allows the device to be woken from reduced power modes (up to power-down, as long as the peripheral function works in that power mode) without enabling the TXLVL interrupt. Only DMA wakes up, processes data, and goes back to sleep. The CPU will remain stopped until woken by another cause, such as DMA completion. See Hardware Wake-up control register.
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