Module lpc55_pac::ahb_secure_ctrl::sec_gpio_mask1[][src]

Secure GPIO mask for port 1 pins.

Structs

PIO1_PIN0_SEC_MASK_R

Field PIO1_PIN0_SEC_MASK reader - Secure mask for pin P1_0

PIO1_PIN0_SEC_MASK_W

Field PIO1_PIN0_SEC_MASK writer - Secure mask for pin P1_0

PIO1_PIN1_SEC_MASK_R

Field PIO1_PIN1_SEC_MASK reader - Secure mask for pin P1_1

PIO1_PIN1_SEC_MASK_W

Field PIO1_PIN1_SEC_MASK writer - Secure mask for pin P1_1

PIO1_PIN2_SEC_MASK_R

Field PIO1_PIN2_SEC_MASK reader - Secure mask for pin P1_2

PIO1_PIN2_SEC_MASK_W

Field PIO1_PIN2_SEC_MASK writer - Secure mask for pin P1_2

PIO1_PIN3_SEC_MASK_R

Field PIO1_PIN3_SEC_MASK reader - Secure mask for pin P1_3

PIO1_PIN3_SEC_MASK_W

Field PIO1_PIN3_SEC_MASK writer - Secure mask for pin P1_3

PIO1_PIN4_SEC_MASK_R

Field PIO1_PIN4_SEC_MASK reader - Secure mask for pin P1_4

PIO1_PIN4_SEC_MASK_W

Field PIO1_PIN4_SEC_MASK writer - Secure mask for pin P1_4

PIO1_PIN5_SEC_MASK_R

Field PIO1_PIN5_SEC_MASK reader - Secure mask for pin P1_5

PIO1_PIN5_SEC_MASK_W

Field PIO1_PIN5_SEC_MASK writer - Secure mask for pin P1_5

PIO1_PIN6_SEC_MASK_R

Field PIO1_PIN6_SEC_MASK reader - Secure mask for pin P1_6

PIO1_PIN6_SEC_MASK_W

Field PIO1_PIN6_SEC_MASK writer - Secure mask for pin P1_6

PIO1_PIN7_SEC_MASK_R

Field PIO1_PIN7_SEC_MASK reader - Secure mask for pin P1_7

PIO1_PIN7_SEC_MASK_W

Field PIO1_PIN7_SEC_MASK writer - Secure mask for pin P1_7

PIO1_PIN8_SEC_MASK_R

Field PIO1_PIN8_SEC_MASK reader - Secure mask for pin P1_8

PIO1_PIN8_SEC_MASK_W

Field PIO1_PIN8_SEC_MASK writer - Secure mask for pin P1_8

PIO1_PIN9_SEC_MASK_R

Field PIO1_PIN9_SEC_MASK reader - Secure mask for pin P1_9

PIO1_PIN9_SEC_MASK_W

Field PIO1_PIN9_SEC_MASK writer - Secure mask for pin P1_9

PIO1_PIN10_SEC_MASK_R

Field PIO1_PIN10_SEC_MASK reader - Secure mask for pin P1_10

PIO1_PIN10_SEC_MASK_W

Field PIO1_PIN10_SEC_MASK writer - Secure mask for pin P1_10

PIO1_PIN11_SEC_MASK_R

Field PIO1_PIN11_SEC_MASK reader - Secure mask for pin P1_11

PIO1_PIN11_SEC_MASK_W

Field PIO1_PIN11_SEC_MASK writer - Secure mask for pin P1_11

PIO1_PIN12_SEC_MASK_R

Field PIO1_PIN12_SEC_MASK reader - Secure mask for pin P1_12

PIO1_PIN12_SEC_MASK_W

Field PIO1_PIN12_SEC_MASK writer - Secure mask for pin P1_12

PIO1_PIN13_SEC_MASK_R

Field PIO1_PIN13_SEC_MASK reader - Secure mask for pin P1_13

PIO1_PIN13_SEC_MASK_W

Field PIO1_PIN13_SEC_MASK writer - Secure mask for pin P1_13

PIO1_PIN14_SEC_MASK_R

Field PIO1_PIN14_SEC_MASK reader - Secure mask for pin P1_14

PIO1_PIN14_SEC_MASK_W

Field PIO1_PIN14_SEC_MASK writer - Secure mask for pin P1_14

PIO1_PIN15_SEC_MASK_R

Field PIO1_PIN15_SEC_MASK reader - Secure mask for pin P1_15

PIO1_PIN15_SEC_MASK_W

Field PIO1_PIN15_SEC_MASK writer - Secure mask for pin P1_15

PIO1_PIN16_SEC_MASK_R

Field PIO1_PIN16_SEC_MASK reader - Secure mask for pin P1_16

PIO1_PIN16_SEC_MASK_W

Field PIO1_PIN16_SEC_MASK writer - Secure mask for pin P1_16

PIO1_PIN17_SEC_MASK_R

Field PIO1_PIN17_SEC_MASK reader - Secure mask for pin P1_17

PIO1_PIN17_SEC_MASK_W

Field PIO1_PIN17_SEC_MASK writer - Secure mask for pin P1_17

PIO1_PIN18_SEC_MASK_R

Field PIO1_PIN18_SEC_MASK reader - Secure mask for pin P1_18

PIO1_PIN18_SEC_MASK_W

Field PIO1_PIN18_SEC_MASK writer - Secure mask for pin P1_18

PIO1_PIN19_SEC_MASK_R

Field PIO1_PIN19_SEC_MASK reader - Secure mask for pin P1_19

PIO1_PIN19_SEC_MASK_W

Field PIO1_PIN19_SEC_MASK writer - Secure mask for pin P1_19

PIO1_PIN20_SEC_MASK_R

Field PIO1_PIN20_SEC_MASK reader - Secure mask for pin P1_20

PIO1_PIN20_SEC_MASK_W

Field PIO1_PIN20_SEC_MASK writer - Secure mask for pin P1_20

PIO1_PIN21_SEC_MASK_R

Field PIO1_PIN21_SEC_MASK reader - Secure mask for pin P1_21

PIO1_PIN21_SEC_MASK_W

Field PIO1_PIN21_SEC_MASK writer - Secure mask for pin P1_21

PIO1_PIN22_SEC_MASK_R

Field PIO1_PIN22_SEC_MASK reader - Secure mask for pin P1_22

PIO1_PIN22_SEC_MASK_W

Field PIO1_PIN22_SEC_MASK writer - Secure mask for pin P1_22

PIO1_PIN23_SEC_MASK_R

Field PIO1_PIN23_SEC_MASK reader - Secure mask for pin P1_23

PIO1_PIN23_SEC_MASK_W

Field PIO1_PIN23_SEC_MASK writer - Secure mask for pin P1_23

PIO1_PIN24_SEC_MASK_R

Field PIO1_PIN24_SEC_MASK reader - Secure mask for pin P1_24

PIO1_PIN24_SEC_MASK_W

Field PIO1_PIN24_SEC_MASK writer - Secure mask for pin P1_24

PIO1_PIN25_SEC_MASK_R

Field PIO1_PIN25_SEC_MASK reader - Secure mask for pin P1_25

PIO1_PIN25_SEC_MASK_W

Field PIO1_PIN25_SEC_MASK writer - Secure mask for pin P1_25

PIO1_PIN26_SEC_MASK_R

Field PIO1_PIN26_SEC_MASK reader - Secure mask for pin P1_26

PIO1_PIN26_SEC_MASK_W

Field PIO1_PIN26_SEC_MASK writer - Secure mask for pin P1_26

PIO1_PIN27_SEC_MASK_R

Field PIO1_PIN27_SEC_MASK reader - Secure mask for pin P1_27

PIO1_PIN27_SEC_MASK_W

Field PIO1_PIN27_SEC_MASK writer - Secure mask for pin P1_27

PIO1_PIN28_SEC_MASK_R

Field PIO1_PIN28_SEC_MASK reader - Secure mask for pin P1_28

PIO1_PIN28_SEC_MASK_W

Field PIO1_PIN28_SEC_MASK writer - Secure mask for pin P1_28

PIO1_PIN29_SEC_MASK_R

Field PIO1_PIN29_SEC_MASK reader - Secure mask for pin P1_29

PIO1_PIN29_SEC_MASK_W

Field PIO1_PIN29_SEC_MASK writer - Secure mask for pin P1_29

PIO1_PIN30_SEC_MASK_R

Field PIO1_PIN30_SEC_MASK reader - Secure mask for pin P1_30

PIO1_PIN30_SEC_MASK_W

Field PIO1_PIN30_SEC_MASK writer - Secure mask for pin P1_30

PIO1_PIN31_SEC_MASK_R

Field PIO1_PIN31_SEC_MASK reader - Secure mask for pin P1_31

PIO1_PIN31_SEC_MASK_W

Field PIO1_PIN31_SEC_MASK writer - Secure mask for pin P1_31

R

Register SEC_GPIO_MASK1 reader

SEC_GPIO_MASK1_SPEC

Secure GPIO mask for port 1 pins.

W

Register SEC_GPIO_MASK1 writer

Enums

PIO1_PIN0_SEC_MASK_A

Secure mask for pin P1_0

PIO1_PIN1_SEC_MASK_A

Secure mask for pin P1_1

PIO1_PIN2_SEC_MASK_A

Secure mask for pin P1_2

PIO1_PIN3_SEC_MASK_A

Secure mask for pin P1_3

PIO1_PIN4_SEC_MASK_A

Secure mask for pin P1_4

PIO1_PIN5_SEC_MASK_A

Secure mask for pin P1_5

PIO1_PIN6_SEC_MASK_A

Secure mask for pin P1_6

PIO1_PIN7_SEC_MASK_A

Secure mask for pin P1_7

PIO1_PIN8_SEC_MASK_A

Secure mask for pin P1_8

PIO1_PIN9_SEC_MASK_A

Secure mask for pin P1_9

PIO1_PIN10_SEC_MASK_A

Secure mask for pin P1_10

PIO1_PIN11_SEC_MASK_A

Secure mask for pin P1_11

PIO1_PIN12_SEC_MASK_A

Secure mask for pin P1_12

PIO1_PIN13_SEC_MASK_A

Secure mask for pin P1_13

PIO1_PIN14_SEC_MASK_A

Secure mask for pin P1_14

PIO1_PIN15_SEC_MASK_A

Secure mask for pin P1_15

PIO1_PIN16_SEC_MASK_A

Secure mask for pin P1_16

PIO1_PIN17_SEC_MASK_A

Secure mask for pin P1_17

PIO1_PIN18_SEC_MASK_A

Secure mask for pin P1_18

PIO1_PIN19_SEC_MASK_A

Secure mask for pin P1_19

PIO1_PIN20_SEC_MASK_A

Secure mask for pin P1_20

PIO1_PIN21_SEC_MASK_A

Secure mask for pin P1_21

PIO1_PIN22_SEC_MASK_A

Secure mask for pin P1_22

PIO1_PIN23_SEC_MASK_A

Secure mask for pin P1_23

PIO1_PIN24_SEC_MASK_A

Secure mask for pin P1_24

PIO1_PIN25_SEC_MASK_A

Secure mask for pin P1_25

PIO1_PIN26_SEC_MASK_A

Secure mask for pin P1_26

PIO1_PIN27_SEC_MASK_A

Secure mask for pin P1_27

PIO1_PIN28_SEC_MASK_A

Secure mask for pin P1_28

PIO1_PIN29_SEC_MASK_A

Secure mask for pin P1_29

PIO1_PIN30_SEC_MASK_A

Secure mask for pin P1_30

PIO1_PIN31_SEC_MASK_A

Secure mask for pin P1_31