[−][src]Module lpc54606_pac::i2s0::cfg1
Configuration register 1 for the primary channel pair.
Structs
| DATALEN_W | Write proxy for field |
| DATAPAUSE_W | Write proxy for field |
| LEFTJUST_W | Write proxy for field |
| MAINENABLE_W | Write proxy for field |
| MODE_W | Write proxy for field |
| MSTSLVCFG_W | Write proxy for field |
| ONECHANNEL_W | Write proxy for field |
| PAIRCOUNT_W | Write proxy for field |
| PDMDATA_W | Write proxy for field |
| RIGHTLOW_W | Write proxy for field |
| SCK_POL_W | Write proxy for field |
| WS_POL_W | Write proxy for field |
Enums
| DATAPAUSE_A | Data flow Pause. Allows pausing data flow between the I2S serializer/deserializer and the FIFO. This could be done in order to change streams, or while restarting after a data underflow or overflow. When paused, FIFO operations can be done without corrupting data that is in the process of being sent or received. Once a data pause has been requested, the interface may need to complete sending data that was in progress before interrupting the flow of data. Software must check that the pause is actually in effect before taking action. This is done by monitoring the DATAPAUSED flag in the STAT register. When DATAPAUSE is cleared, data transfer will resume at the beginning of the next frame. |
| LEFTJUST_A | Left Justify data. |
| MAINENABLE_A | Main enable for I 2S function in this Flexcomm |
| MODE_A | Selects the basic I2S operating mode. Other configurations modify this to obtain all supported cases. See Formats and modes for examples. |
| MSTSLVCFG_A | Master / slave configuration selection, determining how SCK and WS are used by all channel pairs in this Flexcomm. |
| ONECHANNEL_A | Single channel mode. Applies to both transmit and receive. This configuration bit applies only to the first I2S channel pair. Other channel pairs may select this mode independently in their separate CFG1 registers. |
| PAIRCOUNT_A | Provides the number of I2S channel pairs in this Flexcomm This is a read-only field whose value may be different in other Flexcomms. 00 = there is 1 I2S channel pair in this Flexcomm. 01 = there are 2 I2S channel pairs in this Flexcomm. 10 = there are 3 I2S channel pairs in this Flexcomm. 11 = there are 4 I2S channel pairs in this Flexcomm. |
| PDMDATA_A | PDM Data selection. This bit controls the data source for I2S transmit, and cannot be set in Rx mode. This bit only has an effect if the device the Flexcomm resides in includes a D-Mic subsystem. For the LPC5411x, this bit applies only to Flexcomm 7. |
| RIGHTLOW_A | Right channel data is in the Low portion of FIFO data. Essentially, this swaps left and right channel data as it is transferred to or from the FIFO. This bit is not used if the data width is greater than 24 bits or if PDMDATA = 1. Note that if the ONECHANNEL field (bit 10 of this register) = 1, the one channel to be used is the nominally the left channel. POSITION can still place that data in the frame where right channel data is normally located. if all enabled channel pairs have ONECHANNEL = 1, then RIGHTLOW = 1 is not allowed. |
| SCK_POL_A | SCK polarity. |
| WS_POL_A | WS polarity. |
Type Definitions
| DATALEN_R | Reader of field |
| DATAPAUSE_R | Reader of field |
| LEFTJUST_R | Reader of field |
| MAINENABLE_R | Reader of field |
| MODE_R | Reader of field |
| MSTSLVCFG_R | Reader of field |
| ONECHANNEL_R | Reader of field |
| PAIRCOUNT_R | Reader of field |
| PDMDATA_R | Reader of field |
| R | Reader of register CFG1 |
| RIGHTLOW_R | Reader of field |
| SCK_POL_R | Reader of field |
| W | Writer for register CFG1 |
| WS_POL_R | Reader of field |