[−][src]Module lpc54606_pac::dma0::channel::xfercfg

Transfer configuration register for DMA channel .

Structs

CFGVALID_W	Write proxy for field `CFGVALID`
CLRTRIG_W	Write proxy for field `CLRTRIG`
DSTINC_W	Write proxy for field `DSTINC`
RELOAD_W	Write proxy for field `RELOAD`
SETINTA_W	Write proxy for field `SETINTA`
SETINTB_W	Write proxy for field `SETINTB`
SRCINC_W	Write proxy for field `SRCINC`
SWTRIG_W	Write proxy for field `SWTRIG`
WIDTH_W	Write proxy for field `WIDTH`
XFERCOUNT_W	Write proxy for field `XFERCOUNT`

CFGVALID_A	Configuration Valid flag. This bit indicates whether the current channel descriptor is valid and can potentially be acted upon, if all other activation criteria are fulfilled.
CLRTRIG_A	Clear Trigger.
DSTINC_A	Determines whether the destination address is incremented for each DMA transfer.
RELOAD_A	Indicates whether the channel's control structure will be reloaded when the current descriptor is exhausted. Reloading allows ping-pong and linked transfers.
SETINTA_A	Set Interrupt flag A for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
SETINTB_A	Set Interrupt flag B for this channel. There is no hardware distinction between interrupt A and B. They can be used by software to assist with more complex descriptor usage. By convention, interrupt A may be used when only one interrupt flag is needed.
SRCINC_A	Determines whether the source address is incremented for each DMA transfer.
SWTRIG_A	Software Trigger.
WIDTH_A	Transfer width used for this DMA channel.