Module lpc43xx::usart0

USART0_2_3

Modules

acr	Auto-baud Control Register. Contains controls for the auto-baud feature.
dll	Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
dlm	Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
fcr	FIFO Control Register. Controls USART FIFO usage and modes.
fdr	Fractional Divider Register. Generates a clock input for the baud rate divider.
hden	Half-duplex enable Register
icr	IrDA control register (USART3 only)
ier	Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0).
iir	Interrupt ID Register. Identifies which interrupt(s) are pending.
lcr	Line Control Register. Contains controls for frame formatting and break generation.
lsr	Line Status Register. Contains flags for transmit and receive status, including line errors.
osr	Oversampling Register. Controls the degree of oversampling during each bit time.
rbr	Receiver Buffer Register. Contains the next received character to be read (DLAB = 0).
rs485adrmatch	RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
rs485ctrl	RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
rs485dly	RS-485/EIA-485 direction control delay.
scictrl	Smart card interface control register
scr	Scratch Pad Register. Eight-bit temporary storage for software.
syncctrl	Synchronous mode control register.
ter	Transmit Enable Register. Turns off USART transmitter for use with software flow control.
thr	Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0).

Structs

ACR	Auto-baud Control Register. Contains controls for the auto-baud feature.
DLL	Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
DLM	Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB = 1).
FCR	FIFO Control Register. Controls USART FIFO usage and modes.
FDR	Fractional Divider Register. Generates a clock input for the baud rate divider.
HDEN	Half-duplex enable Register
ICR	IrDA control register (USART3 only)
IER	Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts (DLAB = 0).
IIR	Interrupt ID Register. Identifies which interrupt(s) are pending.
LCR	Line Control Register. Contains controls for frame formatting and break generation.
LSR	Line Status Register. Contains flags for transmit and receive status, including line errors.
OSR	Oversampling Register. Controls the degree of oversampling during each bit time.
RBR	Receiver Buffer Register. Contains the next received character to be read (DLAB = 0).
RS485ADRMATCH	RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
RS485CTRL	RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
RS485DLY	RS-485/EIA-485 direction control delay.
RegisterBlock	Register block
SCICTRL	Smart card interface control register
SCR	Scratch Pad Register. Eight-bit temporary storage for software.
SYNCCTRL	Synchronous mode control register.
TER	Transmit Enable Register. Turns off USART transmitter for use with software flow control.
THR	Transmit Holding Register. The next character to be transmitted is written here (DLAB = 0).