Module lpc43xx::i2s0
[−]
[src]
I2S interface
Modules
dai |
I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. |
dao |
I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. |
dma1 |
I2S DMA Configuration Register 1. Contains control information for DMA request 1. |
dma2 |
I2S DMA Configuration Register 2. Contains control information for DMA request 2. |
irq |
I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. |
rxbitrate |
I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. |
rxfifo |
I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. |
rxmode |
I2S Receive mode control. |
rxrate |
I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. |
state |
I2S Status Feedback Register. Contains status information about the I2S interface. |
txbitrate |
I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. |
txfifo |
I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. |
txmode |
I2S Transmit mode control. |
txrate |
I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. |
Structs
DAI |
I2S Digital Audio Input Register. Contains control bits for the I2S receive channel. |
DAO |
I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel. |
DMA1 |
I2S DMA Configuration Register 1. Contains control information for DMA request 1. |
DMA2 |
I2S DMA Configuration Register 2. Contains control information for DMA request 2. |
IRQ |
I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated. |
RXBITRATE |
I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock. |
RXFIFO |
I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO. |
RXMODE |
I2S Receive mode control. |
RXRATE |
I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. |
RegisterBlock |
Register block |
STATE |
I2S Status Feedback Register. Contains status information about the I2S interface. |
TXBITRATE |
I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock. |
TXFIFO |
I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO. |
TXMODE |
I2S Transmit mode control. |
TXRATE |
I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK. |