Module lpc176x_5x::uart0

UART0/2/3

Modules

acr	Auto-baud Control Register. Contains controls for the auto-baud feature.
dll	Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
dlm	Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
fcr	FIFO Control Register. Controls UART FIFO usage and modes.
fdr	Fractional Divider Register. Generates a clock input for the baud rate divider.
ier	Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).
iir	Interrupt ID Register. Identifies which interrupt(s) are pending.
lcr	Line Control Register. Contains controls for frame formatting and break generation.
lsr	Line Status Register. Contains flags for transmit and receive status, including line errors.
rbr	Receiver Buffer Register. Contains the next received character to be read (DLAB =0).
rs485ctrl	RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
rs485adrmatch	RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
rs485dly	RS-485/EIA-485 direction control delay.
scr	Scratch Pad Register. 8-bit temporary storage for software.
ter	Transmit Enable Register. Turns off UART transmitter for use with software flow control.
thr	Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0).

Structs

ACR	Auto-baud Control Register. Contains controls for the auto-baud feature.
DLL	Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
DLM	Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
FCR	FIFO Control Register. Controls UART FIFO usage and modes.
FDR	Fractional Divider Register. Generates a clock input for the baud rate divider.
IER	Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).
IIR	Interrupt ID Register. Identifies which interrupt(s) are pending.
LCR	Line Control Register. Contains controls for frame formatting and break generation.
LSR	Line Status Register. Contains flags for transmit and receive status, including line errors.
RBR	Receiver Buffer Register. Contains the next received character to be read (DLAB =0).
RS485CTRL	RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
RS485ADRMATCH	RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
RS485DLY	RS-485/EIA-485 direction control delay.
RegisterBlock	Register block
SCR	Scratch Pad Register. 8-bit temporary storage for software.
TER	Transmit Enable Register. Turns off UART transmitter for use with software flow control.
THR	Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0).

Unions

DLL_UNION	Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1). Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0). Receiver Buffer Register. Contains the next received character to be read (DLAB =0).
DLM_UNION	Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0). Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
FCR_UNION	FIFO Control Register. Controls UART FIFO usage and modes. Interrupt ID Register. Identifies which interrupt(s) are pending.