Module lpc13xx::syscon
[−]
[src]
Product name title=UM10375 Chapter title=LPC13xx System configuration Modification date=4/4/2011 Major revision=2 Minor revision=2
Modules
| bodctrl |
BOD control |
| clkoutclksel |
CLKOUT clock source select |
| clkoutdiv |
CLKOUT clock divider |
| clkoutuen |
CLKOUT clock source update enable |
| device_id |
Device ID |
| ircctrl |
IRC control |
| mainclksel |
Main clock source select |
| mainclkuen |
Main clock source update enable |
| pdawakecfg |
Power-down states after wake-up from Deep-sleep mode |
| pdruncfg |
Power-down configuration register |
| pdsleepcfg |
Power-down states in Deep-sleep mode |
| pioporcap0 |
POR captured PIO status 0 |
| pioporcap1 |
POR captured PIO status 1 |
| presetctrl |
Peripheral reset control |
| ssp0clkdiv |
SSP clock divder |
| ssp1clkdiv |
SPISP1 clock divder |
| startaprp0 |
Start logic edge control register 0; bottom 32 interrupts |
| startaprp1 |
Start logic edge control register 1; top 8 interrupts |
| starterp0 |
Start logic signal enable register 0; bottom 32 interrupts |
| starterp1 |
Start logic signal enable register 1; top 8 interrupts |
| startrsrp0clr |
Start logic reset register 0; bottom 32 interrupts |
| startrsrp1clr |
Start logic reset register 1; top 8 interrupts |
| startsrp0 |
Start logic status register 0; bottom 32 interrupts |
| startsrp1 |
Start logic status register 1; top 8 interrupts |
| sysahbclkctrl |
System AHB clock control |
| sysahbclkdiv |
System AHB clock divider |
| sysmemremap |
System memory remap |
| sysoscctrl |
System oscillator control |
| syspllclksel |
System PLL clock source select |
| syspllclkuen |
System PLL clock source update enable |
| syspllctrl |
System PLL control |
| syspllstat |
System PLL status |
| sysresstat |
System reset status register |
| systckcal |
System tick counter calibration |
| systickclkdiv |
SYSTICK clock divder |
| traceclkdiv |
ARM trace clock divider |
| uartclkdiv |
UART clock divder |
| usbclkdiv |
USB clock source divider |
| usbclksel |
USB clock source select |
| usbclkuen |
USB clock source update enable |
| usbpllclksel |
USB PLL clock source select |
| usbpllclkuen |
USB PLL clock source update enable |
| usbpllctrl |
USB PLL control |
| usbpllstat |
USB PLL status |
| wdtclkdiv |
WDT clock divider |
| wdtclksel |
WDT clock source select |
| wdtclkuen |
WDT clock source update enable |
| wdtoscctrl |
Watchdog oscillator control |
Structs
| BODCTRL |
BOD control |
| CLKOUTCLKSEL |
CLKOUT clock source select |
| CLKOUTDIV |
CLKOUT clock divider |
| CLKOUTUEN |
CLKOUT clock source update enable |
| DEVICE_ID |
Device ID |
| IRCCTRL |
IRC control |
| MAINCLKSEL |
Main clock source select |
| MAINCLKUEN |
Main clock source update enable |
| PDAWAKECFG |
Power-down states after wake-up from Deep-sleep mode |
| PDRUNCFG |
Power-down configuration register |
| PDSLEEPCFG |
Power-down states in Deep-sleep mode |
| PIOPORCAP0 |
POR captured PIO status 0 |
| PIOPORCAP1 |
POR captured PIO status 1 |
| PRESETCTRL |
Peripheral reset control |
| RegisterBlock |
Register block |
| SSP0CLKDIV |
SSP clock divder |
| SSP1CLKDIV |
SPISP1 clock divder |
| STARTAPRP0 |
Start logic edge control register 0; bottom 32 interrupts |
| STARTAPRP1 |
Start logic edge control register 1; top 8 interrupts |
| STARTERP0 |
Start logic signal enable register 0; bottom 32 interrupts |
| STARTERP1 |
Start logic signal enable register 1; top 8 interrupts |
| STARTRSRP0CLR |
Start logic reset register 0; bottom 32 interrupts |
| STARTRSRP1CLR |
Start logic reset register 1; top 8 interrupts |
| STARTSRP0 |
Start logic status register 0; bottom 32 interrupts |
| STARTSRP1 |
Start logic status register 1; top 8 interrupts |
| SYSAHBCLKCTRL |
System AHB clock control |
| SYSAHBCLKDIV |
System AHB clock divider |
| SYSMEMREMAP |
System memory remap |
| SYSOSCCTRL |
System oscillator control |
| SYSPLLCLKSEL |
System PLL clock source select |
| SYSPLLCLKUEN |
System PLL clock source update enable |
| SYSPLLCTRL |
System PLL control |
| SYSPLLSTAT |
System PLL status |
| SYSRESSTAT |
System reset status register |
| SYSTCKCAL |
System tick counter calibration |
| SYSTICKCLKDIV |
SYSTICK clock divder |
| TRACECLKDIV |
ARM trace clock divider |
| UARTCLKDIV |
UART clock divder |
| USBCLKDIV |
USB clock source divider |
| USBCLKSEL |
USB clock source select |
| USBCLKUEN |
USB clock source update enable |
| USBPLLCLKSEL |
USB PLL clock source select |
| USBPLLCLKUEN |
USB PLL clock source update enable |
| USBPLLCTRL |
USB PLL control |
| USBPLLSTAT |
USB PLL status |
| WDTCLKDIV |
WDT clock divider |
| WDTCLKSEL |
WDT clock source select |
| WDTCLKUEN |
WDT clock source update enable |
| WDTOSCCTRL |
Watchdog oscillator control |