[−][src]Module lpc11xx::syscon
System Configuration Block
Modules
| bodctrl | BOD control |
| clkoutclkdiv | CLKOUT clock divider |
| clkoutclksel | CLKOUT clock source select |
| clkoutuen | CLKOUT clock source update enable |
| device_id | Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L |
| ircctrl | IRC control |
| mainclksel | Main clock source select |
| mainclkuen | Main clock source update enable |
| nmisrc | NMI source selection |
| pdawakecfg | Power-down states after wake-up from Deep-sleep mode |
| pdruncfg | Power-down configuration register |
| pdsleepcfg | Power-down states in Deep-sleep mode |
| pioporcap0 | POR captured PIO status 0 |
| pioporcap1 | POR captured PIO status 1 |
| presetctrl | Peripheral reset control |
| ssp0clkdiv | SPI0 clock divider |
| ssp1clkdiv | SPI1 clock divder |
| startaprp0 | Start logic edge control register 0 |
| starterp0 | Start logic signal enable register 0 |
| startrsrp0clr | Start logic reset register 0 |
| startsrp0 | Start logic status register 0 |
| sysahbclkctrl | System AHB clock control |
| sysahbclkdiv | System AHB clock divider |
| sysmemremap | System memory remap |
| sysoscctrl | System oscillator control |
| syspllclksel | System PLL clock source select |
| syspllclkuen | System PLL clock source update enable |
| syspllctrl | System PLL control |
| syspllstat | System PLL status |
| sysrststat | System reset status register |
| systckcal | System tick counter calibration |
| uartclkdiv | UART clock divder |
| wdtclkdiv | WDT clock divider |
| wdtclksel | WDT clock source select |
| wdtclkuen | WDT clock source update enable |
| wdtoscctrl | Watchdog oscillator control |
Structs
| RegisterBlock | Register block |
Type Definitions
| BODCTRL | BOD control |
| CLKOUTCLKDIV | CLKOUT clock divider |
| CLKOUTCLKSEL | CLKOUT clock source select |
| CLKOUTUEN | CLKOUT clock source update enable |
| DEVICE_ID | Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L |
| IRCCTRL | IRC control |
| MAINCLKSEL | Main clock source select |
| MAINCLKUEN | Main clock source update enable |
| NMISRC | NMI source selection |
| PDAWAKECFG | Power-down states after wake-up from Deep-sleep mode |
| PDRUNCFG | Power-down configuration register |
| PDSLEEPCFG | Power-down states in Deep-sleep mode |
| PIOPORCAP0 | POR captured PIO status 0 |
| PIOPORCAP1 | POR captured PIO status 1 |
| PRESETCTRL | Peripheral reset control |
| SSP0CLKDIV | SPI0 clock divider |
| SSP1CLKDIV | SPI1 clock divder |
| STARTAPRP0 | Start logic edge control register 0 |
| STARTERP0 | Start logic signal enable register 0 |
| STARTRSRP0CLR | Start logic reset register 0 |
| STARTSRP0 | Start logic status register 0 |
| SYSAHBCLKCTRL | System AHB clock control |
| SYSAHBCLKDIV | System AHB clock divider |
| SYSMEMREMAP | System memory remap |
| SYSOSCCTRL | System oscillator control |
| SYSPLLCLKSEL | System PLL clock source select |
| SYSPLLCLKUEN | System PLL clock source update enable |
| SYSPLLCTRL | System PLL control |
| SYSPLLSTAT | System PLL status |
| SYSRSTSTAT | System reset status register |
| SYSTCKCAL | System tick counter calibration |
| UARTCLKDIV | UART clock divder |
| WDTCLKDIV | WDT clock divider |
| WDTCLKSEL | WDT clock source select |
| WDTCLKUEN | WDT clock source update enable |
| WDTOSCCTRL | Watchdog oscillator control |