Module lpc11xx::i2c

Inter-Integrated Circuit (I²C) Controller

Modules

adr	I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address
adr0	I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address
conclr	I2C Control Clear Register.
conset	I2C Control Set Register.
dat	I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register
data_buffer	Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus
mask	I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)
mmctrl	Monitor mode control register
sclh	SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock
scll	SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode
stat	I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed

Structs

RegisterBlock

Register block

Type Definitions

ADR	I2C Slave Address Register 1. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address
ADR0	I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address
CONCLR	I2C Control Clear Register.
CONSET	I2C Control Set Register.
DAT	I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register
DATA_BUFFER	Data buffer register. The contents of the 8 MSBs of the I2DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus
MASK	I2C Slave address mask register 0. This mask register is associated with I2ADR0 to determine an address match. The mask register has no effect when comparing to the General Call address (0000000)
MMCTRL	Monitor mode control register
SCLH	SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock
SCLL	SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. I2nSCLL and I2nSCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode
STAT	I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed