[−][src]Module lpc11xx::ct32b0
32-bit Counter/Timer
Modules
ccr | Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place |
cr | Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input |
ctcr | Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting |
emr | External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0] |
ir | Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending |
mcr | Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs |
mr | Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC |
pc | Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface |
pr | Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC |
pwmc | PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0] |
tc | Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR |
tcr | Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR |
Structs
CCR | Capture Control Register (CCR). The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place |
CR | Capture Register (CR). CR is loaded with the value of TC when there is an event on the CT16Bn_CAPm input |
CTCR | Count Control Register (CTCR). The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting |
EMR | External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0] |
IR | Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending |
MCR | Match Control Register (MCR). The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs |
MR | Match Register. MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC |
PC | Prescale Counter (PC). The 32-bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface |
PR | Prescale Register (PR). When the Prescale Counter (below) is equal to this value, the next clock increments the TC and clears the PC |
PWMC | PWM Control Register (PWMCON). The PWMCON enables PWM mode for the external match pins CT32B0_MAT[3:0] |
RegisterBlock | Register block |
TC | Timer Counter (TC). The 32-bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR |
TCR | Timer Control Register (TCR). The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR |