Expand description
USART
Modules
Auto-baud Control Register. Contains controls for the auto-baud feature.
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
FIFO Control Register. Controls USART FIFO usage and modes.
Fractional Divider Register. Generates a clock input for the baud rate divider.
Half duplex enable register.
IrDA Control Register. Enables and configures the IrDA (remote control) mode.
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)
Interrupt ID Register. Identifies which interrupt(s) are pending.
Line Control Register. Contains controls for frame formatting and break generation.
Line Status Register. Contains flags for transmit and receive status, including line errors.
Modem Control Register.
Modem Status Register.
Oversampling Register. Controls the degree of oversampling during each bit time.
Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
RS-485/EIA-485 direction control delay.
Smart Card Interface Control register. Enables and configures the Smart Card Interface feature.
Scratch Pad Register. Eight-bit temporary storage for software.
Synchronous mode control register.
Transmit Enable Register. Turns off USART transmitter for use with software flow control.
Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)
Structs
Auto-baud Control Register. Contains controls for the auto-baud feature.
Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1)
FIFO Control Register. Controls USART FIFO usage and modes.
Fractional Divider Register. Generates a clock input for the baud rate divider.
Half duplex enable register.
IrDA Control Register. Enables and configures the IrDA (remote control) mode.
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0)
Interrupt ID Register. Identifies which interrupt(s) are pending.
Line Control Register. Contains controls for frame formatting and break generation.
Line Status Register. Contains flags for transmit and receive status, including line errors.
Modem Control Register.
Modem Status Register.
Oversampling Register. Controls the degree of oversampling during each bit time.
Receiver Buffer Register. Contains the next received character to be read. (DLAB=0)
RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
RS-485/EIA-485 direction control delay.
Register block
Smart Card Interface Control register. Enables and configures the Smart Card Interface feature.
Scratch Pad Register. Eight-bit temporary storage for software.
Synchronous mode control register.
Transmit Enable Register. Turns off USART transmitter for use with software flow control.
Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0)