Module circuits

Macros

• wire
  Creates a wire with the same variable name and gate name.

Structs

• Bus
  Data structure that helps with managing buses, it allows you to connect &[GateIndex] to it as well as providing a &[GateIndex] to connect to other components.
• IOBuffer
  Data structure used to represent a piece of RAM that can be easily read and written to from Rust.
• Wire
  Data structure that helps with connecting wires to many different components.
• WordInput
  Data Structure that allows you to easily manage a group of LeverHandles.

Functions

• adder
  Returns the output of a ripple carry adder.
• aluish
  Returns the output of an ALU which can only add and subtract.
• bus_multiplexer
  Returns one of the inputs selected by address. Conceptually it is a combination of multiplexers, one for each I/O bit.
• constant
  Returns a Vec of ON or OFF values representing the bits of any Copy + Sized + ’static value.
• counter
  Returns the output of a counter. The output width will be the same as the provided input.
• d_flip_flop
  Returns the Q output of a D flip-flop.
• decoder
  Returns the output of a decoder. The output width will be 2^address.len().
• io_register
  Returns a pair representing an “updated” bit and the output of a register respectively, Whenever a write happens to the register, the “updated” bit is set,
• multiplexer
  Returns the output of a multiplexer. which selects one of the inputs by address. If inputs is not big enough to cover the whole address space, it will get filled by OFF.
• ones
  Returns a Vec of size n full of ON.
• ram
  Returns the output of a piece of RAM addressed by address.
• register
  Returns the output of a register. The output width will be the same as the provided input.
• rom
  Returns the output of a piece of addressable ROM filled with data. If data is not long enough to fill the entire address space, it will be filled with OFF.
• sr_latch
  Returns the Q output of an SR latch.
• zeros
  Returns a Vec of size n full of OFF.