Module llvmint::gcc_names [−] [src]

Listing of the corresponding name(s) of many GCC intrinsics, for reference/search purposes.

__builtin_HEXAGON_A2_abs: hexagon::A2_abs
__builtin_HEXAGON_A2_absp: hexagon::A2_absp
__builtin_HEXAGON_A2_abssat: hexagon::A2_abssat
__builtin_HEXAGON_A2_add: hexagon::A2_add
__builtin_HEXAGON_A2_addh_h16_hh: hexagon::A2_addh_h16_hh
__builtin_HEXAGON_A2_addh_h16_hl: hexagon::A2_addh_h16_hl
__builtin_HEXAGON_A2_addh_h16_lh: hexagon::A2_addh_h16_lh
__builtin_HEXAGON_A2_addh_h16_ll: hexagon::A2_addh_h16_ll
__builtin_HEXAGON_A2_addh_h16_sat_hh: hexagon::A2_addh_h16_sat_hh
__builtin_HEXAGON_A2_addh_h16_sat_hl: hexagon::A2_addh_h16_sat_hl
__builtin_HEXAGON_A2_addh_h16_sat_lh: hexagon::A2_addh_h16_sat_lh
__builtin_HEXAGON_A2_addh_h16_sat_ll: hexagon::A2_addh_h16_sat_ll
__builtin_HEXAGON_A2_addh_l16_hl: hexagon::A2_addh_l16_hl
__builtin_HEXAGON_A2_addh_l16_ll: hexagon::A2_addh_l16_ll
__builtin_HEXAGON_A2_addh_l16_sat_hl: hexagon::A2_addh_l16_sat_hl
__builtin_HEXAGON_A2_addh_l16_sat_ll: hexagon::A2_addh_l16_sat_ll
__builtin_HEXAGON_A2_addi: hexagon::A2_addi
__builtin_HEXAGON_A2_addp: hexagon::A2_addp
__builtin_HEXAGON_A2_addpsat: hexagon::A2_addpsat
__builtin_HEXAGON_A2_addsat: hexagon::A2_addsat
__builtin_HEXAGON_A2_addsp: hexagon::A2_addsp
__builtin_HEXAGON_A2_and: hexagon::A2_and
__builtin_HEXAGON_A2_andir: hexagon::A2_andir
__builtin_HEXAGON_A2_andp: hexagon::A2_andp
__builtin_HEXAGON_A2_aslh: hexagon::A2_aslh
__builtin_HEXAGON_A2_asrh: hexagon::A2_asrh
__builtin_HEXAGON_A2_combine_hh: hexagon::A2_combine_hh
__builtin_HEXAGON_A2_combine_hl: hexagon::A2_combine_hl
__builtin_HEXAGON_A2_combine_lh: hexagon::A2_combine_lh
__builtin_HEXAGON_A2_combine_ll: hexagon::A2_combine_ll
__builtin_HEXAGON_A2_combineii: hexagon::A2_combineii
__builtin_HEXAGON_A2_combinew: hexagon::A2_combinew
__builtin_HEXAGON_A2_max: hexagon::A2_max
__builtin_HEXAGON_A2_maxp: hexagon::A2_maxp
__builtin_HEXAGON_A2_maxu: hexagon::A2_maxu
__builtin_HEXAGON_A2_maxup: hexagon::A2_maxup
__builtin_HEXAGON_A2_min: hexagon::A2_min
__builtin_HEXAGON_A2_minp: hexagon::A2_minp
__builtin_HEXAGON_A2_minu: hexagon::A2_minu
__builtin_HEXAGON_A2_minup: hexagon::A2_minup
__builtin_HEXAGON_A2_neg: hexagon::A2_neg
__builtin_HEXAGON_A2_negp: hexagon::A2_negp
__builtin_HEXAGON_A2_negsat: hexagon::A2_negsat
__builtin_HEXAGON_A2_not: hexagon::A2_not
__builtin_HEXAGON_A2_notp: hexagon::A2_notp
__builtin_HEXAGON_A2_or: hexagon::A2_or
__builtin_HEXAGON_A2_orir: hexagon::A2_orir
__builtin_HEXAGON_A2_orp: hexagon::A2_orp
__builtin_HEXAGON_A2_roundsat: hexagon::A2_roundsat
__builtin_HEXAGON_A2_sat: hexagon::A2_sat
__builtin_HEXAGON_A2_satb: hexagon::A2_satb
__builtin_HEXAGON_A2_sath: hexagon::A2_sath
__builtin_HEXAGON_A2_satub: hexagon::A2_satub
__builtin_HEXAGON_A2_satuh: hexagon::A2_satuh
__builtin_HEXAGON_A2_sub: hexagon::A2_sub
__builtin_HEXAGON_A2_subh_h16_hh: hexagon::A2_subh_h16_hh
__builtin_HEXAGON_A2_subh_h16_hl: hexagon::A2_subh_h16_hl
__builtin_HEXAGON_A2_subh_h16_lh: hexagon::A2_subh_h16_lh
__builtin_HEXAGON_A2_subh_h16_ll: hexagon::A2_subh_h16_ll
__builtin_HEXAGON_A2_subh_h16_sat_hh: hexagon::A2_subh_h16_sat_hh
__builtin_HEXAGON_A2_subh_h16_sat_hl: hexagon::A2_subh_h16_sat_hl
__builtin_HEXAGON_A2_subh_h16_sat_lh: hexagon::A2_subh_h16_sat_lh
__builtin_HEXAGON_A2_subh_h16_sat_ll: hexagon::A2_subh_h16_sat_ll
__builtin_HEXAGON_A2_subh_l16_hl: hexagon::A2_subh_l16_hl
__builtin_HEXAGON_A2_subh_l16_ll: hexagon::A2_subh_l16_ll
__builtin_HEXAGON_A2_subh_l16_sat_hl: hexagon::A2_subh_l16_sat_hl
__builtin_HEXAGON_A2_subh_l16_sat_ll: hexagon::A2_subh_l16_sat_ll
__builtin_HEXAGON_A2_subp: hexagon::A2_subp
__builtin_HEXAGON_A2_subri: hexagon::A2_subri
__builtin_HEXAGON_A2_subsat: hexagon::A2_subsat
__builtin_HEXAGON_A2_svaddh: hexagon::A2_svaddh
__builtin_HEXAGON_A2_svaddhs: hexagon::A2_svaddhs
__builtin_HEXAGON_A2_svadduhs: hexagon::A2_svadduhs
__builtin_HEXAGON_A2_svavgh: hexagon::A2_svavgh
__builtin_HEXAGON_A2_svavghs: hexagon::A2_svavghs
__builtin_HEXAGON_A2_svnavgh: hexagon::A2_svnavgh
__builtin_HEXAGON_A2_svsubh: hexagon::A2_svsubh
__builtin_HEXAGON_A2_svsubhs: hexagon::A2_svsubhs
__builtin_HEXAGON_A2_svsubuhs: hexagon::A2_svsubuhs
__builtin_HEXAGON_A2_swiz: hexagon::A2_swiz
__builtin_HEXAGON_A2_sxtb: hexagon::A2_sxtb
__builtin_HEXAGON_A2_sxth: hexagon::A2_sxth
__builtin_HEXAGON_A2_sxtw: hexagon::A2_sxtw
__builtin_HEXAGON_A2_tfr: hexagon::A2_tfr
__builtin_HEXAGON_A2_tfrih: hexagon::A2_tfrih
__builtin_HEXAGON_A2_tfril: hexagon::A2_tfril
__builtin_HEXAGON_A2_tfrp: hexagon::A2_tfrp
__builtin_HEXAGON_A2_tfrpi: hexagon::A2_tfrpi
__builtin_HEXAGON_A2_tfrsi: hexagon::A2_tfrsi
__builtin_HEXAGON_A2_vabsh: hexagon::A2_vabsh
__builtin_HEXAGON_A2_vabshsat: hexagon::A2_vabshsat
__builtin_HEXAGON_A2_vabsw: hexagon::A2_vabsw
__builtin_HEXAGON_A2_vabswsat: hexagon::A2_vabswsat
__builtin_HEXAGON_A2_vaddb_map: hexagon::A2_vaddb_map
__builtin_HEXAGON_A2_vaddh: hexagon::A2_vaddh
__builtin_HEXAGON_A2_vaddhs: hexagon::A2_vaddhs
__builtin_HEXAGON_A2_vaddub: hexagon::A2_vaddub
__builtin_HEXAGON_A2_vaddubs: hexagon::A2_vaddubs
__builtin_HEXAGON_A2_vadduhs: hexagon::A2_vadduhs
__builtin_HEXAGON_A2_vaddw: hexagon::A2_vaddw
__builtin_HEXAGON_A2_vaddws: hexagon::A2_vaddws
__builtin_HEXAGON_A2_vavgh: hexagon::A2_vavgh
__builtin_HEXAGON_A2_vavghcr: hexagon::A2_vavghcr
__builtin_HEXAGON_A2_vavghr: hexagon::A2_vavghr
__builtin_HEXAGON_A2_vavgub: hexagon::A2_vavgub
__builtin_HEXAGON_A2_vavgubr: hexagon::A2_vavgubr
__builtin_HEXAGON_A2_vavguh: hexagon::A2_vavguh
__builtin_HEXAGON_A2_vavguhr: hexagon::A2_vavguhr
__builtin_HEXAGON_A2_vavguw: hexagon::A2_vavguw
__builtin_HEXAGON_A2_vavguwr: hexagon::A2_vavguwr
__builtin_HEXAGON_A2_vavgw: hexagon::A2_vavgw
__builtin_HEXAGON_A2_vavgwcr: hexagon::A2_vavgwcr
__builtin_HEXAGON_A2_vavgwr: hexagon::A2_vavgwr
__builtin_HEXAGON_A2_vcmpbeq: hexagon::A2_vcmpbeq
__builtin_HEXAGON_A2_vcmpbgtu: hexagon::A2_vcmpbgtu
__builtin_HEXAGON_A2_vcmpheq: hexagon::A2_vcmpheq
__builtin_HEXAGON_A2_vcmphgt: hexagon::A2_vcmphgt
__builtin_HEXAGON_A2_vcmphgtu: hexagon::A2_vcmphgtu
__builtin_HEXAGON_A2_vcmpweq: hexagon::A2_vcmpweq
__builtin_HEXAGON_A2_vcmpwgt: hexagon::A2_vcmpwgt
__builtin_HEXAGON_A2_vcmpwgtu: hexagon::A2_vcmpwgtu
__builtin_HEXAGON_A2_vconj: hexagon::A2_vconj
__builtin_HEXAGON_A2_vmaxb: hexagon::A2_vmaxb
__builtin_HEXAGON_A2_vmaxh: hexagon::A2_vmaxh
__builtin_HEXAGON_A2_vmaxub: hexagon::A2_vmaxub
__builtin_HEXAGON_A2_vmaxuh: hexagon::A2_vmaxuh
__builtin_HEXAGON_A2_vmaxuw: hexagon::A2_vmaxuw
__builtin_HEXAGON_A2_vmaxw: hexagon::A2_vmaxw
__builtin_HEXAGON_A2_vminb: hexagon::A2_vminb
__builtin_HEXAGON_A2_vminh: hexagon::A2_vminh
__builtin_HEXAGON_A2_vminub: hexagon::A2_vminub
__builtin_HEXAGON_A2_vminuh: hexagon::A2_vminuh
__builtin_HEXAGON_A2_vminuw: hexagon::A2_vminuw
__builtin_HEXAGON_A2_vminw: hexagon::A2_vminw
__builtin_HEXAGON_A2_vnavgh: hexagon::A2_vnavgh
__builtin_HEXAGON_A2_vnavghcr: hexagon::A2_vnavghcr
__builtin_HEXAGON_A2_vnavghr: hexagon::A2_vnavghr
__builtin_HEXAGON_A2_vnavgw: hexagon::A2_vnavgw
__builtin_HEXAGON_A2_vnavgwcr: hexagon::A2_vnavgwcr
__builtin_HEXAGON_A2_vnavgwr: hexagon::A2_vnavgwr
__builtin_HEXAGON_A2_vraddub: hexagon::A2_vraddub
__builtin_HEXAGON_A2_vraddub_acc: hexagon::A2_vraddub_acc
__builtin_HEXAGON_A2_vrsadub: hexagon::A2_vrsadub
__builtin_HEXAGON_A2_vrsadub_acc: hexagon::A2_vrsadub_acc
__builtin_HEXAGON_A2_vsubb_map: hexagon::A2_vsubb_map
__builtin_HEXAGON_A2_vsubh: hexagon::A2_vsubh
__builtin_HEXAGON_A2_vsubhs: hexagon::A2_vsubhs
__builtin_HEXAGON_A2_vsubub: hexagon::A2_vsubub
__builtin_HEXAGON_A2_vsububs: hexagon::A2_vsububs
__builtin_HEXAGON_A2_vsubuhs: hexagon::A2_vsubuhs
__builtin_HEXAGON_A2_vsubw: hexagon::A2_vsubw
__builtin_HEXAGON_A2_vsubws: hexagon::A2_vsubws
__builtin_HEXAGON_A2_xor: hexagon::A2_xor
__builtin_HEXAGON_A2_xorp: hexagon::A2_xorp
__builtin_HEXAGON_A2_zxtb: hexagon::A2_zxtb
__builtin_HEXAGON_A2_zxth: hexagon::A2_zxth
__builtin_HEXAGON_A4_andn: hexagon::A4_andn
__builtin_HEXAGON_A4_andnp: hexagon::A4_andnp
__builtin_HEXAGON_A4_bitsplit: hexagon::A4_bitsplit
__builtin_HEXAGON_A4_bitspliti: hexagon::A4_bitspliti
__builtin_HEXAGON_A4_boundscheck: hexagon::A4_boundscheck
__builtin_HEXAGON_A4_cmpbeq: hexagon::A4_cmpbeq
__builtin_HEXAGON_A4_cmpbeqi: hexagon::A4_cmpbeqi
__builtin_HEXAGON_A4_cmpbgt: hexagon::A4_cmpbgt
__builtin_HEXAGON_A4_cmpbgti: hexagon::A4_cmpbgti
__builtin_HEXAGON_A4_cmpbgtu: hexagon::A4_cmpbgtu
__builtin_HEXAGON_A4_cmpbgtui: hexagon::A4_cmpbgtui
__builtin_HEXAGON_A4_cmpheq: hexagon::A4_cmpheq
__builtin_HEXAGON_A4_cmpheqi: hexagon::A4_cmpheqi
__builtin_HEXAGON_A4_cmphgt: hexagon::A4_cmphgt
__builtin_HEXAGON_A4_cmphgti: hexagon::A4_cmphgti
__builtin_HEXAGON_A4_cmphgtu: hexagon::A4_cmphgtu
__builtin_HEXAGON_A4_cmphgtui: hexagon::A4_cmphgtui
__builtin_HEXAGON_A4_combineir: hexagon::A4_combineir
__builtin_HEXAGON_A4_combineri: hexagon::A4_combineri
__builtin_HEXAGON_A4_cround_ri: hexagon::A4_cround_ri
__builtin_HEXAGON_A4_cround_rr: hexagon::A4_cround_rr
__builtin_HEXAGON_A4_modwrapu: hexagon::A4_modwrapu
__builtin_HEXAGON_A4_orn: hexagon::A4_orn
__builtin_HEXAGON_A4_ornp: hexagon::A4_ornp
__builtin_HEXAGON_A4_rcmpeq: hexagon::A4_rcmpeq
__builtin_HEXAGON_A4_rcmpeqi: hexagon::A4_rcmpeqi
__builtin_HEXAGON_A4_rcmpneq: hexagon::A4_rcmpneq
__builtin_HEXAGON_A4_rcmpneqi: hexagon::A4_rcmpneqi
__builtin_HEXAGON_A4_round_ri: hexagon::A4_round_ri
__builtin_HEXAGON_A4_round_ri_sat: hexagon::A4_round_ri_sat
__builtin_HEXAGON_A4_round_rr: hexagon::A4_round_rr
__builtin_HEXAGON_A4_round_rr_sat: hexagon::A4_round_rr_sat
__builtin_HEXAGON_A4_tlbmatch: hexagon::A4_tlbmatch
__builtin_HEXAGON_A4_vcmpbeq_any: hexagon::A4_vcmpbeq_any
__builtin_HEXAGON_A4_vcmpbeqi: hexagon::A4_vcmpbeqi
__builtin_HEXAGON_A4_vcmpbgt: hexagon::A4_vcmpbgt
__builtin_HEXAGON_A4_vcmpbgti: hexagon::A4_vcmpbgti
__builtin_HEXAGON_A4_vcmpbgtui: hexagon::A4_vcmpbgtui
__builtin_HEXAGON_A4_vcmpheqi: hexagon::A4_vcmpheqi
__builtin_HEXAGON_A4_vcmphgti: hexagon::A4_vcmphgti
__builtin_HEXAGON_A4_vcmphgtui: hexagon::A4_vcmphgtui
__builtin_HEXAGON_A4_vcmpweqi: hexagon::A4_vcmpweqi
__builtin_HEXAGON_A4_vcmpwgti: hexagon::A4_vcmpwgti
__builtin_HEXAGON_A4_vcmpwgtui: hexagon::A4_vcmpwgtui
__builtin_HEXAGON_A4_vrmaxh: hexagon::A4_vrmaxh
__builtin_HEXAGON_A4_vrmaxuh: hexagon::A4_vrmaxuh
__builtin_HEXAGON_A4_vrmaxuw: hexagon::A4_vrmaxuw
__builtin_HEXAGON_A4_vrmaxw: hexagon::A4_vrmaxw
__builtin_HEXAGON_A4_vrminh: hexagon::A4_vrminh
__builtin_HEXAGON_A4_vrminuh: hexagon::A4_vrminuh
__builtin_HEXAGON_A4_vrminuw: hexagon::A4_vrminuw
__builtin_HEXAGON_A4_vrminw: hexagon::A4_vrminw
__builtin_HEXAGON_A5_vaddhubs: hexagon::A5_vaddhubs
__builtin_HEXAGON_C2_all8: hexagon::C2_all8
__builtin_HEXAGON_C2_and: hexagon::C2_and
__builtin_HEXAGON_C2_andn: hexagon::C2_andn
__builtin_HEXAGON_C2_any8: hexagon::C2_any8
__builtin_HEXAGON_C2_bitsclr: hexagon::C2_bitsclr
__builtin_HEXAGON_C2_bitsclri: hexagon::C2_bitsclri
__builtin_HEXAGON_C2_bitsset: hexagon::C2_bitsset
__builtin_HEXAGON_C2_cmpeq: hexagon::C2_cmpeq
__builtin_HEXAGON_C2_cmpeqi: hexagon::C2_cmpeqi
__builtin_HEXAGON_C2_cmpeqp: hexagon::C2_cmpeqp
__builtin_HEXAGON_C2_cmpgei: hexagon::C2_cmpgei
__builtin_HEXAGON_C2_cmpgeui: hexagon::C2_cmpgeui
__builtin_HEXAGON_C2_cmpgt: hexagon::C2_cmpgt
__builtin_HEXAGON_C2_cmpgti: hexagon::C2_cmpgti
__builtin_HEXAGON_C2_cmpgtp: hexagon::C2_cmpgtp
__builtin_HEXAGON_C2_cmpgtu: hexagon::C2_cmpgtu
__builtin_HEXAGON_C2_cmpgtui: hexagon::C2_cmpgtui
__builtin_HEXAGON_C2_cmpgtup: hexagon::C2_cmpgtup
__builtin_HEXAGON_C2_cmplt: hexagon::C2_cmplt
__builtin_HEXAGON_C2_cmpltu: hexagon::C2_cmpltu
__builtin_HEXAGON_C2_mask: hexagon::C2_mask
__builtin_HEXAGON_C2_mux: hexagon::C2_mux
__builtin_HEXAGON_C2_muxii: hexagon::C2_muxii
__builtin_HEXAGON_C2_muxir: hexagon::C2_muxir
__builtin_HEXAGON_C2_muxri: hexagon::C2_muxri
__builtin_HEXAGON_C2_not: hexagon::C2_not
__builtin_HEXAGON_C2_or: hexagon::C2_or
__builtin_HEXAGON_C2_orn: hexagon::C2_orn
__builtin_HEXAGON_C2_pxfer_map: hexagon::C2_pxfer_map
__builtin_HEXAGON_C2_tfrpr: hexagon::C2_tfrpr
__builtin_HEXAGON_C2_tfrrp: hexagon::C2_tfrrp
__builtin_HEXAGON_C2_vitpack: hexagon::C2_vitpack
__builtin_HEXAGON_C2_vmux: hexagon::C2_vmux
__builtin_HEXAGON_C2_xor: hexagon::C2_xor
__builtin_HEXAGON_C4_and_and: hexagon::C4_and_and
__builtin_HEXAGON_C4_and_andn: hexagon::C4_and_andn
__builtin_HEXAGON_C4_and_or: hexagon::C4_and_or
__builtin_HEXAGON_C4_and_orn: hexagon::C4_and_orn
__builtin_HEXAGON_C4_cmplte: hexagon::C4_cmplte
__builtin_HEXAGON_C4_cmpltei: hexagon::C4_cmpltei
__builtin_HEXAGON_C4_cmplteu: hexagon::C4_cmplteu
__builtin_HEXAGON_C4_cmplteui: hexagon::C4_cmplteui
__builtin_HEXAGON_C4_cmpneq: hexagon::C4_cmpneq
__builtin_HEXAGON_C4_cmpneqi: hexagon::C4_cmpneqi
__builtin_HEXAGON_C4_fastcorner9: hexagon::C4_fastcorner9
__builtin_HEXAGON_C4_fastcorner9_not: hexagon::C4_fastcorner9_not
__builtin_HEXAGON_C4_nbitsclr: hexagon::C4_nbitsclr
__builtin_HEXAGON_C4_nbitsclri: hexagon::C4_nbitsclri
__builtin_HEXAGON_C4_nbitsset: hexagon::C4_nbitsset
__builtin_HEXAGON_C4_or_and: hexagon::C4_or_and
__builtin_HEXAGON_C4_or_andn: hexagon::C4_or_andn
__builtin_HEXAGON_C4_or_or: hexagon::C4_or_or
__builtin_HEXAGON_C4_or_orn: hexagon::C4_or_orn
__builtin_HEXAGON_F2_conv_d2df: hexagon::F2_conv_d2df
__builtin_HEXAGON_F2_conv_d2sf: hexagon::F2_conv_d2sf
__builtin_HEXAGON_F2_conv_df2d: hexagon::F2_conv_df2d
__builtin_HEXAGON_F2_conv_df2d_chop: hexagon::F2_conv_df2d_chop
__builtin_HEXAGON_F2_conv_df2sf: hexagon::F2_conv_df2sf
__builtin_HEXAGON_F2_conv_df2ud: hexagon::F2_conv_df2ud
__builtin_HEXAGON_F2_conv_df2ud_chop: hexagon::F2_conv_df2ud_chop
__builtin_HEXAGON_F2_conv_df2uw: hexagon::F2_conv_df2uw
__builtin_HEXAGON_F2_conv_df2uw_chop: hexagon::F2_conv_df2uw_chop
__builtin_HEXAGON_F2_conv_df2w: hexagon::F2_conv_df2w
__builtin_HEXAGON_F2_conv_df2w_chop: hexagon::F2_conv_df2w_chop
__builtin_HEXAGON_F2_conv_sf2d: hexagon::F2_conv_sf2d
__builtin_HEXAGON_F2_conv_sf2d_chop: hexagon::F2_conv_sf2d_chop
__builtin_HEXAGON_F2_conv_sf2df: hexagon::F2_conv_sf2df
__builtin_HEXAGON_F2_conv_sf2ud: hexagon::F2_conv_sf2ud
__builtin_HEXAGON_F2_conv_sf2ud_chop: hexagon::F2_conv_sf2ud_chop
__builtin_HEXAGON_F2_conv_sf2uw: hexagon::F2_conv_sf2uw
__builtin_HEXAGON_F2_conv_sf2uw_chop: hexagon::F2_conv_sf2uw_chop
__builtin_HEXAGON_F2_conv_sf2w: hexagon::F2_conv_sf2w
__builtin_HEXAGON_F2_conv_sf2w_chop: hexagon::F2_conv_sf2w_chop
__builtin_HEXAGON_F2_conv_ud2df: hexagon::F2_conv_ud2df
__builtin_HEXAGON_F2_conv_ud2sf: hexagon::F2_conv_ud2sf
__builtin_HEXAGON_F2_conv_uw2df: hexagon::F2_conv_uw2df
__builtin_HEXAGON_F2_conv_uw2sf: hexagon::F2_conv_uw2sf
__builtin_HEXAGON_F2_conv_w2df: hexagon::F2_conv_w2df
__builtin_HEXAGON_F2_conv_w2sf: hexagon::F2_conv_w2sf
__builtin_HEXAGON_F2_dfclass: hexagon::F2_dfclass
__builtin_HEXAGON_F2_dfcmpeq: hexagon::F2_dfcmpeq
__builtin_HEXAGON_F2_dfcmpge: hexagon::F2_dfcmpge
__builtin_HEXAGON_F2_dfcmpgt: hexagon::F2_dfcmpgt
__builtin_HEXAGON_F2_dfcmpuo: hexagon::F2_dfcmpuo
__builtin_HEXAGON_F2_dfimm_n: hexagon::F2_dfimm_n
__builtin_HEXAGON_F2_dfimm_p: hexagon::F2_dfimm_p
__builtin_HEXAGON_F2_sfadd: hexagon::F2_sfadd
__builtin_HEXAGON_F2_sfclass: hexagon::F2_sfclass
__builtin_HEXAGON_F2_sfcmpeq: hexagon::F2_sfcmpeq
__builtin_HEXAGON_F2_sfcmpge: hexagon::F2_sfcmpge
__builtin_HEXAGON_F2_sfcmpgt: hexagon::F2_sfcmpgt
__builtin_HEXAGON_F2_sfcmpuo: hexagon::F2_sfcmpuo
__builtin_HEXAGON_F2_sffixupd: hexagon::F2_sffixupd
__builtin_HEXAGON_F2_sffixupn: hexagon::F2_sffixupn
__builtin_HEXAGON_F2_sffixupr: hexagon::F2_sffixupr
__builtin_HEXAGON_F2_sffma: hexagon::F2_sffma
__builtin_HEXAGON_F2_sffma_lib: hexagon::F2_sffma_lib
__builtin_HEXAGON_F2_sffma_sc: hexagon::F2_sffma_sc
__builtin_HEXAGON_F2_sffms: hexagon::F2_sffms
__builtin_HEXAGON_F2_sffms_lib: hexagon::F2_sffms_lib
__builtin_HEXAGON_F2_sfimm_n: hexagon::F2_sfimm_n
__builtin_HEXAGON_F2_sfimm_p: hexagon::F2_sfimm_p
__builtin_HEXAGON_F2_sfmax: hexagon::F2_sfmax
__builtin_HEXAGON_F2_sfmin: hexagon::F2_sfmin
__builtin_HEXAGON_F2_sfmpy: hexagon::F2_sfmpy
__builtin_HEXAGON_F2_sfsub: hexagon::F2_sfsub
__builtin_HEXAGON_M2_acci: hexagon::M2_acci
__builtin_HEXAGON_M2_accii: hexagon::M2_accii
__builtin_HEXAGON_M2_cmaci_s0: hexagon::M2_cmaci_s0
__builtin_HEXAGON_M2_cmacr_s0: hexagon::M2_cmacr_s0
__builtin_HEXAGON_M2_cmacs_s0: hexagon::M2_cmacs_s0
__builtin_HEXAGON_M2_cmacs_s1: hexagon::M2_cmacs_s1
__builtin_HEXAGON_M2_cmacsc_s0: hexagon::M2_cmacsc_s0
__builtin_HEXAGON_M2_cmacsc_s1: hexagon::M2_cmacsc_s1
__builtin_HEXAGON_M2_cmpyi_s0: hexagon::M2_cmpyi_s0
__builtin_HEXAGON_M2_cmpyr_s0: hexagon::M2_cmpyr_s0
__builtin_HEXAGON_M2_cmpyrs_s0: hexagon::M2_cmpyrs_s0
__builtin_HEXAGON_M2_cmpyrs_s1: hexagon::M2_cmpyrs_s1
__builtin_HEXAGON_M2_cmpyrsc_s0: hexagon::M2_cmpyrsc_s0
__builtin_HEXAGON_M2_cmpyrsc_s1: hexagon::M2_cmpyrsc_s1
__builtin_HEXAGON_M2_cmpys_s0: hexagon::M2_cmpys_s0
__builtin_HEXAGON_M2_cmpys_s1: hexagon::M2_cmpys_s1
__builtin_HEXAGON_M2_cmpysc_s0: hexagon::M2_cmpysc_s0
__builtin_HEXAGON_M2_cmpysc_s1: hexagon::M2_cmpysc_s1
__builtin_HEXAGON_M2_cnacs_s0: hexagon::M2_cnacs_s0
__builtin_HEXAGON_M2_cnacs_s1: hexagon::M2_cnacs_s1
__builtin_HEXAGON_M2_cnacsc_s0: hexagon::M2_cnacsc_s0
__builtin_HEXAGON_M2_cnacsc_s1: hexagon::M2_cnacsc_s1
__builtin_HEXAGON_M2_dpmpyss_acc_s0: hexagon::M2_dpmpyss_acc_s0
__builtin_HEXAGON_M2_dpmpyss_nac_s0: hexagon::M2_dpmpyss_nac_s0
__builtin_HEXAGON_M2_dpmpyss_rnd_s0: hexagon::M2_dpmpyss_rnd_s0
__builtin_HEXAGON_M2_dpmpyss_s0: hexagon::M2_dpmpyss_s0
__builtin_HEXAGON_M2_dpmpyuu_acc_s0: hexagon::M2_dpmpyuu_acc_s0
__builtin_HEXAGON_M2_dpmpyuu_nac_s0: hexagon::M2_dpmpyuu_nac_s0
__builtin_HEXAGON_M2_dpmpyuu_s0: hexagon::M2_dpmpyuu_s0
__builtin_HEXAGON_M2_hmmpyh_rs1: hexagon::M2_hmmpyh_rs1
__builtin_HEXAGON_M2_hmmpyh_s1: hexagon::M2_hmmpyh_s1
__builtin_HEXAGON_M2_hmmpyl_rs1: hexagon::M2_hmmpyl_rs1
__builtin_HEXAGON_M2_hmmpyl_s1: hexagon::M2_hmmpyl_s1
__builtin_HEXAGON_M2_maci: hexagon::M2_maci
__builtin_HEXAGON_M2_macsin: hexagon::M2_macsin
__builtin_HEXAGON_M2_macsip: hexagon::M2_macsip
__builtin_HEXAGON_M2_mmachs_rs0: hexagon::M2_mmachs_rs0
__builtin_HEXAGON_M2_mmachs_rs1: hexagon::M2_mmachs_rs1
__builtin_HEXAGON_M2_mmachs_s0: hexagon::M2_mmachs_s0
__builtin_HEXAGON_M2_mmachs_s1: hexagon::M2_mmachs_s1
__builtin_HEXAGON_M2_mmacls_rs0: hexagon::M2_mmacls_rs0
__builtin_HEXAGON_M2_mmacls_rs1: hexagon::M2_mmacls_rs1
__builtin_HEXAGON_M2_mmacls_s0: hexagon::M2_mmacls_s0
__builtin_HEXAGON_M2_mmacls_s1: hexagon::M2_mmacls_s1
__builtin_HEXAGON_M2_mmacuhs_rs0: hexagon::M2_mmacuhs_rs0
__builtin_HEXAGON_M2_mmacuhs_rs1: hexagon::M2_mmacuhs_rs1
__builtin_HEXAGON_M2_mmacuhs_s0: hexagon::M2_mmacuhs_s0
__builtin_HEXAGON_M2_mmacuhs_s1: hexagon::M2_mmacuhs_s1
__builtin_HEXAGON_M2_mmaculs_rs0: hexagon::M2_mmaculs_rs0
__builtin_HEXAGON_M2_mmaculs_rs1: hexagon::M2_mmaculs_rs1
__builtin_HEXAGON_M2_mmaculs_s0: hexagon::M2_mmaculs_s0
__builtin_HEXAGON_M2_mmaculs_s1: hexagon::M2_mmaculs_s1
__builtin_HEXAGON_M2_mmpyh_rs0: hexagon::M2_mmpyh_rs0
__builtin_HEXAGON_M2_mmpyh_rs1: hexagon::M2_mmpyh_rs1
__builtin_HEXAGON_M2_mmpyh_s0: hexagon::M2_mmpyh_s0
__builtin_HEXAGON_M2_mmpyh_s1: hexagon::M2_mmpyh_s1
__builtin_HEXAGON_M2_mmpyl_rs0: hexagon::M2_mmpyl_rs0
__builtin_HEXAGON_M2_mmpyl_rs1: hexagon::M2_mmpyl_rs1
__builtin_HEXAGON_M2_mmpyl_s0: hexagon::M2_mmpyl_s0
__builtin_HEXAGON_M2_mmpyl_s1: hexagon::M2_mmpyl_s1
__builtin_HEXAGON_M2_mmpyuh_rs0: hexagon::M2_mmpyuh_rs0
__builtin_HEXAGON_M2_mmpyuh_rs1: hexagon::M2_mmpyuh_rs1
__builtin_HEXAGON_M2_mmpyuh_s0: hexagon::M2_mmpyuh_s0
__builtin_HEXAGON_M2_mmpyuh_s1: hexagon::M2_mmpyuh_s1
__builtin_HEXAGON_M2_mmpyul_rs0: hexagon::M2_mmpyul_rs0
__builtin_HEXAGON_M2_mmpyul_rs1: hexagon::M2_mmpyul_rs1
__builtin_HEXAGON_M2_mmpyul_s0: hexagon::M2_mmpyul_s0
__builtin_HEXAGON_M2_mmpyul_s1: hexagon::M2_mmpyul_s1
__builtin_HEXAGON_M2_mpy_acc_hh_s0: hexagon::M2_mpy_acc_hh_s0
__builtin_HEXAGON_M2_mpy_acc_hh_s1: hexagon::M2_mpy_acc_hh_s1
__builtin_HEXAGON_M2_mpy_acc_hl_s0: hexagon::M2_mpy_acc_hl_s0
__builtin_HEXAGON_M2_mpy_acc_hl_s1: hexagon::M2_mpy_acc_hl_s1
__builtin_HEXAGON_M2_mpy_acc_lh_s0: hexagon::M2_mpy_acc_lh_s0
__builtin_HEXAGON_M2_mpy_acc_lh_s1: hexagon::M2_mpy_acc_lh_s1
__builtin_HEXAGON_M2_mpy_acc_ll_s0: hexagon::M2_mpy_acc_ll_s0
__builtin_HEXAGON_M2_mpy_acc_ll_s1: hexagon::M2_mpy_acc_ll_s1
__builtin_HEXAGON_M2_mpy_acc_sat_hh_s0: hexagon::M2_mpy_acc_sat_hh_s0
__builtin_HEXAGON_M2_mpy_acc_sat_hh_s1: hexagon::M2_mpy_acc_sat_hh_s1
__builtin_HEXAGON_M2_mpy_acc_sat_hl_s0: hexagon::M2_mpy_acc_sat_hl_s0
__builtin_HEXAGON_M2_mpy_acc_sat_hl_s1: hexagon::M2_mpy_acc_sat_hl_s1
__builtin_HEXAGON_M2_mpy_acc_sat_lh_s0: hexagon::M2_mpy_acc_sat_lh_s0
__builtin_HEXAGON_M2_mpy_acc_sat_lh_s1: hexagon::M2_mpy_acc_sat_lh_s1
__builtin_HEXAGON_M2_mpy_acc_sat_ll_s0: hexagon::M2_mpy_acc_sat_ll_s0
__builtin_HEXAGON_M2_mpy_acc_sat_ll_s1: hexagon::M2_mpy_acc_sat_ll_s1
__builtin_HEXAGON_M2_mpy_hh_s0: hexagon::M2_mpy_hh_s0
__builtin_HEXAGON_M2_mpy_hh_s1: hexagon::M2_mpy_hh_s1
__builtin_HEXAGON_M2_mpy_hl_s0: hexagon::M2_mpy_hl_s0
__builtin_HEXAGON_M2_mpy_hl_s1: hexagon::M2_mpy_hl_s1
__builtin_HEXAGON_M2_mpy_lh_s0: hexagon::M2_mpy_lh_s0
__builtin_HEXAGON_M2_mpy_lh_s1: hexagon::M2_mpy_lh_s1
__builtin_HEXAGON_M2_mpy_ll_s0: hexagon::M2_mpy_ll_s0
__builtin_HEXAGON_M2_mpy_ll_s1: hexagon::M2_mpy_ll_s1
__builtin_HEXAGON_M2_mpy_nac_hh_s0: hexagon::M2_mpy_nac_hh_s0
__builtin_HEXAGON_M2_mpy_nac_hh_s1: hexagon::M2_mpy_nac_hh_s1
__builtin_HEXAGON_M2_mpy_nac_hl_s0: hexagon::M2_mpy_nac_hl_s0
__builtin_HEXAGON_M2_mpy_nac_hl_s1: hexagon::M2_mpy_nac_hl_s1
__builtin_HEXAGON_M2_mpy_nac_lh_s0: hexagon::M2_mpy_nac_lh_s0
__builtin_HEXAGON_M2_mpy_nac_lh_s1: hexagon::M2_mpy_nac_lh_s1
__builtin_HEXAGON_M2_mpy_nac_ll_s0: hexagon::M2_mpy_nac_ll_s0
__builtin_HEXAGON_M2_mpy_nac_ll_s1: hexagon::M2_mpy_nac_ll_s1
__builtin_HEXAGON_M2_mpy_nac_sat_hh_s0: hexagon::M2_mpy_nac_sat_hh_s0
__builtin_HEXAGON_M2_mpy_nac_sat_hh_s1: hexagon::M2_mpy_nac_sat_hh_s1
__builtin_HEXAGON_M2_mpy_nac_sat_hl_s0: hexagon::M2_mpy_nac_sat_hl_s0
__builtin_HEXAGON_M2_mpy_nac_sat_hl_s1: hexagon::M2_mpy_nac_sat_hl_s1
__builtin_HEXAGON_M2_mpy_nac_sat_lh_s0: hexagon::M2_mpy_nac_sat_lh_s0
__builtin_HEXAGON_M2_mpy_nac_sat_lh_s1: hexagon::M2_mpy_nac_sat_lh_s1
__builtin_HEXAGON_M2_mpy_nac_sat_ll_s0: hexagon::M2_mpy_nac_sat_ll_s0
__builtin_HEXAGON_M2_mpy_nac_sat_ll_s1: hexagon::M2_mpy_nac_sat_ll_s1
__builtin_HEXAGON_M2_mpy_rnd_hh_s0: hexagon::M2_mpy_rnd_hh_s0
__builtin_HEXAGON_M2_mpy_rnd_hh_s1: hexagon::M2_mpy_rnd_hh_s1
__builtin_HEXAGON_M2_mpy_rnd_hl_s0: hexagon::M2_mpy_rnd_hl_s0
__builtin_HEXAGON_M2_mpy_rnd_hl_s1: hexagon::M2_mpy_rnd_hl_s1
__builtin_HEXAGON_M2_mpy_rnd_lh_s0: hexagon::M2_mpy_rnd_lh_s0
__builtin_HEXAGON_M2_mpy_rnd_lh_s1: hexagon::M2_mpy_rnd_lh_s1
__builtin_HEXAGON_M2_mpy_rnd_ll_s0: hexagon::M2_mpy_rnd_ll_s0
__builtin_HEXAGON_M2_mpy_rnd_ll_s1: hexagon::M2_mpy_rnd_ll_s1
__builtin_HEXAGON_M2_mpy_sat_hh_s0: hexagon::M2_mpy_sat_hh_s0
__builtin_HEXAGON_M2_mpy_sat_hh_s1: hexagon::M2_mpy_sat_hh_s1
__builtin_HEXAGON_M2_mpy_sat_hl_s0: hexagon::M2_mpy_sat_hl_s0
__builtin_HEXAGON_M2_mpy_sat_hl_s1: hexagon::M2_mpy_sat_hl_s1
__builtin_HEXAGON_M2_mpy_sat_lh_s0: hexagon::M2_mpy_sat_lh_s0
__builtin_HEXAGON_M2_mpy_sat_lh_s1: hexagon::M2_mpy_sat_lh_s1
__builtin_HEXAGON_M2_mpy_sat_ll_s0: hexagon::M2_mpy_sat_ll_s0
__builtin_HEXAGON_M2_mpy_sat_ll_s1: hexagon::M2_mpy_sat_ll_s1
__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s0: hexagon::M2_mpy_sat_rnd_hh_s0
__builtin_HEXAGON_M2_mpy_sat_rnd_hh_s1: hexagon::M2_mpy_sat_rnd_hh_s1
__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s0: hexagon::M2_mpy_sat_rnd_hl_s0
__builtin_HEXAGON_M2_mpy_sat_rnd_hl_s1: hexagon::M2_mpy_sat_rnd_hl_s1
__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s0: hexagon::M2_mpy_sat_rnd_lh_s0
__builtin_HEXAGON_M2_mpy_sat_rnd_lh_s1: hexagon::M2_mpy_sat_rnd_lh_s1
__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s0: hexagon::M2_mpy_sat_rnd_ll_s0
__builtin_HEXAGON_M2_mpy_sat_rnd_ll_s1: hexagon::M2_mpy_sat_rnd_ll_s1
__builtin_HEXAGON_M2_mpy_up: hexagon::M2_mpy_up
__builtin_HEXAGON_M2_mpy_up_s1: hexagon::M2_mpy_up_s1
__builtin_HEXAGON_M2_mpy_up_s1_sat: hexagon::M2_mpy_up_s1_sat
__builtin_HEXAGON_M2_mpyd_acc_hh_s0: hexagon::M2_mpyd_acc_hh_s0
__builtin_HEXAGON_M2_mpyd_acc_hh_s1: hexagon::M2_mpyd_acc_hh_s1
__builtin_HEXAGON_M2_mpyd_acc_hl_s0: hexagon::M2_mpyd_acc_hl_s0
__builtin_HEXAGON_M2_mpyd_acc_hl_s1: hexagon::M2_mpyd_acc_hl_s1
__builtin_HEXAGON_M2_mpyd_acc_lh_s0: hexagon::M2_mpyd_acc_lh_s0
__builtin_HEXAGON_M2_mpyd_acc_lh_s1: hexagon::M2_mpyd_acc_lh_s1
__builtin_HEXAGON_M2_mpyd_acc_ll_s0: hexagon::M2_mpyd_acc_ll_s0
__builtin_HEXAGON_M2_mpyd_acc_ll_s1: hexagon::M2_mpyd_acc_ll_s1
__builtin_HEXAGON_M2_mpyd_hh_s0: hexagon::M2_mpyd_hh_s0
__builtin_HEXAGON_M2_mpyd_hh_s1: hexagon::M2_mpyd_hh_s1
__builtin_HEXAGON_M2_mpyd_hl_s0: hexagon::M2_mpyd_hl_s0
__builtin_HEXAGON_M2_mpyd_hl_s1: hexagon::M2_mpyd_hl_s1
__builtin_HEXAGON_M2_mpyd_lh_s0: hexagon::M2_mpyd_lh_s0
__builtin_HEXAGON_M2_mpyd_lh_s1: hexagon::M2_mpyd_lh_s1
__builtin_HEXAGON_M2_mpyd_ll_s0: hexagon::M2_mpyd_ll_s0
__builtin_HEXAGON_M2_mpyd_ll_s1: hexagon::M2_mpyd_ll_s1
__builtin_HEXAGON_M2_mpyd_nac_hh_s0: hexagon::M2_mpyd_nac_hh_s0
__builtin_HEXAGON_M2_mpyd_nac_hh_s1: hexagon::M2_mpyd_nac_hh_s1
__builtin_HEXAGON_M2_mpyd_nac_hl_s0: hexagon::M2_mpyd_nac_hl_s0
__builtin_HEXAGON_M2_mpyd_nac_hl_s1: hexagon::M2_mpyd_nac_hl_s1
__builtin_HEXAGON_M2_mpyd_nac_lh_s0: hexagon::M2_mpyd_nac_lh_s0
__builtin_HEXAGON_M2_mpyd_nac_lh_s1: hexagon::M2_mpyd_nac_lh_s1
__builtin_HEXAGON_M2_mpyd_nac_ll_s0: hexagon::M2_mpyd_nac_ll_s0
__builtin_HEXAGON_M2_mpyd_nac_ll_s1: hexagon::M2_mpyd_nac_ll_s1
__builtin_HEXAGON_M2_mpyd_rnd_hh_s0: hexagon::M2_mpyd_rnd_hh_s0
__builtin_HEXAGON_M2_mpyd_rnd_hh_s1: hexagon::M2_mpyd_rnd_hh_s1
__builtin_HEXAGON_M2_mpyd_rnd_hl_s0: hexagon::M2_mpyd_rnd_hl_s0
__builtin_HEXAGON_M2_mpyd_rnd_hl_s1: hexagon::M2_mpyd_rnd_hl_s1
__builtin_HEXAGON_M2_mpyd_rnd_lh_s0: hexagon::M2_mpyd_rnd_lh_s0
__builtin_HEXAGON_M2_mpyd_rnd_lh_s1: hexagon::M2_mpyd_rnd_lh_s1
__builtin_HEXAGON_M2_mpyd_rnd_ll_s0: hexagon::M2_mpyd_rnd_ll_s0
__builtin_HEXAGON_M2_mpyd_rnd_ll_s1: hexagon::M2_mpyd_rnd_ll_s1
__builtin_HEXAGON_M2_mpyi: hexagon::M2_mpyi
__builtin_HEXAGON_M2_mpysmi: hexagon::M2_mpysmi
__builtin_HEXAGON_M2_mpysu_up: hexagon::M2_mpysu_up
__builtin_HEXAGON_M2_mpyu_acc_hh_s0: hexagon::M2_mpyu_acc_hh_s0
__builtin_HEXAGON_M2_mpyu_acc_hh_s1: hexagon::M2_mpyu_acc_hh_s1
__builtin_HEXAGON_M2_mpyu_acc_hl_s0: hexagon::M2_mpyu_acc_hl_s0
__builtin_HEXAGON_M2_mpyu_acc_hl_s1: hexagon::M2_mpyu_acc_hl_s1
__builtin_HEXAGON_M2_mpyu_acc_lh_s0: hexagon::M2_mpyu_acc_lh_s0
__builtin_HEXAGON_M2_mpyu_acc_lh_s1: hexagon::M2_mpyu_acc_lh_s1
__builtin_HEXAGON_M2_mpyu_acc_ll_s0: hexagon::M2_mpyu_acc_ll_s0
__builtin_HEXAGON_M2_mpyu_acc_ll_s1: hexagon::M2_mpyu_acc_ll_s1
__builtin_HEXAGON_M2_mpyu_hh_s0: hexagon::M2_mpyu_hh_s0
__builtin_HEXAGON_M2_mpyu_hh_s1: hexagon::M2_mpyu_hh_s1
__builtin_HEXAGON_M2_mpyu_hl_s0: hexagon::M2_mpyu_hl_s0
__builtin_HEXAGON_M2_mpyu_hl_s1: hexagon::M2_mpyu_hl_s1
__builtin_HEXAGON_M2_mpyu_lh_s0: hexagon::M2_mpyu_lh_s0
__builtin_HEXAGON_M2_mpyu_lh_s1: hexagon::M2_mpyu_lh_s1
__builtin_HEXAGON_M2_mpyu_ll_s0: hexagon::M2_mpyu_ll_s0
__builtin_HEXAGON_M2_mpyu_ll_s1: hexagon::M2_mpyu_ll_s1
__builtin_HEXAGON_M2_mpyu_nac_hh_s0: hexagon::M2_mpyu_nac_hh_s0
__builtin_HEXAGON_M2_mpyu_nac_hh_s1: hexagon::M2_mpyu_nac_hh_s1
__builtin_HEXAGON_M2_mpyu_nac_hl_s0: hexagon::M2_mpyu_nac_hl_s0
__builtin_HEXAGON_M2_mpyu_nac_hl_s1: hexagon::M2_mpyu_nac_hl_s1
__builtin_HEXAGON_M2_mpyu_nac_lh_s0: hexagon::M2_mpyu_nac_lh_s0
__builtin_HEXAGON_M2_mpyu_nac_lh_s1: hexagon::M2_mpyu_nac_lh_s1
__builtin_HEXAGON_M2_mpyu_nac_ll_s0: hexagon::M2_mpyu_nac_ll_s0
__builtin_HEXAGON_M2_mpyu_nac_ll_s1: hexagon::M2_mpyu_nac_ll_s1
__builtin_HEXAGON_M2_mpyu_up: hexagon::M2_mpyu_up
__builtin_HEXAGON_M2_mpyud_acc_hh_s0: hexagon::M2_mpyud_acc_hh_s0
__builtin_HEXAGON_M2_mpyud_acc_hh_s1: hexagon::M2_mpyud_acc_hh_s1
__builtin_HEXAGON_M2_mpyud_acc_hl_s0: hexagon::M2_mpyud_acc_hl_s0
__builtin_HEXAGON_M2_mpyud_acc_hl_s1: hexagon::M2_mpyud_acc_hl_s1
__builtin_HEXAGON_M2_mpyud_acc_lh_s0: hexagon::M2_mpyud_acc_lh_s0
__builtin_HEXAGON_M2_mpyud_acc_lh_s1: hexagon::M2_mpyud_acc_lh_s1
__builtin_HEXAGON_M2_mpyud_acc_ll_s0: hexagon::M2_mpyud_acc_ll_s0
__builtin_HEXAGON_M2_mpyud_acc_ll_s1: hexagon::M2_mpyud_acc_ll_s1
__builtin_HEXAGON_M2_mpyud_hh_s0: hexagon::M2_mpyud_hh_s0
__builtin_HEXAGON_M2_mpyud_hh_s1: hexagon::M2_mpyud_hh_s1
__builtin_HEXAGON_M2_mpyud_hl_s0: hexagon::M2_mpyud_hl_s0
__builtin_HEXAGON_M2_mpyud_hl_s1: hexagon::M2_mpyud_hl_s1
__builtin_HEXAGON_M2_mpyud_lh_s0: hexagon::M2_mpyud_lh_s0
__builtin_HEXAGON_M2_mpyud_lh_s1: hexagon::M2_mpyud_lh_s1
__builtin_HEXAGON_M2_mpyud_ll_s0: hexagon::M2_mpyud_ll_s0
__builtin_HEXAGON_M2_mpyud_ll_s1: hexagon::M2_mpyud_ll_s1
__builtin_HEXAGON_M2_mpyud_nac_hh_s0: hexagon::M2_mpyud_nac_hh_s0
__builtin_HEXAGON_M2_mpyud_nac_hh_s1: hexagon::M2_mpyud_nac_hh_s1
__builtin_HEXAGON_M2_mpyud_nac_hl_s0: hexagon::M2_mpyud_nac_hl_s0
__builtin_HEXAGON_M2_mpyud_nac_hl_s1: hexagon::M2_mpyud_nac_hl_s1
__builtin_HEXAGON_M2_mpyud_nac_lh_s0: hexagon::M2_mpyud_nac_lh_s0
__builtin_HEXAGON_M2_mpyud_nac_lh_s1: hexagon::M2_mpyud_nac_lh_s1
__builtin_HEXAGON_M2_mpyud_nac_ll_s0: hexagon::M2_mpyud_nac_ll_s0
__builtin_HEXAGON_M2_mpyud_nac_ll_s1: hexagon::M2_mpyud_nac_ll_s1
__builtin_HEXAGON_M2_mpyui: hexagon::M2_mpyui
__builtin_HEXAGON_M2_nacci: hexagon::M2_nacci
__builtin_HEXAGON_M2_naccii: hexagon::M2_naccii
__builtin_HEXAGON_M2_subacc: hexagon::M2_subacc
__builtin_HEXAGON_M2_vabsdiffh: hexagon::M2_vabsdiffh
__builtin_HEXAGON_M2_vabsdiffw: hexagon::M2_vabsdiffw
__builtin_HEXAGON_M2_vcmac_s0_sat_i: hexagon::M2_vcmac_s0_sat_i
__builtin_HEXAGON_M2_vcmac_s0_sat_r: hexagon::M2_vcmac_s0_sat_r
__builtin_HEXAGON_M2_vcmpy_s0_sat_i: hexagon::M2_vcmpy_s0_sat_i
__builtin_HEXAGON_M2_vcmpy_s0_sat_r: hexagon::M2_vcmpy_s0_sat_r
__builtin_HEXAGON_M2_vcmpy_s1_sat_i: hexagon::M2_vcmpy_s1_sat_i
__builtin_HEXAGON_M2_vcmpy_s1_sat_r: hexagon::M2_vcmpy_s1_sat_r
__builtin_HEXAGON_M2_vdmacs_s0: hexagon::M2_vdmacs_s0
__builtin_HEXAGON_M2_vdmacs_s1: hexagon::M2_vdmacs_s1
__builtin_HEXAGON_M2_vdmpyrs_s0: hexagon::M2_vdmpyrs_s0
__builtin_HEXAGON_M2_vdmpyrs_s1: hexagon::M2_vdmpyrs_s1
__builtin_HEXAGON_M2_vdmpys_s0: hexagon::M2_vdmpys_s0
__builtin_HEXAGON_M2_vdmpys_s1: hexagon::M2_vdmpys_s1
__builtin_HEXAGON_M2_vmac2: hexagon::M2_vmac2
__builtin_HEXAGON_M2_vmac2es: hexagon::M2_vmac2es
__builtin_HEXAGON_M2_vmac2es_s0: hexagon::M2_vmac2es_s0
__builtin_HEXAGON_M2_vmac2es_s1: hexagon::M2_vmac2es_s1
__builtin_HEXAGON_M2_vmac2s_s0: hexagon::M2_vmac2s_s0
__builtin_HEXAGON_M2_vmac2s_s1: hexagon::M2_vmac2s_s1
__builtin_HEXAGON_M2_vmac2su_s0: hexagon::M2_vmac2su_s0
__builtin_HEXAGON_M2_vmac2su_s1: hexagon::M2_vmac2su_s1
__builtin_HEXAGON_M2_vmpy2es_s0: hexagon::M2_vmpy2es_s0
__builtin_HEXAGON_M2_vmpy2es_s1: hexagon::M2_vmpy2es_s1
__builtin_HEXAGON_M2_vmpy2s_s0: hexagon::M2_vmpy2s_s0
__builtin_HEXAGON_M2_vmpy2s_s0pack: hexagon::M2_vmpy2s_s0pack
__builtin_HEXAGON_M2_vmpy2s_s1: hexagon::M2_vmpy2s_s1
__builtin_HEXAGON_M2_vmpy2s_s1pack: hexagon::M2_vmpy2s_s1pack
__builtin_HEXAGON_M2_vmpy2su_s0: hexagon::M2_vmpy2su_s0
__builtin_HEXAGON_M2_vmpy2su_s1: hexagon::M2_vmpy2su_s1
__builtin_HEXAGON_M2_vraddh: hexagon::M2_vraddh
__builtin_HEXAGON_M2_vradduh: hexagon::M2_vradduh
__builtin_HEXAGON_M2_vrcmaci_s0: hexagon::M2_vrcmaci_s0
__builtin_HEXAGON_M2_vrcmaci_s0c: hexagon::M2_vrcmaci_s0c
__builtin_HEXAGON_M2_vrcmacr_s0: hexagon::M2_vrcmacr_s0
__builtin_HEXAGON_M2_vrcmacr_s0c: hexagon::M2_vrcmacr_s0c
__builtin_HEXAGON_M2_vrcmpyi_s0: hexagon::M2_vrcmpyi_s0
__builtin_HEXAGON_M2_vrcmpyi_s0c: hexagon::M2_vrcmpyi_s0c
__builtin_HEXAGON_M2_vrcmpyr_s0: hexagon::M2_vrcmpyr_s0
__builtin_HEXAGON_M2_vrcmpyr_s0c: hexagon::M2_vrcmpyr_s0c
__builtin_HEXAGON_M2_vrcmpys_acc_s1: hexagon::M2_vrcmpys_acc_s1
__builtin_HEXAGON_M2_vrcmpys_s1: hexagon::M2_vrcmpys_s1
__builtin_HEXAGON_M2_vrcmpys_s1rp: hexagon::M2_vrcmpys_s1rp
__builtin_HEXAGON_M2_vrmac_s0: hexagon::M2_vrmac_s0
__builtin_HEXAGON_M2_vrmpy_s0: hexagon::M2_vrmpy_s0
__builtin_HEXAGON_M2_xor_xacc: hexagon::M2_xor_xacc
__builtin_HEXAGON_M4_and_and: hexagon::M4_and_and
__builtin_HEXAGON_M4_and_andn: hexagon::M4_and_andn
__builtin_HEXAGON_M4_and_or: hexagon::M4_and_or
__builtin_HEXAGON_M4_and_xor: hexagon::M4_and_xor
__builtin_HEXAGON_M4_cmpyi_wh: hexagon::M4_cmpyi_wh
__builtin_HEXAGON_M4_cmpyi_whc: hexagon::M4_cmpyi_whc
__builtin_HEXAGON_M4_cmpyr_wh: hexagon::M4_cmpyr_wh
__builtin_HEXAGON_M4_cmpyr_whc: hexagon::M4_cmpyr_whc
__builtin_HEXAGON_M4_mac_up_s1_sat: hexagon::M4_mac_up_s1_sat
__builtin_HEXAGON_M4_mpyri_addi: hexagon::M4_mpyri_addi
__builtin_HEXAGON_M4_mpyri_addr: hexagon::M4_mpyri_addr
__builtin_HEXAGON_M4_mpyri_addr_u2: hexagon::M4_mpyri_addr_u2
__builtin_HEXAGON_M4_mpyrr_addi: hexagon::M4_mpyrr_addi
__builtin_HEXAGON_M4_mpyrr_addr: hexagon::M4_mpyrr_addr
__builtin_HEXAGON_M4_nac_up_s1_sat: hexagon::M4_nac_up_s1_sat
__builtin_HEXAGON_M4_or_and: hexagon::M4_or_and
__builtin_HEXAGON_M4_or_andn: hexagon::M4_or_andn
__builtin_HEXAGON_M4_or_or: hexagon::M4_or_or
__builtin_HEXAGON_M4_or_xor: hexagon::M4_or_xor
__builtin_HEXAGON_M4_pmpyw: hexagon::M4_pmpyw
__builtin_HEXAGON_M4_pmpyw_acc: hexagon::M4_pmpyw_acc
__builtin_HEXAGON_M4_vpmpyh: hexagon::M4_vpmpyh
__builtin_HEXAGON_M4_vpmpyh_acc: hexagon::M4_vpmpyh_acc
__builtin_HEXAGON_M4_vrmpyeh_acc_s0: hexagon::M4_vrmpyeh_acc_s0
__builtin_HEXAGON_M4_vrmpyeh_acc_s1: hexagon::M4_vrmpyeh_acc_s1
__builtin_HEXAGON_M4_vrmpyeh_s0: hexagon::M4_vrmpyeh_s0
__builtin_HEXAGON_M4_vrmpyeh_s1: hexagon::M4_vrmpyeh_s1
__builtin_HEXAGON_M4_vrmpyoh_acc_s0: hexagon::M4_vrmpyoh_acc_s0
__builtin_HEXAGON_M4_vrmpyoh_acc_s1: hexagon::M4_vrmpyoh_acc_s1
__builtin_HEXAGON_M4_vrmpyoh_s0: hexagon::M4_vrmpyoh_s0
__builtin_HEXAGON_M4_vrmpyoh_s1: hexagon::M4_vrmpyoh_s1
__builtin_HEXAGON_M4_xor_and: hexagon::M4_xor_and
__builtin_HEXAGON_M4_xor_andn: hexagon::M4_xor_andn
__builtin_HEXAGON_M4_xor_or: hexagon::M4_xor_or
__builtin_HEXAGON_M4_xor_xacc: hexagon::M4_xor_xacc
__builtin_HEXAGON_M5_vdmacbsu: hexagon::M5_vdmacbsu
__builtin_HEXAGON_M5_vdmpybsu: hexagon::M5_vdmpybsu
__builtin_HEXAGON_M5_vmacbsu: hexagon::M5_vmacbsu
__builtin_HEXAGON_M5_vmacbuu: hexagon::M5_vmacbuu
__builtin_HEXAGON_M5_vmpybsu: hexagon::M5_vmpybsu
__builtin_HEXAGON_M5_vmpybuu: hexagon::M5_vmpybuu
__builtin_HEXAGON_M5_vrmacbsu: hexagon::M5_vrmacbsu
__builtin_HEXAGON_M5_vrmacbuu: hexagon::M5_vrmacbuu
__builtin_HEXAGON_M5_vrmpybsu: hexagon::M5_vrmpybsu
__builtin_HEXAGON_M5_vrmpybuu: hexagon::M5_vrmpybuu
__builtin_HEXAGON_M6_vabsdiffb: hexagon::M6_vabsdiffb
__builtin_HEXAGON_M6_vabsdiffub: hexagon::M6_vabsdiffub
__builtin_HEXAGON_S2_addasl_rrri: hexagon::S2_addasl_rrri
__builtin_HEXAGON_S2_asl_i_p: hexagon::S2_asl_i_p
__builtin_HEXAGON_S2_asl_i_p_acc: hexagon::S2_asl_i_p_acc
__builtin_HEXAGON_S2_asl_i_p_and: hexagon::S2_asl_i_p_and
__builtin_HEXAGON_S2_asl_i_p_nac: hexagon::S2_asl_i_p_nac
__builtin_HEXAGON_S2_asl_i_p_or: hexagon::S2_asl_i_p_or
__builtin_HEXAGON_S2_asl_i_p_xacc: hexagon::S2_asl_i_p_xacc
__builtin_HEXAGON_S2_asl_i_r: hexagon::S2_asl_i_r
__builtin_HEXAGON_S2_asl_i_r_acc: hexagon::S2_asl_i_r_acc
__builtin_HEXAGON_S2_asl_i_r_and: hexagon::S2_asl_i_r_and
__builtin_HEXAGON_S2_asl_i_r_nac: hexagon::S2_asl_i_r_nac
__builtin_HEXAGON_S2_asl_i_r_or: hexagon::S2_asl_i_r_or
__builtin_HEXAGON_S2_asl_i_r_sat: hexagon::S2_asl_i_r_sat
__builtin_HEXAGON_S2_asl_i_r_xacc: hexagon::S2_asl_i_r_xacc
__builtin_HEXAGON_S2_asl_i_vh: hexagon::S2_asl_i_vh
__builtin_HEXAGON_S2_asl_i_vw: hexagon::S2_asl_i_vw
__builtin_HEXAGON_S2_asl_r_p: hexagon::S2_asl_r_p
__builtin_HEXAGON_S2_asl_r_p_acc: hexagon::S2_asl_r_p_acc
__builtin_HEXAGON_S2_asl_r_p_and: hexagon::S2_asl_r_p_and
__builtin_HEXAGON_S2_asl_r_p_nac: hexagon::S2_asl_r_p_nac
__builtin_HEXAGON_S2_asl_r_p_or: hexagon::S2_asl_r_p_or
__builtin_HEXAGON_S2_asl_r_p_xor: hexagon::S2_asl_r_p_xor
__builtin_HEXAGON_S2_asl_r_r: hexagon::S2_asl_r_r
__builtin_HEXAGON_S2_asl_r_r_acc: hexagon::S2_asl_r_r_acc
__builtin_HEXAGON_S2_asl_r_r_and: hexagon::S2_asl_r_r_and
__builtin_HEXAGON_S2_asl_r_r_nac: hexagon::S2_asl_r_r_nac
__builtin_HEXAGON_S2_asl_r_r_or: hexagon::S2_asl_r_r_or
__builtin_HEXAGON_S2_asl_r_r_sat: hexagon::S2_asl_r_r_sat
__builtin_HEXAGON_S2_asl_r_vh: hexagon::S2_asl_r_vh
__builtin_HEXAGON_S2_asl_r_vw: hexagon::S2_asl_r_vw
__builtin_HEXAGON_S2_asr_i_p: hexagon::S2_asr_i_p
__builtin_HEXAGON_S2_asr_i_p_acc: hexagon::S2_asr_i_p_acc
__builtin_HEXAGON_S2_asr_i_p_and: hexagon::S2_asr_i_p_and
__builtin_HEXAGON_S2_asr_i_p_nac: hexagon::S2_asr_i_p_nac
__builtin_HEXAGON_S2_asr_i_p_or: hexagon::S2_asr_i_p_or
__builtin_HEXAGON_S2_asr_i_p_rnd: hexagon::S2_asr_i_p_rnd
__builtin_HEXAGON_S2_asr_i_p_rnd_goodsyntax: hexagon::S2_asr_i_p_rnd_goodsyntax
__builtin_HEXAGON_S2_asr_i_r: hexagon::S2_asr_i_r
__builtin_HEXAGON_S2_asr_i_r_acc: hexagon::S2_asr_i_r_acc
__builtin_HEXAGON_S2_asr_i_r_and: hexagon::S2_asr_i_r_and
__builtin_HEXAGON_S2_asr_i_r_nac: hexagon::S2_asr_i_r_nac
__builtin_HEXAGON_S2_asr_i_r_or: hexagon::S2_asr_i_r_or
__builtin_HEXAGON_S2_asr_i_r_rnd: hexagon::S2_asr_i_r_rnd
__builtin_HEXAGON_S2_asr_i_r_rnd_goodsyntax: hexagon::S2_asr_i_r_rnd_goodsyntax
__builtin_HEXAGON_S2_asr_i_svw_trun: hexagon::S2_asr_i_svw_trun
__builtin_HEXAGON_S2_asr_i_vh: hexagon::S2_asr_i_vh
__builtin_HEXAGON_S2_asr_i_vw: hexagon::S2_asr_i_vw
__builtin_HEXAGON_S2_asr_r_p: hexagon::S2_asr_r_p
__builtin_HEXAGON_S2_asr_r_p_acc: hexagon::S2_asr_r_p_acc
__builtin_HEXAGON_S2_asr_r_p_and: hexagon::S2_asr_r_p_and
__builtin_HEXAGON_S2_asr_r_p_nac: hexagon::S2_asr_r_p_nac
__builtin_HEXAGON_S2_asr_r_p_or: hexagon::S2_asr_r_p_or
__builtin_HEXAGON_S2_asr_r_p_xor: hexagon::S2_asr_r_p_xor
__builtin_HEXAGON_S2_asr_r_r: hexagon::S2_asr_r_r
__builtin_HEXAGON_S2_asr_r_r_acc: hexagon::S2_asr_r_r_acc
__builtin_HEXAGON_S2_asr_r_r_and: hexagon::S2_asr_r_r_and
__builtin_HEXAGON_S2_asr_r_r_nac: hexagon::S2_asr_r_r_nac
__builtin_HEXAGON_S2_asr_r_r_or: hexagon::S2_asr_r_r_or
__builtin_HEXAGON_S2_asr_r_r_sat: hexagon::S2_asr_r_r_sat
__builtin_HEXAGON_S2_asr_r_svw_trun: hexagon::S2_asr_r_svw_trun
__builtin_HEXAGON_S2_asr_r_vh: hexagon::S2_asr_r_vh
__builtin_HEXAGON_S2_asr_r_vw: hexagon::S2_asr_r_vw
__builtin_HEXAGON_S2_brev: hexagon::S2_brev
__builtin_HEXAGON_S2_brevp: hexagon::S2_brevp
__builtin_HEXAGON_S2_cabacencbin: hexagon::S2_cabacencbin
__builtin_HEXAGON_S2_cl0: hexagon::S2_cl0
__builtin_HEXAGON_S2_cl0p: hexagon::S2_cl0p
__builtin_HEXAGON_S2_cl1: hexagon::S2_cl1
__builtin_HEXAGON_S2_cl1p: hexagon::S2_cl1p
__builtin_HEXAGON_S2_clb: hexagon::S2_clb
__builtin_HEXAGON_S2_clbnorm: hexagon::S2_clbnorm
__builtin_HEXAGON_S2_clbp: hexagon::S2_clbp
__builtin_HEXAGON_S2_clrbit_i: hexagon::S2_clrbit_i
__builtin_HEXAGON_S2_clrbit_r: hexagon::S2_clrbit_r
__builtin_HEXAGON_S2_ct0: hexagon::S2_ct0
__builtin_HEXAGON_S2_ct0p: hexagon::S2_ct0p
__builtin_HEXAGON_S2_ct1: hexagon::S2_ct1
__builtin_HEXAGON_S2_ct1p: hexagon::S2_ct1p
__builtin_HEXAGON_S2_deinterleave: hexagon::S2_deinterleave
__builtin_HEXAGON_S2_extractu: hexagon::S2_extractu
__builtin_HEXAGON_S2_extractu_rp: hexagon::S2_extractu_rp
__builtin_HEXAGON_S2_extractup: hexagon::S2_extractup
__builtin_HEXAGON_S2_extractup_rp: hexagon::S2_extractup_rp
__builtin_HEXAGON_S2_insert: hexagon::S2_insert
__builtin_HEXAGON_S2_insert_rp: hexagon::S2_insert_rp
__builtin_HEXAGON_S2_insertp: hexagon::S2_insertp
__builtin_HEXAGON_S2_insertp_rp: hexagon::S2_insertp_rp
__builtin_HEXAGON_S2_interleave: hexagon::S2_interleave
__builtin_HEXAGON_S2_lfsp: hexagon::S2_lfsp
__builtin_HEXAGON_S2_lsl_r_p: hexagon::S2_lsl_r_p
__builtin_HEXAGON_S2_lsl_r_p_acc: hexagon::S2_lsl_r_p_acc
__builtin_HEXAGON_S2_lsl_r_p_and: hexagon::S2_lsl_r_p_and
__builtin_HEXAGON_S2_lsl_r_p_nac: hexagon::S2_lsl_r_p_nac
__builtin_HEXAGON_S2_lsl_r_p_or: hexagon::S2_lsl_r_p_or
__builtin_HEXAGON_S2_lsl_r_p_xor: hexagon::S2_lsl_r_p_xor
__builtin_HEXAGON_S2_lsl_r_r: hexagon::S2_lsl_r_r
__builtin_HEXAGON_S2_lsl_r_r_acc: hexagon::S2_lsl_r_r_acc
__builtin_HEXAGON_S2_lsl_r_r_and: hexagon::S2_lsl_r_r_and
__builtin_HEXAGON_S2_lsl_r_r_nac: hexagon::S2_lsl_r_r_nac
__builtin_HEXAGON_S2_lsl_r_r_or: hexagon::S2_lsl_r_r_or
__builtin_HEXAGON_S2_lsl_r_vh: hexagon::S2_lsl_r_vh
__builtin_HEXAGON_S2_lsl_r_vw: hexagon::S2_lsl_r_vw
__builtin_HEXAGON_S2_lsr_i_p: hexagon::S2_lsr_i_p
__builtin_HEXAGON_S2_lsr_i_p_acc: hexagon::S2_lsr_i_p_acc
__builtin_HEXAGON_S2_lsr_i_p_and: hexagon::S2_lsr_i_p_and
__builtin_HEXAGON_S2_lsr_i_p_nac: hexagon::S2_lsr_i_p_nac
__builtin_HEXAGON_S2_lsr_i_p_or: hexagon::S2_lsr_i_p_or
__builtin_HEXAGON_S2_lsr_i_p_xacc: hexagon::S2_lsr_i_p_xacc
__builtin_HEXAGON_S2_lsr_i_r: hexagon::S2_lsr_i_r
__builtin_HEXAGON_S2_lsr_i_r_acc: hexagon::S2_lsr_i_r_acc
__builtin_HEXAGON_S2_lsr_i_r_and: hexagon::S2_lsr_i_r_and
__builtin_HEXAGON_S2_lsr_i_r_nac: hexagon::S2_lsr_i_r_nac
__builtin_HEXAGON_S2_lsr_i_r_or: hexagon::S2_lsr_i_r_or
__builtin_HEXAGON_S2_lsr_i_r_xacc: hexagon::S2_lsr_i_r_xacc
__builtin_HEXAGON_S2_lsr_i_vh: hexagon::S2_lsr_i_vh
__builtin_HEXAGON_S2_lsr_i_vw: hexagon::S2_lsr_i_vw
__builtin_HEXAGON_S2_lsr_r_p: hexagon::S2_lsr_r_p
__builtin_HEXAGON_S2_lsr_r_p_acc: hexagon::S2_lsr_r_p_acc
__builtin_HEXAGON_S2_lsr_r_p_and: hexagon::S2_lsr_r_p_and
__builtin_HEXAGON_S2_lsr_r_p_nac: hexagon::S2_lsr_r_p_nac
__builtin_HEXAGON_S2_lsr_r_p_or: hexagon::S2_lsr_r_p_or
__builtin_HEXAGON_S2_lsr_r_p_xor: hexagon::S2_lsr_r_p_xor
__builtin_HEXAGON_S2_lsr_r_r: hexagon::S2_lsr_r_r
__builtin_HEXAGON_S2_lsr_r_r_acc: hexagon::S2_lsr_r_r_acc
__builtin_HEXAGON_S2_lsr_r_r_and: hexagon::S2_lsr_r_r_and
__builtin_HEXAGON_S2_lsr_r_r_nac: hexagon::S2_lsr_r_r_nac
__builtin_HEXAGON_S2_lsr_r_r_or: hexagon::S2_lsr_r_r_or
__builtin_HEXAGON_S2_lsr_r_vh: hexagon::S2_lsr_r_vh
__builtin_HEXAGON_S2_lsr_r_vw: hexagon::S2_lsr_r_vw
__builtin_HEXAGON_S2_packhl: hexagon::S2_packhl
__builtin_HEXAGON_S2_parityp: hexagon::S2_parityp
__builtin_HEXAGON_S2_setbit_i: hexagon::S2_setbit_i
__builtin_HEXAGON_S2_setbit_r: hexagon::S2_setbit_r
__builtin_HEXAGON_S2_shuffeb: hexagon::S2_shuffeb
__builtin_HEXAGON_S2_shuffeh: hexagon::S2_shuffeh
__builtin_HEXAGON_S2_shuffob: hexagon::S2_shuffob
__builtin_HEXAGON_S2_shuffoh: hexagon::S2_shuffoh
__builtin_HEXAGON_S2_svsathb: hexagon::S2_svsathb
__builtin_HEXAGON_S2_svsathub: hexagon::S2_svsathub
__builtin_HEXAGON_S2_tableidxb_goodsyntax: hexagon::S2_tableidxb_goodsyntax
__builtin_HEXAGON_S2_tableidxd_goodsyntax: hexagon::S2_tableidxd_goodsyntax
__builtin_HEXAGON_S2_tableidxh_goodsyntax: hexagon::S2_tableidxh_goodsyntax
__builtin_HEXAGON_S2_tableidxw_goodsyntax: hexagon::S2_tableidxw_goodsyntax
__builtin_HEXAGON_S2_togglebit_i: hexagon::S2_togglebit_i
__builtin_HEXAGON_S2_togglebit_r: hexagon::S2_togglebit_r
__builtin_HEXAGON_S2_tstbit_i: hexagon::S2_tstbit_i
__builtin_HEXAGON_S2_tstbit_r: hexagon::S2_tstbit_r
__builtin_HEXAGON_S2_valignib: hexagon::S2_valignib
__builtin_HEXAGON_S2_valignrb: hexagon::S2_valignrb
__builtin_HEXAGON_S2_vcnegh: hexagon::S2_vcnegh
__builtin_HEXAGON_S2_vcrotate: hexagon::S2_vcrotate
__builtin_HEXAGON_S2_vrcnegh: hexagon::S2_vrcnegh
__builtin_HEXAGON_S2_vrndpackwh: hexagon::S2_vrndpackwh
__builtin_HEXAGON_S2_vrndpackwhs: hexagon::S2_vrndpackwhs
__builtin_HEXAGON_S2_vsathb: hexagon::S2_vsathb
__builtin_HEXAGON_S2_vsathb_nopack: hexagon::S2_vsathb_nopack
__builtin_HEXAGON_S2_vsathub: hexagon::S2_vsathub
__builtin_HEXAGON_S2_vsathub_nopack: hexagon::S2_vsathub_nopack
__builtin_HEXAGON_S2_vsatwh: hexagon::S2_vsatwh
__builtin_HEXAGON_S2_vsatwh_nopack: hexagon::S2_vsatwh_nopack
__builtin_HEXAGON_S2_vsatwuh: hexagon::S2_vsatwuh
__builtin_HEXAGON_S2_vsatwuh_nopack: hexagon::S2_vsatwuh_nopack
__builtin_HEXAGON_S2_vsplatrb: hexagon::S2_vsplatrb
__builtin_HEXAGON_S2_vsplatrh: hexagon::S2_vsplatrh
__builtin_HEXAGON_S2_vspliceib: hexagon::S2_vspliceib
__builtin_HEXAGON_S2_vsplicerb: hexagon::S2_vsplicerb
__builtin_HEXAGON_S2_vsxtbh: hexagon::S2_vsxtbh
__builtin_HEXAGON_S2_vsxthw: hexagon::S2_vsxthw
__builtin_HEXAGON_S2_vtrunehb: hexagon::S2_vtrunehb
__builtin_HEXAGON_S2_vtrunewh: hexagon::S2_vtrunewh
__builtin_HEXAGON_S2_vtrunohb: hexagon::S2_vtrunohb
__builtin_HEXAGON_S2_vtrunowh: hexagon::S2_vtrunowh
__builtin_HEXAGON_S2_vzxtbh: hexagon::S2_vzxtbh
__builtin_HEXAGON_S2_vzxthw: hexagon::S2_vzxthw
__builtin_HEXAGON_S4_addaddi: hexagon::S4_addaddi
__builtin_HEXAGON_S4_addi_asl_ri: hexagon::S4_addi_asl_ri
__builtin_HEXAGON_S4_addi_lsr_ri: hexagon::S4_addi_lsr_ri
__builtin_HEXAGON_S4_andi_asl_ri: hexagon::S4_andi_asl_ri
__builtin_HEXAGON_S4_andi_lsr_ri: hexagon::S4_andi_lsr_ri
__builtin_HEXAGON_S4_clbaddi: hexagon::S4_clbaddi
__builtin_HEXAGON_S4_clbpaddi: hexagon::S4_clbpaddi
__builtin_HEXAGON_S4_clbpnorm: hexagon::S4_clbpnorm
__builtin_HEXAGON_S4_extract: hexagon::S4_extract
__builtin_HEXAGON_S4_extract_rp: hexagon::S4_extract_rp
__builtin_HEXAGON_S4_extractp: hexagon::S4_extractp
__builtin_HEXAGON_S4_extractp_rp: hexagon::S4_extractp_rp
__builtin_HEXAGON_S4_lsli: hexagon::S4_lsli
__builtin_HEXAGON_S4_ntstbit_i: hexagon::S4_ntstbit_i
__builtin_HEXAGON_S4_ntstbit_r: hexagon::S4_ntstbit_r
__builtin_HEXAGON_S4_or_andi: hexagon::S4_or_andi
__builtin_HEXAGON_S4_or_andix: hexagon::S4_or_andix
__builtin_HEXAGON_S4_or_ori: hexagon::S4_or_ori
__builtin_HEXAGON_S4_ori_asl_ri: hexagon::S4_ori_asl_ri
__builtin_HEXAGON_S4_ori_lsr_ri: hexagon::S4_ori_lsr_ri
__builtin_HEXAGON_S4_parity: hexagon::S4_parity
__builtin_HEXAGON_S4_subaddi: hexagon::S4_subaddi
__builtin_HEXAGON_S4_subi_asl_ri: hexagon::S4_subi_asl_ri
__builtin_HEXAGON_S4_subi_lsr_ri: hexagon::S4_subi_lsr_ri
__builtin_HEXAGON_S4_vrcrotate: hexagon::S4_vrcrotate
__builtin_HEXAGON_S4_vrcrotate_acc: hexagon::S4_vrcrotate_acc
__builtin_HEXAGON_S4_vxaddsubh: hexagon::S4_vxaddsubh
__builtin_HEXAGON_S4_vxaddsubhr: hexagon::S4_vxaddsubhr
__builtin_HEXAGON_S4_vxaddsubw: hexagon::S4_vxaddsubw
__builtin_HEXAGON_S4_vxsubaddh: hexagon::S4_vxsubaddh
__builtin_HEXAGON_S4_vxsubaddhr: hexagon::S4_vxsubaddhr
__builtin_HEXAGON_S4_vxsubaddw: hexagon::S4_vxsubaddw
__builtin_HEXAGON_S5_asrhub_rnd_sat_goodsyntax: hexagon::S5_asrhub_rnd_sat_goodsyntax
__builtin_HEXAGON_S5_asrhub_sat: hexagon::S5_asrhub_sat
__builtin_HEXAGON_S5_popcountp: hexagon::S5_popcountp
__builtin_HEXAGON_S5_vasrhrnd_goodsyntax: hexagon::S5_vasrhrnd_goodsyntax
__builtin_HEXAGON_S6_rol_i_p: hexagon::S6_rol_i_p
__builtin_HEXAGON_S6_rol_i_p_acc: hexagon::S6_rol_i_p_acc
__builtin_HEXAGON_S6_rol_i_p_and: hexagon::S6_rol_i_p_and
__builtin_HEXAGON_S6_rol_i_p_nac: hexagon::S6_rol_i_p_nac
__builtin_HEXAGON_S6_rol_i_p_or: hexagon::S6_rol_i_p_or
__builtin_HEXAGON_S6_rol_i_p_xacc: hexagon::S6_rol_i_p_xacc
__builtin_HEXAGON_S6_rol_i_r: hexagon::S6_rol_i_r
__builtin_HEXAGON_S6_rol_i_r_acc: hexagon::S6_rol_i_r_acc
__builtin_HEXAGON_S6_rol_i_r_and: hexagon::S6_rol_i_r_and
__builtin_HEXAGON_S6_rol_i_r_nac: hexagon::S6_rol_i_r_nac
__builtin_HEXAGON_S6_rol_i_r_or: hexagon::S6_rol_i_r_or
__builtin_HEXAGON_S6_rol_i_r_xacc: hexagon::S6_rol_i_r_xacc
__builtin_HEXAGON_S6_vsplatrbp: hexagon::S6_vsplatrbp
__builtin_HEXAGON_S6_vtrunehb_ppp: hexagon::S6_vtrunehb_ppp
__builtin_HEXAGON_S6_vtrunohb_ppp: hexagon::S6_vtrunohb_ppp
__builtin_HEXAGON_V6_extractw: hexagon::V6_extractw
__builtin_HEXAGON_V6_extractw_128B: hexagon::V6_extractw_128B
__builtin_HEXAGON_V6_hi: hexagon::V6_hi
__builtin_HEXAGON_V6_hi_128B: hexagon::V6_hi_128B
__builtin_HEXAGON_V6_lo: hexagon::V6_lo
__builtin_HEXAGON_V6_lo_128B: hexagon::V6_lo_128B
__builtin_HEXAGON_V6_lvsplatw: hexagon::V6_lvsplatw
__builtin_HEXAGON_V6_lvsplatw_128B: hexagon::V6_lvsplatw_128B
__builtin_HEXAGON_V6_vabsdiffh: hexagon::V6_vabsdiffh
__builtin_HEXAGON_V6_vabsdiffh_128B: hexagon::V6_vabsdiffh_128B
__builtin_HEXAGON_V6_vabsdiffub: hexagon::V6_vabsdiffub
__builtin_HEXAGON_V6_vabsdiffub_128B: hexagon::V6_vabsdiffub_128B
__builtin_HEXAGON_V6_vabsdiffuh: hexagon::V6_vabsdiffuh
__builtin_HEXAGON_V6_vabsdiffuh_128B: hexagon::V6_vabsdiffuh_128B
__builtin_HEXAGON_V6_vabsdiffw: hexagon::V6_vabsdiffw
__builtin_HEXAGON_V6_vabsdiffw_128B: hexagon::V6_vabsdiffw_128B
__builtin_HEXAGON_V6_vabsh: hexagon::V6_vabsh
__builtin_HEXAGON_V6_vabsh_128B: hexagon::V6_vabsh_128B
__builtin_HEXAGON_V6_vabsh_sat: hexagon::V6_vabsh_sat
__builtin_HEXAGON_V6_vabsh_sat_128B: hexagon::V6_vabsh_sat_128B
__builtin_HEXAGON_V6_vabsw: hexagon::V6_vabsw
__builtin_HEXAGON_V6_vabsw_128B: hexagon::V6_vabsw_128B
__builtin_HEXAGON_V6_vabsw_sat: hexagon::V6_vabsw_sat
__builtin_HEXAGON_V6_vabsw_sat_128B: hexagon::V6_vabsw_sat_128B
__builtin_HEXAGON_V6_vaddb: hexagon::V6_vaddb
__builtin_HEXAGON_V6_vaddb_128B: hexagon::V6_vaddb_128B
__builtin_HEXAGON_V6_vaddb_dv: hexagon::V6_vaddb_dv
__builtin_HEXAGON_V6_vaddb_dv_128B: hexagon::V6_vaddb_dv_128B
__builtin_HEXAGON_V6_vaddh: hexagon::V6_vaddh
__builtin_HEXAGON_V6_vaddh_128B: hexagon::V6_vaddh_128B
__builtin_HEXAGON_V6_vaddh_dv: hexagon::V6_vaddh_dv
__builtin_HEXAGON_V6_vaddh_dv_128B: hexagon::V6_vaddh_dv_128B
__builtin_HEXAGON_V6_vaddhsat: hexagon::V6_vaddhsat
__builtin_HEXAGON_V6_vaddhsat_128B: hexagon::V6_vaddhsat_128B
__builtin_HEXAGON_V6_vaddhsat_dv: hexagon::V6_vaddhsat_dv
__builtin_HEXAGON_V6_vaddhsat_dv_128B: hexagon::V6_vaddhsat_dv_128B
__builtin_HEXAGON_V6_vaddhw: hexagon::V6_vaddhw
__builtin_HEXAGON_V6_vaddhw_128B: hexagon::V6_vaddhw_128B
__builtin_HEXAGON_V6_vaddubh: hexagon::V6_vaddubh
__builtin_HEXAGON_V6_vaddubh_128B: hexagon::V6_vaddubh_128B
__builtin_HEXAGON_V6_vaddubsat: hexagon::V6_vaddubsat
__builtin_HEXAGON_V6_vaddubsat_128B: hexagon::V6_vaddubsat_128B
__builtin_HEXAGON_V6_vaddubsat_dv: hexagon::V6_vaddubsat_dv
__builtin_HEXAGON_V6_vaddubsat_dv_128B: hexagon::V6_vaddubsat_dv_128B
__builtin_HEXAGON_V6_vadduhsat: hexagon::V6_vadduhsat
__builtin_HEXAGON_V6_vadduhsat_128B: hexagon::V6_vadduhsat_128B
__builtin_HEXAGON_V6_vadduhsat_dv: hexagon::V6_vadduhsat_dv
__builtin_HEXAGON_V6_vadduhsat_dv_128B: hexagon::V6_vadduhsat_dv_128B
__builtin_HEXAGON_V6_vadduhw: hexagon::V6_vadduhw
__builtin_HEXAGON_V6_vadduhw_128B: hexagon::V6_vadduhw_128B
__builtin_HEXAGON_V6_vaddw: hexagon::V6_vaddw
__builtin_HEXAGON_V6_vaddw_128B: hexagon::V6_vaddw_128B
__builtin_HEXAGON_V6_vaddw_dv: hexagon::V6_vaddw_dv
__builtin_HEXAGON_V6_vaddw_dv_128B: hexagon::V6_vaddw_dv_128B
__builtin_HEXAGON_V6_vaddwsat: hexagon::V6_vaddwsat
__builtin_HEXAGON_V6_vaddwsat_128B: hexagon::V6_vaddwsat_128B
__builtin_HEXAGON_V6_vaddwsat_dv: hexagon::V6_vaddwsat_dv
__builtin_HEXAGON_V6_vaddwsat_dv_128B: hexagon::V6_vaddwsat_dv_128B
__builtin_HEXAGON_V6_valignb: hexagon::V6_valignb
__builtin_HEXAGON_V6_valignb_128B: hexagon::V6_valignb_128B
__builtin_HEXAGON_V6_valignbi: hexagon::V6_valignbi
__builtin_HEXAGON_V6_valignbi_128B: hexagon::V6_valignbi_128B
__builtin_HEXAGON_V6_vand: hexagon::V6_vand
__builtin_HEXAGON_V6_vand_128B: hexagon::V6_vand_128B
__builtin_HEXAGON_V6_vaslh: hexagon::V6_vaslh
__builtin_HEXAGON_V6_vaslh_128B: hexagon::V6_vaslh_128B
__builtin_HEXAGON_V6_vaslhv: hexagon::V6_vaslhv
__builtin_HEXAGON_V6_vaslhv_128B: hexagon::V6_vaslhv_128B
__builtin_HEXAGON_V6_vaslw: hexagon::V6_vaslw
__builtin_HEXAGON_V6_vaslw_128B: hexagon::V6_vaslw_128B
__builtin_HEXAGON_V6_vaslw_acc: hexagon::V6_vaslw_acc
__builtin_HEXAGON_V6_vaslw_acc_128B: hexagon::V6_vaslw_acc_128B
__builtin_HEXAGON_V6_vaslwv: hexagon::V6_vaslwv
__builtin_HEXAGON_V6_vaslwv_128B: hexagon::V6_vaslwv_128B
__builtin_HEXAGON_V6_vasrh: hexagon::V6_vasrh
__builtin_HEXAGON_V6_vasrh_128B: hexagon::V6_vasrh_128B
__builtin_HEXAGON_V6_vasrhbrndsat: hexagon::V6_vasrhbrndsat
__builtin_HEXAGON_V6_vasrhbrndsat_128B: hexagon::V6_vasrhbrndsat_128B
__builtin_HEXAGON_V6_vasrhubrndsat: hexagon::V6_vasrhubrndsat
__builtin_HEXAGON_V6_vasrhubrndsat_128B: hexagon::V6_vasrhubrndsat_128B
__builtin_HEXAGON_V6_vasrhubsat: hexagon::V6_vasrhubsat
__builtin_HEXAGON_V6_vasrhubsat_128B: hexagon::V6_vasrhubsat_128B
__builtin_HEXAGON_V6_vasrhv: hexagon::V6_vasrhv
__builtin_HEXAGON_V6_vasrhv_128B: hexagon::V6_vasrhv_128B
__builtin_HEXAGON_V6_vasrw: hexagon::V6_vasrw
__builtin_HEXAGON_V6_vasrw_128B: hexagon::V6_vasrw_128B
__builtin_HEXAGON_V6_vasrw_acc: hexagon::V6_vasrw_acc
__builtin_HEXAGON_V6_vasrw_acc_128B: hexagon::V6_vasrw_acc_128B
__builtin_HEXAGON_V6_vasrwh: hexagon::V6_vasrwh
__builtin_HEXAGON_V6_vasrwh_128B: hexagon::V6_vasrwh_128B
__builtin_HEXAGON_V6_vasrwhrndsat: hexagon::V6_vasrwhrndsat
__builtin_HEXAGON_V6_vasrwhrndsat_128B: hexagon::V6_vasrwhrndsat_128B
__builtin_HEXAGON_V6_vasrwhsat: hexagon::V6_vasrwhsat
__builtin_HEXAGON_V6_vasrwhsat_128B: hexagon::V6_vasrwhsat_128B
__builtin_HEXAGON_V6_vasrwuhsat: hexagon::V6_vasrwuhsat
__builtin_HEXAGON_V6_vasrwuhsat_128B: hexagon::V6_vasrwuhsat_128B
__builtin_HEXAGON_V6_vasrwv: hexagon::V6_vasrwv
__builtin_HEXAGON_V6_vasrwv_128B: hexagon::V6_vasrwv_128B
__builtin_HEXAGON_V6_vassign: hexagon::V6_vassign
__builtin_HEXAGON_V6_vassign_128B: hexagon::V6_vassign_128B
__builtin_HEXAGON_V6_vassignp: hexagon::V6_vassignp
__builtin_HEXAGON_V6_vassignp_128B: hexagon::V6_vassignp_128B
__builtin_HEXAGON_V6_vavgh: hexagon::V6_vavgh
__builtin_HEXAGON_V6_vavgh_128B: hexagon::V6_vavgh_128B
__builtin_HEXAGON_V6_vavghrnd: hexagon::V6_vavghrnd
__builtin_HEXAGON_V6_vavghrnd_128B: hexagon::V6_vavghrnd_128B
__builtin_HEXAGON_V6_vavgub: hexagon::V6_vavgub
__builtin_HEXAGON_V6_vavgub_128B: hexagon::V6_vavgub_128B
__builtin_HEXAGON_V6_vavgubrnd: hexagon::V6_vavgubrnd
__builtin_HEXAGON_V6_vavgubrnd_128B: hexagon::V6_vavgubrnd_128B
__builtin_HEXAGON_V6_vavguh: hexagon::V6_vavguh
__builtin_HEXAGON_V6_vavguh_128B: hexagon::V6_vavguh_128B
__builtin_HEXAGON_V6_vavguhrnd: hexagon::V6_vavguhrnd
__builtin_HEXAGON_V6_vavguhrnd_128B: hexagon::V6_vavguhrnd_128B
__builtin_HEXAGON_V6_vavgw: hexagon::V6_vavgw
__builtin_HEXAGON_V6_vavgw_128B: hexagon::V6_vavgw_128B
__builtin_HEXAGON_V6_vavgwrnd: hexagon::V6_vavgwrnd
__builtin_HEXAGON_V6_vavgwrnd_128B: hexagon::V6_vavgwrnd_128B
__builtin_HEXAGON_V6_vcl0h: hexagon::V6_vcl0h
__builtin_HEXAGON_V6_vcl0h_128B: hexagon::V6_vcl0h_128B
__builtin_HEXAGON_V6_vcl0w: hexagon::V6_vcl0w
__builtin_HEXAGON_V6_vcl0w_128B: hexagon::V6_vcl0w_128B
__builtin_HEXAGON_V6_vcombine: hexagon::V6_vcombine
__builtin_HEXAGON_V6_vcombine_128B: hexagon::V6_vcombine_128B
__builtin_HEXAGON_V6_vd0: hexagon::V6_vd0
__builtin_HEXAGON_V6_vd0_128B: hexagon::V6_vd0_128B
__builtin_HEXAGON_V6_vdealb: hexagon::V6_vdealb
__builtin_HEXAGON_V6_vdealb4w: hexagon::V6_vdealb4w
__builtin_HEXAGON_V6_vdealb4w_128B: hexagon::V6_vdealb4w_128B
__builtin_HEXAGON_V6_vdealb_128B: hexagon::V6_vdealb_128B
__builtin_HEXAGON_V6_vdealh: hexagon::V6_vdealh
__builtin_HEXAGON_V6_vdealh_128B: hexagon::V6_vdealh_128B
__builtin_HEXAGON_V6_vdealvdd: hexagon::V6_vdealvdd
__builtin_HEXAGON_V6_vdealvdd_128B: hexagon::V6_vdealvdd_128B
__builtin_HEXAGON_V6_vdelta: hexagon::V6_vdelta
__builtin_HEXAGON_V6_vdelta_128B: hexagon::V6_vdelta_128B
__builtin_HEXAGON_V6_vdmpybus: hexagon::V6_vdmpybus
__builtin_HEXAGON_V6_vdmpybus_128B: hexagon::V6_vdmpybus_128B
__builtin_HEXAGON_V6_vdmpybus_acc: hexagon::V6_vdmpybus_acc
__builtin_HEXAGON_V6_vdmpybus_acc_128B: hexagon::V6_vdmpybus_acc_128B
__builtin_HEXAGON_V6_vdmpybus_dv: hexagon::V6_vdmpybus_dv
__builtin_HEXAGON_V6_vdmpybus_dv_128B: hexagon::V6_vdmpybus_dv_128B
__builtin_HEXAGON_V6_vdmpybus_dv_acc: hexagon::V6_vdmpybus_dv_acc
__builtin_HEXAGON_V6_vdmpybus_dv_acc_128B: hexagon::V6_vdmpybus_dv_acc_128B
__builtin_HEXAGON_V6_vdmpyhb: hexagon::V6_vdmpyhb
__builtin_HEXAGON_V6_vdmpyhb_128B: hexagon::V6_vdmpyhb_128B
__builtin_HEXAGON_V6_vdmpyhb_acc: hexagon::V6_vdmpyhb_acc
__builtin_HEXAGON_V6_vdmpyhb_acc_128B: hexagon::V6_vdmpyhb_acc_128B
__builtin_HEXAGON_V6_vdmpyhb_dv: hexagon::V6_vdmpyhb_dv
__builtin_HEXAGON_V6_vdmpyhb_dv_128B: hexagon::V6_vdmpyhb_dv_128B
__builtin_HEXAGON_V6_vdmpyhb_dv_acc: hexagon::V6_vdmpyhb_dv_acc
__builtin_HEXAGON_V6_vdmpyhb_dv_acc_128B: hexagon::V6_vdmpyhb_dv_acc_128B
__builtin_HEXAGON_V6_vdmpyhisat: hexagon::V6_vdmpyhisat
__builtin_HEXAGON_V6_vdmpyhisat_128B: hexagon::V6_vdmpyhisat_128B
__builtin_HEXAGON_V6_vdmpyhisat_acc: hexagon::V6_vdmpyhisat_acc
__builtin_HEXAGON_V6_vdmpyhisat_acc_128B: hexagon::V6_vdmpyhisat_acc_128B
__builtin_HEXAGON_V6_vdmpyhsat: hexagon::V6_vdmpyhsat
__builtin_HEXAGON_V6_vdmpyhsat_128B: hexagon::V6_vdmpyhsat_128B
__builtin_HEXAGON_V6_vdmpyhsat_acc: hexagon::V6_vdmpyhsat_acc
__builtin_HEXAGON_V6_vdmpyhsat_acc_128B: hexagon::V6_vdmpyhsat_acc_128B
__builtin_HEXAGON_V6_vdmpyhsuisat: hexagon::V6_vdmpyhsuisat
__builtin_HEXAGON_V6_vdmpyhsuisat_128B: hexagon::V6_vdmpyhsuisat_128B
__builtin_HEXAGON_V6_vdmpyhsuisat_acc: hexagon::V6_vdmpyhsuisat_acc
__builtin_HEXAGON_V6_vdmpyhsuisat_acc_128B: hexagon::V6_vdmpyhsuisat_acc_128B
__builtin_HEXAGON_V6_vdmpyhsusat: hexagon::V6_vdmpyhsusat
__builtin_HEXAGON_V6_vdmpyhsusat_128B: hexagon::V6_vdmpyhsusat_128B
__builtin_HEXAGON_V6_vdmpyhsusat_acc: hexagon::V6_vdmpyhsusat_acc
__builtin_HEXAGON_V6_vdmpyhsusat_acc_128B: hexagon::V6_vdmpyhsusat_acc_128B
__builtin_HEXAGON_V6_vdmpyhvsat: hexagon::V6_vdmpyhvsat
__builtin_HEXAGON_V6_vdmpyhvsat_128B: hexagon::V6_vdmpyhvsat_128B
__builtin_HEXAGON_V6_vdmpyhvsat_acc: hexagon::V6_vdmpyhvsat_acc
__builtin_HEXAGON_V6_vdmpyhvsat_acc_128B: hexagon::V6_vdmpyhvsat_acc_128B
__builtin_HEXAGON_V6_vdsaduh: hexagon::V6_vdsaduh
__builtin_HEXAGON_V6_vdsaduh_128B: hexagon::V6_vdsaduh_128B
__builtin_HEXAGON_V6_vdsaduh_acc: hexagon::V6_vdsaduh_acc
__builtin_HEXAGON_V6_vdsaduh_acc_128B: hexagon::V6_vdsaduh_acc_128B
__builtin_HEXAGON_V6_vinsertwr: hexagon::V6_vinsertwr
__builtin_HEXAGON_V6_vinsertwr_128B: hexagon::V6_vinsertwr_128B
__builtin_HEXAGON_V6_vlalignb: hexagon::V6_vlalignb
__builtin_HEXAGON_V6_vlalignb_128B: hexagon::V6_vlalignb_128B
__builtin_HEXAGON_V6_vlalignbi: hexagon::V6_vlalignbi
__builtin_HEXAGON_V6_vlalignbi_128B: hexagon::V6_vlalignbi_128B
__builtin_HEXAGON_V6_vlsrh: hexagon::V6_vlsrh
__builtin_HEXAGON_V6_vlsrh_128B: hexagon::V6_vlsrh_128B
__builtin_HEXAGON_V6_vlsrhv: hexagon::V6_vlsrhv
__builtin_HEXAGON_V6_vlsrhv_128B: hexagon::V6_vlsrhv_128B
__builtin_HEXAGON_V6_vlsrw: hexagon::V6_vlsrw
__builtin_HEXAGON_V6_vlsrw_128B: hexagon::V6_vlsrw_128B
__builtin_HEXAGON_V6_vlsrwv: hexagon::V6_vlsrwv
__builtin_HEXAGON_V6_vlsrwv_128B: hexagon::V6_vlsrwv_128B
__builtin_HEXAGON_V6_vlutb: hexagon::V6_vlutb
__builtin_HEXAGON_V6_vlutb_128B: hexagon::V6_vlutb_128B
__builtin_HEXAGON_V6_vlutb_acc: hexagon::V6_vlutb_acc
__builtin_HEXAGON_V6_vlutb_acc_128B: hexagon::V6_vlutb_acc_128B
__builtin_HEXAGON_V6_vlutb_dv: hexagon::V6_vlutb_dv
__builtin_HEXAGON_V6_vlutb_dv_128B: hexagon::V6_vlutb_dv_128B
__builtin_HEXAGON_V6_vlutb_dv_acc: hexagon::V6_vlutb_dv_acc
__builtin_HEXAGON_V6_vlutb_dv_acc_128B: hexagon::V6_vlutb_dv_acc_128B
__builtin_HEXAGON_V6_vlutvvb: hexagon::V6_vlutvvb
__builtin_HEXAGON_V6_vlutvvb_128B: hexagon::V6_vlutvvb_128B
__builtin_HEXAGON_V6_vlutvvb_oracc: hexagon::V6_vlutvvb_oracc
__builtin_HEXAGON_V6_vlutvvb_oracc_128B: hexagon::V6_vlutvvb_oracc_128B
__builtin_HEXAGON_V6_vlutvwh: hexagon::V6_vlutvwh
__builtin_HEXAGON_V6_vlutvwh_128B: hexagon::V6_vlutvwh_128B
__builtin_HEXAGON_V6_vlutvwh_oracc: hexagon::V6_vlutvwh_oracc
__builtin_HEXAGON_V6_vlutvwh_oracc_128B: hexagon::V6_vlutvwh_oracc_128B
__builtin_HEXAGON_V6_vmaxh: hexagon::V6_vmaxh
__builtin_HEXAGON_V6_vmaxh_128B: hexagon::V6_vmaxh_128B
__builtin_HEXAGON_V6_vmaxub: hexagon::V6_vmaxub
__builtin_HEXAGON_V6_vmaxub_128B: hexagon::V6_vmaxub_128B
__builtin_HEXAGON_V6_vmaxuh: hexagon::V6_vmaxuh
__builtin_HEXAGON_V6_vmaxuh_128B: hexagon::V6_vmaxuh_128B
__builtin_HEXAGON_V6_vmaxw: hexagon::V6_vmaxw
__builtin_HEXAGON_V6_vmaxw_128B: hexagon::V6_vmaxw_128B
__builtin_HEXAGON_V6_vminh: hexagon::V6_vminh
__builtin_HEXAGON_V6_vminh_128B: hexagon::V6_vminh_128B
__builtin_HEXAGON_V6_vminub: hexagon::V6_vminub
__builtin_HEXAGON_V6_vminub_128B: hexagon::V6_vminub_128B
__builtin_HEXAGON_V6_vminuh: hexagon::V6_vminuh
__builtin_HEXAGON_V6_vminuh_128B: hexagon::V6_vminuh_128B
__builtin_HEXAGON_V6_vminw: hexagon::V6_vminw
__builtin_HEXAGON_V6_vminw_128B: hexagon::V6_vminw_128B
__builtin_HEXAGON_V6_vmpabus: hexagon::V6_vmpabus
__builtin_HEXAGON_V6_vmpabus_128B: hexagon::V6_vmpabus_128B
__builtin_HEXAGON_V6_vmpabus_acc: hexagon::V6_vmpabus_acc
__builtin_HEXAGON_V6_vmpabus_acc_128B: hexagon::V6_vmpabus_acc_128B
__builtin_HEXAGON_V6_vmpabusv: hexagon::V6_vmpabusv
__builtin_HEXAGON_V6_vmpabusv_128B: hexagon::V6_vmpabusv_128B
__builtin_HEXAGON_V6_vmpabuuv: hexagon::V6_vmpabuuv
__builtin_HEXAGON_V6_vmpabuuv_128B: hexagon::V6_vmpabuuv_128B
__builtin_HEXAGON_V6_vmpahb: hexagon::V6_vmpahb
__builtin_HEXAGON_V6_vmpahb_128B: hexagon::V6_vmpahb_128B
__builtin_HEXAGON_V6_vmpahb_acc: hexagon::V6_vmpahb_acc
__builtin_HEXAGON_V6_vmpahb_acc_128B: hexagon::V6_vmpahb_acc_128B
__builtin_HEXAGON_V6_vmpybus: hexagon::V6_vmpybus
__builtin_HEXAGON_V6_vmpybus_128B: hexagon::V6_vmpybus_128B
__builtin_HEXAGON_V6_vmpybus_acc: hexagon::V6_vmpybus_acc
__builtin_HEXAGON_V6_vmpybus_acc_128B: hexagon::V6_vmpybus_acc_128B
__builtin_HEXAGON_V6_vmpybusv: hexagon::V6_vmpybusv
__builtin_HEXAGON_V6_vmpybusv_128B: hexagon::V6_vmpybusv_128B
__builtin_HEXAGON_V6_vmpybusv_acc: hexagon::V6_vmpybusv_acc
__builtin_HEXAGON_V6_vmpybusv_acc_128B: hexagon::V6_vmpybusv_acc_128B
__builtin_HEXAGON_V6_vmpybv: hexagon::V6_vmpybv
__builtin_HEXAGON_V6_vmpybv_128B: hexagon::V6_vmpybv_128B
__builtin_HEXAGON_V6_vmpybv_acc: hexagon::V6_vmpybv_acc
__builtin_HEXAGON_V6_vmpybv_acc_128B: hexagon::V6_vmpybv_acc_128B
__builtin_HEXAGON_V6_vmpyewuh: hexagon::V6_vmpyewuh
__builtin_HEXAGON_V6_vmpyewuh_128B: hexagon::V6_vmpyewuh_128B
__builtin_HEXAGON_V6_vmpyh: hexagon::V6_vmpyh
__builtin_HEXAGON_V6_vmpyh_128B: hexagon::V6_vmpyh_128B
__builtin_HEXAGON_V6_vmpyhsat_acc: hexagon::V6_vmpyhsat_acc
__builtin_HEXAGON_V6_vmpyhsat_acc_128B: hexagon::V6_vmpyhsat_acc_128B
__builtin_HEXAGON_V6_vmpyhsrs: hexagon::V6_vmpyhsrs
__builtin_HEXAGON_V6_vmpyhsrs_128B: hexagon::V6_vmpyhsrs_128B
__builtin_HEXAGON_V6_vmpyhss: hexagon::V6_vmpyhss
__builtin_HEXAGON_V6_vmpyhss_128B: hexagon::V6_vmpyhss_128B
__builtin_HEXAGON_V6_vmpyhus: hexagon::V6_vmpyhus
__builtin_HEXAGON_V6_vmpyhus_128B: hexagon::V6_vmpyhus_128B
__builtin_HEXAGON_V6_vmpyhus_acc: hexagon::V6_vmpyhus_acc
__builtin_HEXAGON_V6_vmpyhus_acc_128B: hexagon::V6_vmpyhus_acc_128B
__builtin_HEXAGON_V6_vmpyhv: hexagon::V6_vmpyhv
__builtin_HEXAGON_V6_vmpyhv_128B: hexagon::V6_vmpyhv_128B
__builtin_HEXAGON_V6_vmpyhv_acc: hexagon::V6_vmpyhv_acc
__builtin_HEXAGON_V6_vmpyhv_acc_128B: hexagon::V6_vmpyhv_acc_128B
__builtin_HEXAGON_V6_vmpyhvsrs: hexagon::V6_vmpyhvsrs
__builtin_HEXAGON_V6_vmpyhvsrs_128B: hexagon::V6_vmpyhvsrs_128B
__builtin_HEXAGON_V6_vmpyieoh: hexagon::V6_vmpyieoh
__builtin_HEXAGON_V6_vmpyieoh_128B: hexagon::V6_vmpyieoh_128B
__builtin_HEXAGON_V6_vmpyiewh_acc: hexagon::V6_vmpyiewh_acc
__builtin_HEXAGON_V6_vmpyiewh_acc_128B: hexagon::V6_vmpyiewh_acc_128B
__builtin_HEXAGON_V6_vmpyiewuh: hexagon::V6_vmpyiewuh
__builtin_HEXAGON_V6_vmpyiewuh_128B: hexagon::V6_vmpyiewuh_128B
__builtin_HEXAGON_V6_vmpyiewuh_acc: hexagon::V6_vmpyiewuh_acc
__builtin_HEXAGON_V6_vmpyiewuh_acc_128B: hexagon::V6_vmpyiewuh_acc_128B
__builtin_HEXAGON_V6_vmpyih: hexagon::V6_vmpyih
__builtin_HEXAGON_V6_vmpyih_128B: hexagon::V6_vmpyih_128B
__builtin_HEXAGON_V6_vmpyih_acc: hexagon::V6_vmpyih_acc
__builtin_HEXAGON_V6_vmpyih_acc_128B: hexagon::V6_vmpyih_acc_128B
__builtin_HEXAGON_V6_vmpyihb: hexagon::V6_vmpyihb
__builtin_HEXAGON_V6_vmpyihb_128B: hexagon::V6_vmpyihb_128B
__builtin_HEXAGON_V6_vmpyihb_acc: hexagon::V6_vmpyihb_acc
__builtin_HEXAGON_V6_vmpyihb_acc_128B: hexagon::V6_vmpyihb_acc_128B
__builtin_HEXAGON_V6_vmpyiowh: hexagon::V6_vmpyiowh
__builtin_HEXAGON_V6_vmpyiowh_128B: hexagon::V6_vmpyiowh_128B
__builtin_HEXAGON_V6_vmpyiwb: hexagon::V6_vmpyiwb
__builtin_HEXAGON_V6_vmpyiwb_128B: hexagon::V6_vmpyiwb_128B
__builtin_HEXAGON_V6_vmpyiwb_acc: hexagon::V6_vmpyiwb_acc
__builtin_HEXAGON_V6_vmpyiwb_acc_128B: hexagon::V6_vmpyiwb_acc_128B
__builtin_HEXAGON_V6_vmpyiwh: hexagon::V6_vmpyiwh
__builtin_HEXAGON_V6_vmpyiwh_128B: hexagon::V6_vmpyiwh_128B
__builtin_HEXAGON_V6_vmpyiwh_acc: hexagon::V6_vmpyiwh_acc
__builtin_HEXAGON_V6_vmpyiwh_acc_128B: hexagon::V6_vmpyiwh_acc_128B
__builtin_HEXAGON_V6_vmpyowh: hexagon::V6_vmpyowh
__builtin_HEXAGON_V6_vmpyowh_128B: hexagon::V6_vmpyowh_128B
__builtin_HEXAGON_V6_vmpyowh_rnd: hexagon::V6_vmpyowh_rnd
__builtin_HEXAGON_V6_vmpyowh_rnd_128B: hexagon::V6_vmpyowh_rnd_128B
__builtin_HEXAGON_V6_vmpyowh_rnd_sacc: hexagon::V6_vmpyowh_rnd_sacc
__builtin_HEXAGON_V6_vmpyowh_rnd_sacc_128B: hexagon::V6_vmpyowh_rnd_sacc_128B
__builtin_HEXAGON_V6_vmpyowh_sacc: hexagon::V6_vmpyowh_sacc
__builtin_HEXAGON_V6_vmpyowh_sacc_128B: hexagon::V6_vmpyowh_sacc_128B
__builtin_HEXAGON_V6_vmpyub: hexagon::V6_vmpyub
__builtin_HEXAGON_V6_vmpyub_128B: hexagon::V6_vmpyub_128B
__builtin_HEXAGON_V6_vmpyub_acc: hexagon::V6_vmpyub_acc
__builtin_HEXAGON_V6_vmpyub_acc_128B: hexagon::V6_vmpyub_acc_128B
__builtin_HEXAGON_V6_vmpyubv: hexagon::V6_vmpyubv
__builtin_HEXAGON_V6_vmpyubv_128B: hexagon::V6_vmpyubv_128B
__builtin_HEXAGON_V6_vmpyubv_acc: hexagon::V6_vmpyubv_acc
__builtin_HEXAGON_V6_vmpyubv_acc_128B: hexagon::V6_vmpyubv_acc_128B
__builtin_HEXAGON_V6_vmpyuh: hexagon::V6_vmpyuh
__builtin_HEXAGON_V6_vmpyuh_128B: hexagon::V6_vmpyuh_128B
__builtin_HEXAGON_V6_vmpyuh_acc: hexagon::V6_vmpyuh_acc
__builtin_HEXAGON_V6_vmpyuh_acc_128B: hexagon::V6_vmpyuh_acc_128B
__builtin_HEXAGON_V6_vmpyuhv: hexagon::V6_vmpyuhv
__builtin_HEXAGON_V6_vmpyuhv_128B: hexagon::V6_vmpyuhv_128B
__builtin_HEXAGON_V6_vmpyuhv_acc: hexagon::V6_vmpyuhv_acc
__builtin_HEXAGON_V6_vmpyuhv_acc_128B: hexagon::V6_vmpyuhv_acc_128B
__builtin_HEXAGON_V6_vnavgh: hexagon::V6_vnavgh
__builtin_HEXAGON_V6_vnavgh_128B: hexagon::V6_vnavgh_128B
__builtin_HEXAGON_V6_vnavgub: hexagon::V6_vnavgub
__builtin_HEXAGON_V6_vnavgub_128B: hexagon::V6_vnavgub_128B
__builtin_HEXAGON_V6_vnavgw: hexagon::V6_vnavgw
__builtin_HEXAGON_V6_vnavgw_128B: hexagon::V6_vnavgw_128B
__builtin_HEXAGON_V6_vnormamth: hexagon::V6_vnormamth
__builtin_HEXAGON_V6_vnormamth_128B: hexagon::V6_vnormamth_128B
__builtin_HEXAGON_V6_vnormamtw: hexagon::V6_vnormamtw
__builtin_HEXAGON_V6_vnormamtw_128B: hexagon::V6_vnormamtw_128B
__builtin_HEXAGON_V6_vnot: hexagon::V6_vnot
__builtin_HEXAGON_V6_vnot_128B: hexagon::V6_vnot_128B
__builtin_HEXAGON_V6_vor: hexagon::V6_vor
__builtin_HEXAGON_V6_vor_128B: hexagon::V6_vor_128B
__builtin_HEXAGON_V6_vpackeb: hexagon::V6_vpackeb
__builtin_HEXAGON_V6_vpackeb_128B: hexagon::V6_vpackeb_128B
__builtin_HEXAGON_V6_vpackeh: hexagon::V6_vpackeh
__builtin_HEXAGON_V6_vpackeh_128B: hexagon::V6_vpackeh_128B
__builtin_HEXAGON_V6_vpackhb_sat: hexagon::V6_vpackhb_sat
__builtin_HEXAGON_V6_vpackhb_sat_128B: hexagon::V6_vpackhb_sat_128B
__builtin_HEXAGON_V6_vpackhub_sat: hexagon::V6_vpackhub_sat
__builtin_HEXAGON_V6_vpackhub_sat_128B: hexagon::V6_vpackhub_sat_128B
__builtin_HEXAGON_V6_vpackob: hexagon::V6_vpackob
__builtin_HEXAGON_V6_vpackob_128B: hexagon::V6_vpackob_128B
__builtin_HEXAGON_V6_vpackoh: hexagon::V6_vpackoh
__builtin_HEXAGON_V6_vpackoh_128B: hexagon::V6_vpackoh_128B
__builtin_HEXAGON_V6_vpackwh_sat: hexagon::V6_vpackwh_sat
__builtin_HEXAGON_V6_vpackwh_sat_128B: hexagon::V6_vpackwh_sat_128B
__builtin_HEXAGON_V6_vpackwuh_sat: hexagon::V6_vpackwuh_sat
__builtin_HEXAGON_V6_vpackwuh_sat_128B: hexagon::V6_vpackwuh_sat_128B
__builtin_HEXAGON_V6_vpopcounth: hexagon::V6_vpopcounth
__builtin_HEXAGON_V6_vpopcounth_128B: hexagon::V6_vpopcounth_128B
__builtin_HEXAGON_V6_vrdelta: hexagon::V6_vrdelta
__builtin_HEXAGON_V6_vrdelta_128B: hexagon::V6_vrdelta_128B
__builtin_HEXAGON_V6_vrmpybus: hexagon::V6_vrmpybus
__builtin_HEXAGON_V6_vrmpybus_128B: hexagon::V6_vrmpybus_128B
__builtin_HEXAGON_V6_vrmpybus_acc: hexagon::V6_vrmpybus_acc
__builtin_HEXAGON_V6_vrmpybus_acc_128B: hexagon::V6_vrmpybus_acc_128B
__builtin_HEXAGON_V6_vrmpybusi: hexagon::V6_vrmpybusi
__builtin_HEXAGON_V6_vrmpybusi_128B: hexagon::V6_vrmpybusi_128B
__builtin_HEXAGON_V6_vrmpybusi_acc: hexagon::V6_vrmpybusi_acc
__builtin_HEXAGON_V6_vrmpybusi_acc_128B: hexagon::V6_vrmpybusi_acc_128B
__builtin_HEXAGON_V6_vrmpybusv: hexagon::V6_vrmpybusv
__builtin_HEXAGON_V6_vrmpybusv_128B: hexagon::V6_vrmpybusv_128B
__builtin_HEXAGON_V6_vrmpybusv_acc: hexagon::V6_vrmpybusv_acc
__builtin_HEXAGON_V6_vrmpybusv_acc_128B: hexagon::V6_vrmpybusv_acc_128B
__builtin_HEXAGON_V6_vrmpybv: hexagon::V6_vrmpybv
__builtin_HEXAGON_V6_vrmpybv_128B: hexagon::V6_vrmpybv_128B
__builtin_HEXAGON_V6_vrmpybv_acc: hexagon::V6_vrmpybv_acc
__builtin_HEXAGON_V6_vrmpybv_acc_128B: hexagon::V6_vrmpybv_acc_128B
__builtin_HEXAGON_V6_vrmpyub: hexagon::V6_vrmpyub
__builtin_HEXAGON_V6_vrmpyub_128B: hexagon::V6_vrmpyub_128B
__builtin_HEXAGON_V6_vrmpyub_acc: hexagon::V6_vrmpyub_acc
__builtin_HEXAGON_V6_vrmpyub_acc_128B: hexagon::V6_vrmpyub_acc_128B
__builtin_HEXAGON_V6_vrmpyubi: hexagon::V6_vrmpyubi
__builtin_HEXAGON_V6_vrmpyubi_128B: hexagon::V6_vrmpyubi_128B
__builtin_HEXAGON_V6_vrmpyubi_acc: hexagon::V6_vrmpyubi_acc
__builtin_HEXAGON_V6_vrmpyubi_acc_128B: hexagon::V6_vrmpyubi_acc_128B
__builtin_HEXAGON_V6_vrmpyubv: hexagon::V6_vrmpyubv
__builtin_HEXAGON_V6_vrmpyubv_128B: hexagon::V6_vrmpyubv_128B
__builtin_HEXAGON_V6_vrmpyubv_acc: hexagon::V6_vrmpyubv_acc
__builtin_HEXAGON_V6_vrmpyubv_acc_128B: hexagon::V6_vrmpyubv_acc_128B
__builtin_HEXAGON_V6_vror: hexagon::V6_vror
__builtin_HEXAGON_V6_vror_128B: hexagon::V6_vror_128B
__builtin_HEXAGON_V6_vroundhb: hexagon::V6_vroundhb
__builtin_HEXAGON_V6_vroundhb_128B: hexagon::V6_vroundhb_128B
__builtin_HEXAGON_V6_vroundhub: hexagon::V6_vroundhub
__builtin_HEXAGON_V6_vroundhub_128B: hexagon::V6_vroundhub_128B
__builtin_HEXAGON_V6_vroundwh: hexagon::V6_vroundwh
__builtin_HEXAGON_V6_vroundwh_128B: hexagon::V6_vroundwh_128B
__builtin_HEXAGON_V6_vroundwuh: hexagon::V6_vroundwuh
__builtin_HEXAGON_V6_vroundwuh_128B: hexagon::V6_vroundwuh_128B
__builtin_HEXAGON_V6_vrsadubi: hexagon::V6_vrsadubi
__builtin_HEXAGON_V6_vrsadubi_128B: hexagon::V6_vrsadubi_128B
__builtin_HEXAGON_V6_vrsadubi_acc: hexagon::V6_vrsadubi_acc
__builtin_HEXAGON_V6_vrsadubi_acc_128B: hexagon::V6_vrsadubi_acc_128B
__builtin_HEXAGON_V6_vsathub: hexagon::V6_vsathub
__builtin_HEXAGON_V6_vsathub_128B: hexagon::V6_vsathub_128B
__builtin_HEXAGON_V6_vsatwh: hexagon::V6_vsatwh
__builtin_HEXAGON_V6_vsatwh_128B: hexagon::V6_vsatwh_128B
__builtin_HEXAGON_V6_vsb: hexagon::V6_vsb
__builtin_HEXAGON_V6_vsb_128B: hexagon::V6_vsb_128B
__builtin_HEXAGON_V6_vsh: hexagon::V6_vsh
__builtin_HEXAGON_V6_vsh_128B: hexagon::V6_vsh_128B
__builtin_HEXAGON_V6_vshufeh: hexagon::V6_vshufeh
__builtin_HEXAGON_V6_vshufeh_128B: hexagon::V6_vshufeh_128B
__builtin_HEXAGON_V6_vshuffb: hexagon::V6_vshuffb
__builtin_HEXAGON_V6_vshuffb_128B: hexagon::V6_vshuffb_128B
__builtin_HEXAGON_V6_vshuffeb: hexagon::V6_vshuffeb
__builtin_HEXAGON_V6_vshuffeb_128B: hexagon::V6_vshuffeb_128B
__builtin_HEXAGON_V6_vshuffh: hexagon::V6_vshuffh
__builtin_HEXAGON_V6_vshuffh_128B: hexagon::V6_vshuffh_128B
__builtin_HEXAGON_V6_vshuffob: hexagon::V6_vshuffob
__builtin_HEXAGON_V6_vshuffob_128B: hexagon::V6_vshuffob_128B
__builtin_HEXAGON_V6_vshuffvdd: hexagon::V6_vshuffvdd
__builtin_HEXAGON_V6_vshuffvdd_128B: hexagon::V6_vshuffvdd_128B
__builtin_HEXAGON_V6_vshufoeb: hexagon::V6_vshufoeb
__builtin_HEXAGON_V6_vshufoeb_128B: hexagon::V6_vshufoeb_128B
__builtin_HEXAGON_V6_vshufoeh: hexagon::V6_vshufoeh
__builtin_HEXAGON_V6_vshufoeh_128B: hexagon::V6_vshufoeh_128B
__builtin_HEXAGON_V6_vshufoh: hexagon::V6_vshufoh
__builtin_HEXAGON_V6_vshufoh_128B: hexagon::V6_vshufoh_128B
__builtin_HEXAGON_V6_vsubb: hexagon::V6_vsubb
__builtin_HEXAGON_V6_vsubb_128B: hexagon::V6_vsubb_128B
__builtin_HEXAGON_V6_vsubb_dv: hexagon::V6_vsubb_dv
__builtin_HEXAGON_V6_vsubb_dv_128B: hexagon::V6_vsubb_dv_128B
__builtin_HEXAGON_V6_vsubh: hexagon::V6_vsubh
__builtin_HEXAGON_V6_vsubh_128B: hexagon::V6_vsubh_128B
__builtin_HEXAGON_V6_vsubh_dv: hexagon::V6_vsubh_dv
__builtin_HEXAGON_V6_vsubh_dv_128B: hexagon::V6_vsubh_dv_128B
__builtin_HEXAGON_V6_vsubhsat: hexagon::V6_vsubhsat
__builtin_HEXAGON_V6_vsubhsat_128B: hexagon::V6_vsubhsat_128B
__builtin_HEXAGON_V6_vsubhsat_dv: hexagon::V6_vsubhsat_dv
__builtin_HEXAGON_V6_vsubhsat_dv_128B: hexagon::V6_vsubhsat_dv_128B
__builtin_HEXAGON_V6_vsubhw: hexagon::V6_vsubhw
__builtin_HEXAGON_V6_vsubhw_128B: hexagon::V6_vsubhw_128B
__builtin_HEXAGON_V6_vsububh: hexagon::V6_vsububh
__builtin_HEXAGON_V6_vsububh_128B: hexagon::V6_vsububh_128B
__builtin_HEXAGON_V6_vsububsat: hexagon::V6_vsububsat
__builtin_HEXAGON_V6_vsububsat_128B: hexagon::V6_vsububsat_128B
__builtin_HEXAGON_V6_vsububsat_dv: hexagon::V6_vsububsat_dv
__builtin_HEXAGON_V6_vsububsat_dv_128B: hexagon::V6_vsububsat_dv_128B
__builtin_HEXAGON_V6_vsubuhsat: hexagon::V6_vsubuhsat
__builtin_HEXAGON_V6_vsubuhsat_128B: hexagon::V6_vsubuhsat_128B
__builtin_HEXAGON_V6_vsubuhsat_dv: hexagon::V6_vsubuhsat_dv
__builtin_HEXAGON_V6_vsubuhsat_dv_128B: hexagon::V6_vsubuhsat_dv_128B
__builtin_HEXAGON_V6_vsubuhw: hexagon::V6_vsubuhw
__builtin_HEXAGON_V6_vsubuhw_128B: hexagon::V6_vsubuhw_128B
__builtin_HEXAGON_V6_vsubw: hexagon::V6_vsubw
__builtin_HEXAGON_V6_vsubw_128B: hexagon::V6_vsubw_128B
__builtin_HEXAGON_V6_vsubw_dv: hexagon::V6_vsubw_dv
__builtin_HEXAGON_V6_vsubw_dv_128B: hexagon::V6_vsubw_dv_128B
__builtin_HEXAGON_V6_vsubwsat: hexagon::V6_vsubwsat
__builtin_HEXAGON_V6_vsubwsat_128B: hexagon::V6_vsubwsat_128B
__builtin_HEXAGON_V6_vsubwsat_dv: hexagon::V6_vsubwsat_dv
__builtin_HEXAGON_V6_vsubwsat_dv_128B: hexagon::V6_vsubwsat_dv_128B
__builtin_HEXAGON_V6_vtmpyb: hexagon::V6_vtmpyb
__builtin_HEXAGON_V6_vtmpyb_128B: hexagon::V6_vtmpyb_128B
__builtin_HEXAGON_V6_vtmpyb_acc: hexagon::V6_vtmpyb_acc
__builtin_HEXAGON_V6_vtmpyb_acc_128B: hexagon::V6_vtmpyb_acc_128B
__builtin_HEXAGON_V6_vtmpybus: hexagon::V6_vtmpybus
__builtin_HEXAGON_V6_vtmpybus_128B: hexagon::V6_vtmpybus_128B
__builtin_HEXAGON_V6_vtmpybus_acc: hexagon::V6_vtmpybus_acc
__builtin_HEXAGON_V6_vtmpybus_acc_128B: hexagon::V6_vtmpybus_acc_128B
__builtin_HEXAGON_V6_vtmpyhb: hexagon::V6_vtmpyhb
__builtin_HEXAGON_V6_vtmpyhb_128B: hexagon::V6_vtmpyhb_128B
__builtin_HEXAGON_V6_vtmpyhb_acc: hexagon::V6_vtmpyhb_acc
__builtin_HEXAGON_V6_vtmpyhb_acc_128B: hexagon::V6_vtmpyhb_acc_128B
__builtin_HEXAGON_V6_vunpackb: hexagon::V6_vunpackb
__builtin_HEXAGON_V6_vunpackb_128B: hexagon::V6_vunpackb_128B
__builtin_HEXAGON_V6_vunpackh: hexagon::V6_vunpackh
__builtin_HEXAGON_V6_vunpackh_128B: hexagon::V6_vunpackh_128B
__builtin_HEXAGON_V6_vunpackob: hexagon::V6_vunpackob
__builtin_HEXAGON_V6_vunpackob_128B: hexagon::V6_vunpackob_128B
__builtin_HEXAGON_V6_vunpackoh: hexagon::V6_vunpackoh
__builtin_HEXAGON_V6_vunpackoh_128B: hexagon::V6_vunpackoh_128B
__builtin_HEXAGON_V6_vunpackub: hexagon::V6_vunpackub
__builtin_HEXAGON_V6_vunpackub_128B: hexagon::V6_vunpackub_128B
__builtin_HEXAGON_V6_vunpackuh: hexagon::V6_vunpackuh
__builtin_HEXAGON_V6_vunpackuh_128B: hexagon::V6_vunpackuh_128B
__builtin_HEXAGON_V6_vxor: hexagon::V6_vxor
__builtin_HEXAGON_V6_vxor_128B: hexagon::V6_vxor_128B
__builtin_HEXAGON_V6_vzb: hexagon::V6_vzb
__builtin_HEXAGON_V6_vzb_128B: hexagon::V6_vzb_128B
__builtin_HEXAGON_V6_vzh: hexagon::V6_vzh
__builtin_HEXAGON_V6_vzh_128B: hexagon::V6_vzh_128B
__builtin_HEXAGON_prefetch: hexagon::prefetch
__builtin_SI_to_SXTHI_asrh: hexagon::SI_to_SXTHI_asrh
__builtin__mm256i_vaddw: hexagon::mm256i_vaddw
__builtin_adjust_trampoline: adjust_trampoline
__builtin_altivec_crypto_vcipher: ppc::altivec_crypto_vcipher
__builtin_altivec_crypto_vcipherlast: ppc::altivec_crypto_vcipherlast
__builtin_altivec_crypto_vncipher: ppc::altivec_crypto_vncipher
__builtin_altivec_crypto_vncipherlast: ppc::altivec_crypto_vncipherlast
__builtin_altivec_crypto_vpermxor: ppc::altivec_crypto_vpermxor
__builtin_altivec_crypto_vpmsumb: ppc::altivec_crypto_vpmsumb
__builtin_altivec_crypto_vpmsumd: ppc::altivec_crypto_vpmsumd
__builtin_altivec_crypto_vpmsumh: ppc::altivec_crypto_vpmsumh
__builtin_altivec_crypto_vpmsumw: ppc::altivec_crypto_vpmsumw
__builtin_altivec_crypto_vsbox: ppc::altivec_crypto_vsbox
__builtin_altivec_crypto_vshasigmad: ppc::altivec_crypto_vshasigmad
__builtin_altivec_crypto_vshasigmaw: ppc::altivec_crypto_vshasigmaw
__builtin_altivec_dss: ppc::altivec_dss
__builtin_altivec_dssall: ppc::altivec_dssall
__builtin_altivec_dst: ppc::altivec_dst
__builtin_altivec_dstst: ppc::altivec_dstst
__builtin_altivec_dststt: ppc::altivec_dststt
__builtin_altivec_dstt: ppc::altivec_dstt
__builtin_altivec_mfvscr: ppc::altivec_mfvscr
__builtin_altivec_mtvscr: ppc::altivec_mtvscr
__builtin_altivec_vaddcuw: ppc::altivec_vaddcuw
__builtin_altivec_vaddsbs: ppc::altivec_vaddsbs
__builtin_altivec_vaddshs: ppc::altivec_vaddshs
__builtin_altivec_vaddsws: ppc::altivec_vaddsws
__builtin_altivec_vaddubs: ppc::altivec_vaddubs
__builtin_altivec_vadduhs: ppc::altivec_vadduhs
__builtin_altivec_vadduws: ppc::altivec_vadduws
__builtin_altivec_vavgsb: ppc::altivec_vavgsb
__builtin_altivec_vavgsh: ppc::altivec_vavgsh
__builtin_altivec_vavgsw: ppc::altivec_vavgsw
__builtin_altivec_vavgub: ppc::altivec_vavgub
__builtin_altivec_vavguh: ppc::altivec_vavguh
__builtin_altivec_vavguw: ppc::altivec_vavguw
__builtin_altivec_vbpermq: ppc::altivec_vbpermq
__builtin_altivec_vcfsx: ppc::altivec_vcfsx
__builtin_altivec_vcfux: ppc::altivec_vcfux
__builtin_altivec_vcmpbfp: ppc::altivec_vcmpbfp
__builtin_altivec_vcmpbfp_p: ppc::altivec_vcmpbfp_p
__builtin_altivec_vcmpeqfp: ppc::altivec_vcmpeqfp
__builtin_altivec_vcmpeqfp_p: ppc::altivec_vcmpeqfp_p
__builtin_altivec_vcmpequb: ppc::altivec_vcmpequb
__builtin_altivec_vcmpequb_p: ppc::altivec_vcmpequb_p
__builtin_altivec_vcmpequd: ppc::altivec_vcmpequd
__builtin_altivec_vcmpequd_p: ppc::altivec_vcmpequd_p
__builtin_altivec_vcmpequh: ppc::altivec_vcmpequh
__builtin_altivec_vcmpequh_p: ppc::altivec_vcmpequh_p
__builtin_altivec_vcmpequw: ppc::altivec_vcmpequw
__builtin_altivec_vcmpequw_p: ppc::altivec_vcmpequw_p
__builtin_altivec_vcmpgefp: ppc::altivec_vcmpgefp
__builtin_altivec_vcmpgefp_p: ppc::altivec_vcmpgefp_p
__builtin_altivec_vcmpgtfp: ppc::altivec_vcmpgtfp
__builtin_altivec_vcmpgtfp_p: ppc::altivec_vcmpgtfp_p
__builtin_altivec_vcmpgtsb: ppc::altivec_vcmpgtsb
__builtin_altivec_vcmpgtsb_p: ppc::altivec_vcmpgtsb_p
__builtin_altivec_vcmpgtsd: ppc::altivec_vcmpgtsd
__builtin_altivec_vcmpgtsd_p: ppc::altivec_vcmpgtsd_p
__builtin_altivec_vcmpgtsh: ppc::altivec_vcmpgtsh
__builtin_altivec_vcmpgtsh_p: ppc::altivec_vcmpgtsh_p
__builtin_altivec_vcmpgtsw: ppc::altivec_vcmpgtsw
__builtin_altivec_vcmpgtsw_p: ppc::altivec_vcmpgtsw_p
__builtin_altivec_vcmpgtub: ppc::altivec_vcmpgtub
__builtin_altivec_vcmpgtub_p: ppc::altivec_vcmpgtub_p
__builtin_altivec_vcmpgtud: ppc::altivec_vcmpgtud
__builtin_altivec_vcmpgtud_p: ppc::altivec_vcmpgtud_p
__builtin_altivec_vcmpgtuh: ppc::altivec_vcmpgtuh
__builtin_altivec_vcmpgtuh_p: ppc::altivec_vcmpgtuh_p
__builtin_altivec_vcmpgtuw: ppc::altivec_vcmpgtuw
__builtin_altivec_vcmpgtuw_p: ppc::altivec_vcmpgtuw_p
__builtin_altivec_vctsxs: ppc::altivec_vctsxs
__builtin_altivec_vctuxs: ppc::altivec_vctuxs
__builtin_altivec_vexptefp: ppc::altivec_vexptefp
__builtin_altivec_vgbbd: ppc::altivec_vgbbd
__builtin_altivec_vlogefp: ppc::altivec_vlogefp
__builtin_altivec_vmaddfp: ppc::altivec_vmaddfp
__builtin_altivec_vmaxfp: ppc::altivec_vmaxfp
__builtin_altivec_vmaxsb: ppc::altivec_vmaxsb
__builtin_altivec_vmaxsd: ppc::altivec_vmaxsd
__builtin_altivec_vmaxsh: ppc::altivec_vmaxsh
__builtin_altivec_vmaxsw: ppc::altivec_vmaxsw
__builtin_altivec_vmaxub: ppc::altivec_vmaxub
__builtin_altivec_vmaxud: ppc::altivec_vmaxud
__builtin_altivec_vmaxuh: ppc::altivec_vmaxuh
__builtin_altivec_vmaxuw: ppc::altivec_vmaxuw
__builtin_altivec_vmhaddshs: ppc::altivec_vmhaddshs
__builtin_altivec_vmhraddshs: ppc::altivec_vmhraddshs
__builtin_altivec_vminfp: ppc::altivec_vminfp
__builtin_altivec_vminsb: ppc::altivec_vminsb
__builtin_altivec_vminsd: ppc::altivec_vminsd
__builtin_altivec_vminsh: ppc::altivec_vminsh
__builtin_altivec_vminsw: ppc::altivec_vminsw
__builtin_altivec_vminub: ppc::altivec_vminub
__builtin_altivec_vminud: ppc::altivec_vminud
__builtin_altivec_vminuh: ppc::altivec_vminuh
__builtin_altivec_vminuw: ppc::altivec_vminuw
__builtin_altivec_vmladduhm: ppc::altivec_vmladduhm
__builtin_altivec_vmsummbm: ppc::altivec_vmsummbm
__builtin_altivec_vmsumshm: ppc::altivec_vmsumshm
__builtin_altivec_vmsumshs: ppc::altivec_vmsumshs
__builtin_altivec_vmsumubm: ppc::altivec_vmsumubm
__builtin_altivec_vmsumuhm: ppc::altivec_vmsumuhm
__builtin_altivec_vmsumuhs: ppc::altivec_vmsumuhs
__builtin_altivec_vmulesb: ppc::altivec_vmulesb
__builtin_altivec_vmulesh: ppc::altivec_vmulesh
__builtin_altivec_vmulesw: ppc::altivec_vmulesw
__builtin_altivec_vmuleub: ppc::altivec_vmuleub
__builtin_altivec_vmuleuh: ppc::altivec_vmuleuh
__builtin_altivec_vmuleuw: ppc::altivec_vmuleuw
__builtin_altivec_vmulosb: ppc::altivec_vmulosb
__builtin_altivec_vmulosh: ppc::altivec_vmulosh
__builtin_altivec_vmulosw: ppc::altivec_vmulosw
__builtin_altivec_vmuloub: ppc::altivec_vmuloub
__builtin_altivec_vmulouh: ppc::altivec_vmulouh
__builtin_altivec_vmulouw: ppc::altivec_vmulouw
__builtin_altivec_vnmsubfp: ppc::altivec_vnmsubfp
__builtin_altivec_vperm_4si: ppc::altivec_vperm
__builtin_altivec_vpkpx: ppc::altivec_vpkpx
__builtin_altivec_vpksdss: ppc::altivec_vpksdss
__builtin_altivec_vpksdus: ppc::altivec_vpksdus
__builtin_altivec_vpkshss: ppc::altivec_vpkshss
__builtin_altivec_vpkshus: ppc::altivec_vpkshus
__builtin_altivec_vpkswss: ppc::altivec_vpkswss
__builtin_altivec_vpkswus: ppc::altivec_vpkswus
__builtin_altivec_vpkudus: ppc::altivec_vpkudus
__builtin_altivec_vpkuhus: ppc::altivec_vpkuhus
__builtin_altivec_vpkuwus: ppc::altivec_vpkuwus
__builtin_altivec_vrefp: ppc::altivec_vrefp
__builtin_altivec_vrfim: ppc::altivec_vrfim
__builtin_altivec_vrfin: ppc::altivec_vrfin
__builtin_altivec_vrfip: ppc::altivec_vrfip
__builtin_altivec_vrfiz: ppc::altivec_vrfiz
__builtin_altivec_vrlb: ppc::altivec_vrlb
__builtin_altivec_vrld: ppc::altivec_vrld
__builtin_altivec_vrlh: ppc::altivec_vrlh
__builtin_altivec_vrlw: ppc::altivec_vrlw
__builtin_altivec_vrsqrtefp: ppc::altivec_vrsqrtefp
__builtin_altivec_vsel_4si: ppc::altivec_vsel
__builtin_altivec_vsl: ppc::altivec_vsl
__builtin_altivec_vslb: ppc::altivec_vslb
__builtin_altivec_vslh: ppc::altivec_vslh
__builtin_altivec_vslo: ppc::altivec_vslo
__builtin_altivec_vslw: ppc::altivec_vslw
__builtin_altivec_vsr: ppc::altivec_vsr
__builtin_altivec_vsrab: ppc::altivec_vsrab
__builtin_altivec_vsrah: ppc::altivec_vsrah
__builtin_altivec_vsraw: ppc::altivec_vsraw
__builtin_altivec_vsrb: ppc::altivec_vsrb
__builtin_altivec_vsrh: ppc::altivec_vsrh
__builtin_altivec_vsro: ppc::altivec_vsro
__builtin_altivec_vsrw: ppc::altivec_vsrw
__builtin_altivec_vsubcuw: ppc::altivec_vsubcuw
__builtin_altivec_vsubsbs: ppc::altivec_vsubsbs
__builtin_altivec_vsubshs: ppc::altivec_vsubshs
__builtin_altivec_vsubsws: ppc::altivec_vsubsws
__builtin_altivec_vsububs: ppc::altivec_vsububs
__builtin_altivec_vsubuhs: ppc::altivec_vsubuhs
__builtin_altivec_vsubuws: ppc::altivec_vsubuws
__builtin_altivec_vsum2sws: ppc::altivec_vsum2sws
__builtin_altivec_vsum4sbs: ppc::altivec_vsum4sbs
__builtin_altivec_vsum4shs: ppc::altivec_vsum4shs
__builtin_altivec_vsum4ubs: ppc::altivec_vsum4ubs
__builtin_altivec_vsumsws: ppc::altivec_vsumsws
__builtin_altivec_vupkhpx: ppc::altivec_vupkhpx
__builtin_altivec_vupkhsb: ppc::altivec_vupkhsb
__builtin_altivec_vupkhsh: ppc::altivec_vupkhsh
__builtin_altivec_vupkhsw: ppc::altivec_vupkhsw
__builtin_altivec_vupklpx: ppc::altivec_vupklpx
__builtin_altivec_vupklsb: ppc::altivec_vupklsb
__builtin_altivec_vupklsh: ppc::altivec_vupklsh
__builtin_altivec_vupklsw: ppc::altivec_vupklsw
__builtin_amdgcn_buffer_wbinvl1: amdgcn_buffer_wbinvl1
__builtin_amdgcn_buffer_wbinvl1_sc: amdgcn_buffer_wbinvl1_sc
__builtin_amdgcn_buffer_wbinvl1_vol: amdgcn_buffer_wbinvl1_vol
__builtin_amdgcn_cubeid: amdgcn_cubeid
__builtin_amdgcn_cubema: amdgcn_cubema
__builtin_amdgcn_cubesc: amdgcn_cubesc
__builtin_amdgcn_cubetc: amdgcn_cubetc
__builtin_amdgcn_ds_swizzle: amdgcn_ds_swizzle
__builtin_amdgcn_groupstaticsize: amdgcn_groupstaticsize
__builtin_amdgcn_interp_p1: amdgcn_interp_p1
__builtin_amdgcn_interp_p2: amdgcn_interp_p2
__builtin_amdgcn_lerp: amdgcn_lerp
__builtin_amdgcn_mbcnt_hi: amdgcn_mbcnt_hi
__builtin_amdgcn_mbcnt_lo: amdgcn_mbcnt_lo
__builtin_amdgcn_rsq_legacy: amdgcn_rsq_legacy
__builtin_amdgcn_s_barrier: amdgcn_s_barrier
__builtin_amdgcn_s_dcache_inv: amdgcn_s_dcache_inv
__builtin_amdgcn_s_dcache_inv_vol: amdgcn_s_dcache_inv_vol
__builtin_amdgcn_s_dcache_wb: amdgcn_s_dcache_wb
__builtin_amdgcn_s_dcache_wb_vol: amdgcn_s_dcache_wb_vol
__builtin_amdgcn_s_getreg: amdgcn_s_getreg
__builtin_amdgcn_s_memrealtime: amdgcn_s_memrealtime
__builtin_amdgcn_s_memtime: amdgcn_s_memtime
__builtin_amdgcn_s_sleep: amdgcn_s_sleep
__builtin_arm_cdp: arm::cdp
__builtin_arm_cdp2: arm::cdp2
__builtin_arm_dmb: aarch64::dmb; arm::dmb
__builtin_arm_dsb: aarch64::dsb; arm::dsb
__builtin_arm_get_fpscr: arm::get_fpscr
__builtin_arm_isb: aarch64::isb; arm::isb
__builtin_arm_ldc: arm::ldc
__builtin_arm_ldc2: arm::ldc2
__builtin_arm_ldc2l: arm::ldc2l
__builtin_arm_ldcl: arm::ldcl
__builtin_arm_mcr: arm::mcr
__builtin_arm_mcr2: arm::mcr2
__builtin_arm_mrc: arm::mrc
__builtin_arm_mrc2: arm::mrc2
__builtin_arm_qadd: arm::qadd
__builtin_arm_qsub: arm::qsub
__builtin_arm_set_fpscr: arm::set_fpscr
__builtin_arm_ssat: arm::ssat
__builtin_arm_stc: arm::stc
__builtin_arm_stc2: arm::stc2
__builtin_arm_stc2l: arm::stc2l
__builtin_arm_stcl: arm::stcl
__builtin_arm_usat: arm::usat
__builtin_bitrev: xcore::bitrev
__builtin_bpermd: ppc::bpermd
__builtin_bpf_load_byte: bpf_load_byte
__builtin_bpf_load_half: bpf_load_half
__builtin_bpf_load_word: bpf_load_word
__builtin_bpf_pseudo: bpf_pseudo
__builtin_brev_ldb: hexagon::brev_ldb
__builtin_brev_ldd: hexagon::brev_ldd
__builtin_brev_ldh: hexagon::brev_ldh
__builtin_brev_ldub: hexagon::brev_ldub
__builtin_brev_lduh: hexagon::brev_lduh
__builtin_brev_ldw: hexagon::brev_ldw
__builtin_brev_stb: hexagon::brev_stb
__builtin_brev_std: hexagon::brev_std
__builtin_brev_sth: hexagon::brev_sth
__builtin_brev_sthhi: hexagon::brev_sthhi
__builtin_brev_stw: hexagon::brev_stw
__builtin_circ_ldb: hexagon::circ_ldb
__builtin_circ_ldd: hexagon::circ_ldd
__builtin_circ_ldh: hexagon::circ_ldh
__builtin_circ_ldub: hexagon::circ_ldub
__builtin_circ_lduh: hexagon::circ_lduh
__builtin_circ_ldw: hexagon::circ_ldw
__builtin_circ_stb: hexagon::circ_stb
__builtin_circ_std: hexagon::circ_std
__builtin_circ_sth: hexagon::circ_sth
__builtin_circ_sthhi: hexagon::circ_sthhi
__builtin_circ_stw: hexagon::circ_stw
__builtin_debugtrap: debugtrap
__builtin_divde: ppc::divde
__builtin_divdeu: ppc::divdeu
__builtin_divwe: ppc::divwe
__builtin_divweu: ppc::divweu
__builtin_flt_rounds: flt_rounds
__builtin_get_texasr: ppc::get_texasr
__builtin_get_texasru: ppc::get_texasru
__builtin_get_tfhar: ppc::get_tfhar
__builtin_get_tfiar: ppc::get_tfiar
__builtin_getid: xcore::getid
__builtin_getps: xcore::getps
__builtin_ia32_addcarry_u32: x86::addcarry_u32
__builtin_ia32_addcarry_u64: x86::addcarry_u64
__builtin_ia32_addcarryx_u32: x86::addcarryx_u32
__builtin_ia32_addcarryx_u64: x86::addcarryx_u64
__builtin_ia32_addpd128_mask: x86::avx512_mask_add_pd_128
__builtin_ia32_addpd256_mask: x86::avx512_mask_add_pd_256
__builtin_ia32_addpd512_mask: x86::avx512_mask_add_pd_512
__builtin_ia32_addps128_mask: x86::avx512_mask_add_ps_128
__builtin_ia32_addps256_mask: x86::avx512_mask_add_ps_256
__builtin_ia32_addps512_mask: x86::avx512_mask_add_ps_512
__builtin_ia32_addsd_round_mask: x86::avx512_mask_add_sd_round
__builtin_ia32_addss_round_mask: x86::avx512_mask_add_ss_round
__builtin_ia32_addsubpd: x86::sse3_addsub_pd
__builtin_ia32_addsubpd256: x86::avx_addsub_pd_256
__builtin_ia32_addsubps: x86::sse3_addsub_ps
__builtin_ia32_addsubps256: x86::avx_addsub_ps_256
__builtin_ia32_aesdec128: x86::aesni_aesdec
__builtin_ia32_aesdeclast128: x86::aesni_aesdeclast
__builtin_ia32_aesenc128: x86::aesni_aesenc
__builtin_ia32_aesenclast128: x86::aesni_aesenclast
__builtin_ia32_aesimc128: x86::aesni_aesimc
__builtin_ia32_aeskeygenassist128: x86::aesni_aeskeygenassist
__builtin_ia32_alignd128_mask: x86::avx512_mask_valign_d_128
__builtin_ia32_alignd256_mask: x86::avx512_mask_valign_d_256
__builtin_ia32_alignd512_mask: x86::avx512_mask_valign_d_512
__builtin_ia32_alignq128_mask: x86::avx512_mask_valign_q_128
__builtin_ia32_alignq256_mask: x86::avx512_mask_valign_q_256
__builtin_ia32_alignq512_mask: x86::avx512_mask_valign_q_512
__builtin_ia32_andnpd128_mask: x86::avx512_mask_andn_pd_128
__builtin_ia32_andnpd256_mask: x86::avx512_mask_andn_pd_256
__builtin_ia32_andnpd512_mask: x86::avx512_mask_andn_pd_512
__builtin_ia32_andnps128_mask: x86::avx512_mask_andn_ps_128
__builtin_ia32_andnps256_mask: x86::avx512_mask_andn_ps_256
__builtin_ia32_andnps512_mask: x86::avx512_mask_andn_ps_512
__builtin_ia32_andpd128_mask: x86::avx512_mask_and_pd_128
__builtin_ia32_andpd256_mask: x86::avx512_mask_and_pd_256
__builtin_ia32_andpd512_mask: x86::avx512_mask_and_pd_512
__builtin_ia32_andps128_mask: x86::avx512_mask_and_ps_128
__builtin_ia32_andps256_mask: x86::avx512_mask_and_ps_256
__builtin_ia32_andps512_mask: x86::avx512_mask_and_ps_512
__builtin_ia32_bextr_u32: x86::bmi_bextr_32
__builtin_ia32_bextr_u64: x86::bmi_bextr_64
__builtin_ia32_bextri_u32: x86::tbm_bextri_u32
__builtin_ia32_bextri_u64: x86::tbm_bextri_u64
__builtin_ia32_blendvpd: x86::sse41_blendvpd
__builtin_ia32_blendvpd256: x86::avx_blendv_pd_256
__builtin_ia32_blendvps: x86::sse41_blendvps
__builtin_ia32_blendvps256: x86::avx_blendv_ps_256
__builtin_ia32_broadcastf32x2_256_mask: x86::avx512_mask_broadcastf32x2_256
__builtin_ia32_broadcastf32x2_512_mask: x86::avx512_mask_broadcastf32x2_512
__builtin_ia32_broadcastf32x4_256_mask: x86::avx512_mask_broadcastf32x4_256
__builtin_ia32_broadcastf32x4_512: x86::avx512_mask_broadcastf32x4_512
__builtin_ia32_broadcastf32x8_512_mask: x86::avx512_mask_broadcastf32x8_512
__builtin_ia32_broadcastf64x2_256_mask: x86::avx512_mask_broadcastf64x2_256
__builtin_ia32_broadcastf64x2_512_mask: x86::avx512_mask_broadcastf64x2_512
__builtin_ia32_broadcastf64x4_512: x86::avx512_mask_broadcastf64x4_512
__builtin_ia32_broadcasti32x2_128_mask: x86::avx512_mask_broadcasti32x2_128
__builtin_ia32_broadcasti32x2_256_mask: x86::avx512_mask_broadcasti32x2_256
__builtin_ia32_broadcasti32x2_512_mask: x86::avx512_mask_broadcasti32x2_512
__builtin_ia32_broadcasti32x4_256_mask: x86::avx512_mask_broadcasti32x4_256
__builtin_ia32_broadcasti32x4_512: x86::avx512_mask_broadcasti32x4_512
__builtin_ia32_broadcasti32x8_512_mask: x86::avx512_mask_broadcasti32x8_512
__builtin_ia32_broadcasti64x2_256_mask: x86::avx512_mask_broadcasti64x2_256
__builtin_ia32_broadcasti64x2_512_mask: x86::avx512_mask_broadcasti64x2_512
__builtin_ia32_broadcasti64x4_512: x86::avx512_mask_broadcasti64x4_512
__builtin_ia32_broadcastmb128: x86::avx512_broadcastmb_128
__builtin_ia32_broadcastmb256: x86::avx512_broadcastmb_256
__builtin_ia32_broadcastmb512: x86::avx512_broadcastmb_512
__builtin_ia32_broadcastmw128: x86::avx512_broadcastmw_128
__builtin_ia32_broadcastmw256: x86::avx512_broadcastmw_256
__builtin_ia32_broadcastmw512: x86::avx512_broadcastmw_512
__builtin_ia32_bzhi_di: x86::bmi_bzhi_64
__builtin_ia32_bzhi_si: x86::bmi_bzhi_32
__builtin_ia32_clflush: x86::sse2_clflush
__builtin_ia32_clflushopt: x86::clflushopt
__builtin_ia32_cmppd128_mask: x86::avx512_mask_cmp_pd_128
__builtin_ia32_cmppd256_mask: x86::avx512_mask_cmp_pd_256
__builtin_ia32_cmppd512_mask: x86::avx512_mask_cmp_pd_512
__builtin_ia32_cmpps128_mask: x86::avx512_mask_cmp_ps_128
__builtin_ia32_cmpps256_mask: x86::avx512_mask_cmp_ps_256
__builtin_ia32_cmpps512_mask: x86::avx512_mask_cmp_ps_512
__builtin_ia32_cmpsd: x86::sse2_cmp_sd
__builtin_ia32_cmpsd_mask: x86::avx512_mask_cmp_sd
__builtin_ia32_cmpss: x86::sse_cmp_ss
__builtin_ia32_cmpss_mask: x86::avx512_mask_cmp_ss
__builtin_ia32_comieq: x86::sse_comieq_ss
__builtin_ia32_comige: x86::sse_comige_ss
__builtin_ia32_comigt: x86::sse_comigt_ss
__builtin_ia32_comile: x86::sse_comile_ss
__builtin_ia32_comilt: x86::sse_comilt_ss
__builtin_ia32_comineq: x86::sse_comineq_ss
__builtin_ia32_comisdeq: x86::sse2_comieq_sd
__builtin_ia32_comisdge: x86::sse2_comige_sd
__builtin_ia32_comisdgt: x86::sse2_comigt_sd
__builtin_ia32_comisdle: x86::sse2_comile_sd
__builtin_ia32_comisdlt: x86::sse2_comilt_sd
__builtin_ia32_comisdneq: x86::sse2_comineq_sd
__builtin_ia32_compressdf128_mask: x86::avx512_mask_compress_pd_128
__builtin_ia32_compressdf256_mask: x86::avx512_mask_compress_pd_256
__builtin_ia32_compressdf512_mask: x86::avx512_mask_compress_pd_512
__builtin_ia32_compressdi128_mask: x86::avx512_mask_compress_q_128
__builtin_ia32_compressdi256_mask: x86::avx512_mask_compress_q_256
__builtin_ia32_compressdi512_mask: x86::avx512_mask_compress_q_512
__builtin_ia32_compresssf128_mask: x86::avx512_mask_compress_ps_128
__builtin_ia32_compresssf256_mask: x86::avx512_mask_compress_ps_256
__builtin_ia32_compresssf512_mask: x86::avx512_mask_compress_ps_512
__builtin_ia32_compresssi128_mask: x86::avx512_mask_compress_d_128
__builtin_ia32_compresssi256_mask: x86::avx512_mask_compress_d_256
__builtin_ia32_compresssi512_mask: x86::avx512_mask_compress_d_512
__builtin_ia32_compressstoredf128_mask: x86::avx512_mask_compress_store_pd_128
__builtin_ia32_compressstoredf256_mask: x86::avx512_mask_compress_store_pd_256
__builtin_ia32_compressstoredf512_mask: x86::avx512_mask_compress_store_pd_512
__builtin_ia32_compressstoredi128_mask: x86::avx512_mask_compress_store_q_128
__builtin_ia32_compressstoredi256_mask: x86::avx512_mask_compress_store_q_256
__builtin_ia32_compressstoredi512_mask: x86::avx512_mask_compress_store_q_512
__builtin_ia32_compressstoresf128_mask: x86::avx512_mask_compress_store_ps_128
__builtin_ia32_compressstoresf256_mask: x86::avx512_mask_compress_store_ps_256
__builtin_ia32_compressstoresf512_mask: x86::avx512_mask_compress_store_ps_512
__builtin_ia32_compressstoresi128_mask: x86::avx512_mask_compress_store_d_128
__builtin_ia32_compressstoresi256_mask: x86::avx512_mask_compress_store_d_256
__builtin_ia32_compressstoresi512_mask: x86::avx512_mask_compress_store_d_512
__builtin_ia32_crc32di: x86::sse42_crc32_64_64
__builtin_ia32_crc32hi: x86::sse42_crc32_32_16
__builtin_ia32_crc32qi: x86::sse42_crc32_32_8
__builtin_ia32_crc32si: x86::sse42_crc32_32_32
__builtin_ia32_cvtb2mask128: x86::avx512_cvtb2mask_128
__builtin_ia32_cvtb2mask256: x86::avx512_cvtb2mask_256
__builtin_ia32_cvtb2mask512: x86::avx512_cvtb2mask_512
__builtin_ia32_cvtd2mask128: x86::avx512_cvtd2mask_128
__builtin_ia32_cvtd2mask256: x86::avx512_cvtd2mask_256
__builtin_ia32_cvtd2mask512: x86::avx512_cvtd2mask_512
__builtin_ia32_cvtdq2pd128_mask: x86::avx512_mask_cvtdq2pd_128
__builtin_ia32_cvtdq2pd256_mask: x86::avx512_mask_cvtdq2pd_256
__builtin_ia32_cvtdq2pd512_mask: x86::avx512_mask_cvtdq2pd_512
__builtin_ia32_cvtdq2ps: x86::sse2_cvtdq2ps
__builtin_ia32_cvtdq2ps128_mask: x86::avx512_mask_cvtdq2ps_128
__builtin_ia32_cvtdq2ps256: x86::avx_cvtdq2_ps_256
__builtin_ia32_cvtdq2ps256_mask: x86::avx512_mask_cvtdq2ps_256
__builtin_ia32_cvtdq2ps512_mask: x86::avx512_mask_cvtdq2ps_512
__builtin_ia32_cvtmask2b128: x86::avx512_cvtmask2b_128
__builtin_ia32_cvtmask2b256: x86::avx512_cvtmask2b_256
__builtin_ia32_cvtmask2b512: x86::avx512_cvtmask2b_512
__builtin_ia32_cvtmask2d128: x86::avx512_cvtmask2d_128
__builtin_ia32_cvtmask2d256: x86::avx512_cvtmask2d_256
__builtin_ia32_cvtmask2d512: x86::avx512_cvtmask2d_512
__builtin_ia32_cvtmask2q128: x86::avx512_cvtmask2q_128
__builtin_ia32_cvtmask2q256: x86::avx512_cvtmask2q_256
__builtin_ia32_cvtmask2q512: x86::avx512_cvtmask2q_512
__builtin_ia32_cvtmask2w128: x86::avx512_cvtmask2w_128
__builtin_ia32_cvtmask2w256: x86::avx512_cvtmask2w_256
__builtin_ia32_cvtmask2w512: x86::avx512_cvtmask2w_512
__builtin_ia32_cvtpd2dq: x86::sse2_cvtpd2dq
__builtin_ia32_cvtpd2dq128_mask: x86::avx512_mask_cvtpd2dq_128
__builtin_ia32_cvtpd2dq256: x86::avx_cvt_pd2dq_256
__builtin_ia32_cvtpd2dq256_mask: x86::avx512_mask_cvtpd2dq_256
__builtin_ia32_cvtpd2dq512_mask: x86::avx512_mask_cvtpd2dq_512
__builtin_ia32_cvtpd2ps: x86::sse2_cvtpd2ps
__builtin_ia32_cvtpd2ps256: x86::avx_cvt_pd2_ps_256
__builtin_ia32_cvtpd2ps256_mask: x86::avx512_mask_cvtpd2ps_256
__builtin_ia32_cvtpd2ps512_mask: x86::avx512_mask_cvtpd2ps_512
__builtin_ia32_cvtpd2ps_mask: x86::avx512_mask_cvtpd2ps
__builtin_ia32_cvtpd2qq128_mask: x86::avx512_mask_cvtpd2qq_128
__builtin_ia32_cvtpd2qq256_mask: x86::avx512_mask_cvtpd2qq_256
__builtin_ia32_cvtpd2qq512_mask: x86::avx512_mask_cvtpd2qq_512
__builtin_ia32_cvtpd2udq128_mask: x86::avx512_mask_cvtpd2udq_128
__builtin_ia32_cvtpd2udq256_mask: x86::avx512_mask_cvtpd2udq_256
__builtin_ia32_cvtpd2udq512_mask: x86::avx512_mask_cvtpd2udq_512
__builtin_ia32_cvtpd2uqq128_mask: x86::avx512_mask_cvtpd2uqq_128
__builtin_ia32_cvtpd2uqq256_mask: x86::avx512_mask_cvtpd2uqq_256
__builtin_ia32_cvtpd2uqq512_mask: x86::avx512_mask_cvtpd2uqq_512
__builtin_ia32_cvtps2dq: x86::sse2_cvtps2dq
__builtin_ia32_cvtps2dq128_mask: x86::avx512_mask_cvtps2dq_128
__builtin_ia32_cvtps2dq256: x86::avx_cvt_ps2dq_256
__builtin_ia32_cvtps2dq256_mask: x86::avx512_mask_cvtps2dq_256
__builtin_ia32_cvtps2dq512_mask: x86::avx512_mask_cvtps2dq_512
__builtin_ia32_cvtps2pd128_mask: x86::avx512_mask_cvtps2pd_128
__builtin_ia32_cvtps2pd256_mask: x86::avx512_mask_cvtps2pd_256
__builtin_ia32_cvtps2pd512_mask: x86::avx512_mask_cvtps2pd_512
__builtin_ia32_cvtps2qq128_mask: x86::avx512_mask_cvtps2qq_128
__builtin_ia32_cvtps2qq256_mask: x86::avx512_mask_cvtps2qq_256
__builtin_ia32_cvtps2qq512_mask: x86::avx512_mask_cvtps2qq_512
__builtin_ia32_cvtps2udq128_mask: x86::avx512_mask_cvtps2udq_128
__builtin_ia32_cvtps2udq256_mask: x86::avx512_mask_cvtps2udq_256
__builtin_ia32_cvtps2udq512_mask: x86::avx512_mask_cvtps2udq_512
__builtin_ia32_cvtps2uqq128_mask: x86::avx512_mask_cvtps2uqq_128
__builtin_ia32_cvtps2uqq256_mask: x86::avx512_mask_cvtps2uqq_256
__builtin_ia32_cvtps2uqq512_mask: x86::avx512_mask_cvtps2uqq_512
__builtin_ia32_cvtq2mask128: x86::avx512_cvtq2mask_128
__builtin_ia32_cvtq2mask256: x86::avx512_cvtq2mask_256
__builtin_ia32_cvtq2mask512: x86::avx512_cvtq2mask_512
__builtin_ia32_cvtqq2pd128_mask: x86::avx512_mask_cvtqq2pd_128
__builtin_ia32_cvtqq2pd256_mask: x86::avx512_mask_cvtqq2pd_256
__builtin_ia32_cvtqq2pd512_mask: x86::avx512_mask_cvtqq2pd_512
__builtin_ia32_cvtqq2ps128_mask: x86::avx512_mask_cvtqq2ps_128
__builtin_ia32_cvtqq2ps256_mask: x86::avx512_mask_cvtqq2ps_256
__builtin_ia32_cvtqq2ps512_mask: x86::avx512_mask_cvtqq2ps_512
__builtin_ia32_cvtsd2si: x86::sse2_cvtsd2si
__builtin_ia32_cvtsd2si64: x86::sse2_cvtsd2si64
__builtin_ia32_cvtsd2ss: x86::sse2_cvtsd2ss
__builtin_ia32_cvtsd2ss_round_mask: x86::avx512_mask_cvtsd2ss_round
__builtin_ia32_cvtsi2sd: x86::sse2_cvtsi2sd
__builtin_ia32_cvtsi2sd32: x86::avx512_cvtsi2sd32
__builtin_ia32_cvtsi2sd64: x86::avx512_cvtsi2sd64
__builtin_ia32_cvtsi2ss: x86::sse_cvtsi2ss
__builtin_ia32_cvtsi2ss32: x86::avx512_cvtsi2ss32
__builtin_ia32_cvtsi2ss64: x86::avx512_cvtsi2ss64
__builtin_ia32_cvtsi642sd: x86::sse2_cvtsi642sd
__builtin_ia32_cvtsi642ss: x86::sse_cvtsi642ss
__builtin_ia32_cvtss2sd: x86::sse2_cvtss2sd
__builtin_ia32_cvtss2sd_round_mask: x86::avx512_mask_cvtss2sd_round
__builtin_ia32_cvtss2si: x86::sse_cvtss2si
__builtin_ia32_cvtss2si64: x86::sse_cvtss2si64
__builtin_ia32_cvttpd2dq: x86::sse2_cvttpd2dq
__builtin_ia32_cvttpd2dq128_mask: x86::avx512_mask_cvttpd2dq_128
__builtin_ia32_cvttpd2dq256: x86::avx_cvtt_pd2dq_256
__builtin_ia32_cvttpd2dq256_mask: x86::avx512_mask_cvttpd2dq_256
__builtin_ia32_cvttpd2dq512_mask: x86::avx512_mask_cvttpd2dq_512
__builtin_ia32_cvttpd2qq128_mask: x86::avx512_mask_cvttpd2qq_128
__builtin_ia32_cvttpd2qq256_mask: x86::avx512_mask_cvttpd2qq_256
__builtin_ia32_cvttpd2qq512_mask: x86::avx512_mask_cvttpd2qq_512
__builtin_ia32_cvttpd2udq128_mask: x86::avx512_mask_cvttpd2udq_128
__builtin_ia32_cvttpd2udq256_mask: x86::avx512_mask_cvttpd2udq_256
__builtin_ia32_cvttpd2udq512_mask: x86::avx512_mask_cvttpd2udq_512
__builtin_ia32_cvttpd2uqq128_mask: x86::avx512_mask_cvttpd2uqq_128
__builtin_ia32_cvttpd2uqq256_mask: x86::avx512_mask_cvttpd2uqq_256
__builtin_ia32_cvttpd2uqq512_mask: x86::avx512_mask_cvttpd2uqq_512
__builtin_ia32_cvttps2dq: x86::sse2_cvttps2dq
__builtin_ia32_cvttps2dq128_mask: x86::avx512_mask_cvttps2dq_128
__builtin_ia32_cvttps2dq256: x86::avx_cvtt_ps2dq_256
__builtin_ia32_cvttps2dq256_mask: x86::avx512_mask_cvttps2dq_256
__builtin_ia32_cvttps2dq512_mask: x86::avx512_mask_cvttps2dq_512
__builtin_ia32_cvttps2qq128_mask: x86::avx512_mask_cvttps2qq_128
__builtin_ia32_cvttps2qq256_mask: x86::avx512_mask_cvttps2qq_256
__builtin_ia32_cvttps2qq512_mask: x86::avx512_mask_cvttps2qq_512
__builtin_ia32_cvttps2udq128_mask: x86::avx512_mask_cvttps2udq_128
__builtin_ia32_cvttps2udq256_mask: x86::avx512_mask_cvttps2udq_256
__builtin_ia32_cvttps2udq512_mask: x86::avx512_mask_cvttps2udq_512
__builtin_ia32_cvttps2uqq128_mask: x86::avx512_mask_cvttps2uqq_128
__builtin_ia32_cvttps2uqq256_mask: x86::avx512_mask_cvttps2uqq_256
__builtin_ia32_cvttps2uqq512_mask: x86::avx512_mask_cvttps2uqq_512
__builtin_ia32_cvttsd2si: x86::sse2_cvttsd2si
__builtin_ia32_cvttsd2si64: x86::sse2_cvttsd2si64
__builtin_ia32_cvttss2si: x86::sse_cvttss2si
__builtin_ia32_cvttss2si64: x86::sse_cvttss2si64
__builtin_ia32_cvtudq2pd128_mask: x86::avx512_mask_cvtudq2pd_128
__builtin_ia32_cvtudq2pd256_mask: x86::avx512_mask_cvtudq2pd_256
__builtin_ia32_cvtudq2pd512_mask: x86::avx512_mask_cvtudq2pd_512
__builtin_ia32_cvtudq2ps128_mask: x86::avx512_mask_cvtudq2ps_128
__builtin_ia32_cvtudq2ps256_mask: x86::avx512_mask_cvtudq2ps_256
__builtin_ia32_cvtudq2ps512_mask: x86::avx512_mask_cvtudq2ps_512
__builtin_ia32_cvtuqq2pd128_mask: x86::avx512_mask_cvtuqq2pd_128
__builtin_ia32_cvtuqq2pd256_mask: x86::avx512_mask_cvtuqq2pd_256
__builtin_ia32_cvtuqq2pd512_mask: x86::avx512_mask_cvtuqq2pd_512
__builtin_ia32_cvtuqq2ps128_mask: x86::avx512_mask_cvtuqq2ps_128
__builtin_ia32_cvtuqq2ps256_mask: x86::avx512_mask_cvtuqq2ps_256
__builtin_ia32_cvtuqq2ps512_mask: x86::avx512_mask_cvtuqq2ps_512
__builtin_ia32_cvtusi2sd32: x86::avx512_cvtusi2sd
__builtin_ia32_cvtusi2sd64: x86::avx512_cvtusi642sd
__builtin_ia32_cvtusi2ss32: x86::avx512_cvtusi2ss
__builtin_ia32_cvtusi2ss64: x86::avx512_cvtusi642ss
__builtin_ia32_cvtw2mask128: x86::avx512_cvtw2mask_128
__builtin_ia32_cvtw2mask256: x86::avx512_cvtw2mask_256
__builtin_ia32_cvtw2mask512: x86::avx512_cvtw2mask_512
__builtin_ia32_dbpsadbw128_mask: x86::avx512_mask_dbpsadbw_128
__builtin_ia32_dbpsadbw256_mask: x86::avx512_mask_dbpsadbw_256
__builtin_ia32_dbpsadbw512_mask: x86::avx512_mask_dbpsadbw_512
__builtin_ia32_divpd256_mask: x86::avx512_mask_div_pd_256
__builtin_ia32_divpd512_mask: x86::avx512_mask_div_pd_512
__builtin_ia32_divpd_mask: x86::avx512_mask_div_pd_128
__builtin_ia32_divps256_mask: x86::avx512_mask_div_ps_256
__builtin_ia32_divps512_mask: x86::avx512_mask_div_ps_512
__builtin_ia32_divps_mask: x86::avx512_mask_div_ps_128
__builtin_ia32_divsd_round_mask: x86::avx512_mask_div_sd_round
__builtin_ia32_divss_round_mask: x86::avx512_mask_div_ss_round
__builtin_ia32_dppd: x86::sse41_dppd
__builtin_ia32_dpps: x86::sse41_dpps
__builtin_ia32_dpps256: x86::avx_dp_ps_256
__builtin_ia32_emms: x86::mmx_emms
__builtin_ia32_exp2pd_mask: x86::avx512_exp2_pd
__builtin_ia32_exp2ps_mask: x86::avx512_exp2_ps
__builtin_ia32_expanddf128_mask: x86::avx512_mask_expand_pd_128
__builtin_ia32_expanddf256_mask: x86::avx512_mask_expand_pd_256
__builtin_ia32_expanddf512_mask: x86::avx512_mask_expand_pd_512
__builtin_ia32_expanddi128_mask: x86::avx512_mask_expand_q_128
__builtin_ia32_expanddi256_mask: x86::avx512_mask_expand_q_256
__builtin_ia32_expanddi512_mask: x86::avx512_mask_expand_q_512
__builtin_ia32_expandloaddf128_mask: x86::avx512_mask_expand_load_pd_128
__builtin_ia32_expandloaddf256_mask: x86::avx512_mask_expand_load_pd_256
__builtin_ia32_expandloaddf512_mask: x86::avx512_mask_expand_load_pd_512
__builtin_ia32_expandloaddi128_mask: x86::avx512_mask_expand_load_q_128
__builtin_ia32_expandloaddi256_mask: x86::avx512_mask_expand_load_q_256
__builtin_ia32_expandloaddi512_mask: x86::avx512_mask_expand_load_q_512
__builtin_ia32_expandloadsf128_mask: x86::avx512_mask_expand_load_ps_128
__builtin_ia32_expandloadsf256_mask: x86::avx512_mask_expand_load_ps_256
__builtin_ia32_expandloadsf512_mask: x86::avx512_mask_expand_load_ps_512
__builtin_ia32_expandloadsi128_mask: x86::avx512_mask_expand_load_d_128
__builtin_ia32_expandloadsi256_mask: x86::avx512_mask_expand_load_d_256
__builtin_ia32_expandloadsi512_mask: x86::avx512_mask_expand_load_d_512
__builtin_ia32_expandsf128_mask: x86::avx512_mask_expand_ps_128
__builtin_ia32_expandsf256_mask: x86::avx512_mask_expand_ps_256
__builtin_ia32_expandsf512_mask: x86::avx512_mask_expand_ps_512
__builtin_ia32_expandsi128_mask: x86::avx512_mask_expand_d_128
__builtin_ia32_expandsi256_mask: x86::avx512_mask_expand_d_256
__builtin_ia32_expandsi512_mask: x86::avx512_mask_expand_d_512
__builtin_ia32_extractf32x4_256_mask: x86::avx512_mask_vextractf32x4_256
__builtin_ia32_extractf32x4_mask: x86::avx512_mask_vextractf32x4_512
__builtin_ia32_extractf32x8_mask: x86::avx512_mask_vextractf32x8_512
__builtin_ia32_extractf64x2_256_mask: x86::avx512_mask_vextractf64x2_256
__builtin_ia32_extractf64x2_512_mask: x86::avx512_mask_vextractf64x2_512
__builtin_ia32_extractf64x4_mask: x86::avx512_mask_vextractf64x4_512
__builtin_ia32_extracti32x4_256_mask: x86::avx512_mask_vextracti32x4_256
__builtin_ia32_extracti32x4_mask: x86::avx512_mask_vextracti32x4_512
__builtin_ia32_extracti32x8_mask: x86::avx512_mask_vextracti32x8_512
__builtin_ia32_extracti64x2_256_mask: x86::avx512_mask_vextracti64x2_256
__builtin_ia32_extracti64x2_512_mask: x86::avx512_mask_vextracti64x2_512
__builtin_ia32_extracti64x4_mask: x86::avx512_mask_vextracti64x4_512
__builtin_ia32_extrq: x86::sse4a_extrq
__builtin_ia32_extrqi: x86::sse4a_extrqi
__builtin_ia32_femms: x86::mmx_femms
__builtin_ia32_fixupimmpd128_mask: x86::avx512_mask_fixupimm_pd_128
__builtin_ia32_fixupimmpd128_maskz: x86::avx512_maskz_fixupimm_pd_128
__builtin_ia32_fixupimmpd256_mask: x86::avx512_mask_fixupimm_pd_256
__builtin_ia32_fixupimmpd256_maskz: x86::avx512_maskz_fixupimm_pd_256
__builtin_ia32_fixupimmpd512_mask: x86::avx512_mask_fixupimm_pd_512
__builtin_ia32_fixupimmpd512_maskz: x86::avx512_maskz_fixupimm_pd_512
__builtin_ia32_fixupimmps128_mask: x86::avx512_mask_fixupimm_ps_128
__builtin_ia32_fixupimmps128_maskz: x86::avx512_maskz_fixupimm_ps_128
__builtin_ia32_fixupimmps256_mask: x86::avx512_mask_fixupimm_ps_256
__builtin_ia32_fixupimmps256_maskz: x86::avx512_maskz_fixupimm_ps_256
__builtin_ia32_fixupimmps512_mask: x86::avx512_mask_fixupimm_ps_512
__builtin_ia32_fixupimmps512_maskz: x86::avx512_maskz_fixupimm_ps_512
__builtin_ia32_fixupimmsd_mask: x86::avx512_mask_fixupimm_sd
__builtin_ia32_fixupimmsd_maskz: x86::avx512_maskz_fixupimm_sd
__builtin_ia32_fixupimmss_mask: x86::avx512_mask_fixupimm_ss
__builtin_ia32_fixupimmss_maskz: x86::avx512_maskz_fixupimm_ss
__builtin_ia32_fpclasspd128_mask: x86::avx512_mask_fpclass_pd_128
__builtin_ia32_fpclasspd256_mask: x86::avx512_mask_fpclass_pd_256
__builtin_ia32_fpclasspd512_mask: x86::avx512_mask_fpclass_pd_512
__builtin_ia32_fpclassps128_mask: x86::avx512_mask_fpclass_ps_128
__builtin_ia32_fpclassps256_mask: x86::avx512_mask_fpclass_ps_256
__builtin_ia32_fpclassps512_mask: x86::avx512_mask_fpclass_ps_512
__builtin_ia32_fpclasssd_mask: x86::avx512_mask_fpclass_sd
__builtin_ia32_fpclassss_mask: x86::avx512_mask_fpclass_ss
__builtin_ia32_fxrstor: x86::fxrstor
__builtin_ia32_fxrstor64: x86::fxrstor64
__builtin_ia32_fxsave: x86::fxsave
__builtin_ia32_fxsave64: x86::fxsave64
__builtin_ia32_gather3div2df: x86::avx512_gather3div2_df
__builtin_ia32_gather3div2di: x86::avx512_gather3div2_di
__builtin_ia32_gather3div4df: x86::avx512_gather3div4_df
__builtin_ia32_gather3div4di: x86::avx512_gather3div4_di
__builtin_ia32_gather3div4sf: x86::avx512_gather3div4_sf
__builtin_ia32_gather3div4si: x86::avx512_gather3div4_si
__builtin_ia32_gather3div8sf: x86::avx512_gather3div8_sf
__builtin_ia32_gather3div8si: x86::avx512_gather3div8_si
__builtin_ia32_gather3siv2df: x86::avx512_gather3siv2_df
__builtin_ia32_gather3siv2di: x86::avx512_gather3siv2_di
__builtin_ia32_gather3siv4df: x86::avx512_gather3siv4_df
__builtin_ia32_gather3siv4di: x86::avx512_gather3siv4_di
__builtin_ia32_gather3siv4sf: x86::avx512_gather3siv4_sf
__builtin_ia32_gather3siv4si: x86::avx512_gather3siv4_si
__builtin_ia32_gather3siv8sf: x86::avx512_gather3siv8_sf
__builtin_ia32_gather3siv8si: x86::avx512_gather3siv8_si
__builtin_ia32_gatherd_d: x86::avx2_gather_d_d
__builtin_ia32_gatherd_d256: x86::avx2_gather_d_d_256
__builtin_ia32_gatherd_pd: x86::avx2_gather_d_pd
__builtin_ia32_gatherd_pd256: x86::avx2_gather_d_pd_256
__builtin_ia32_gatherd_ps: x86::avx2_gather_d_ps
__builtin_ia32_gatherd_ps256: x86::avx2_gather_d_ps_256
__builtin_ia32_gatherd_q: x86::avx2_gather_d_q
__builtin_ia32_gatherd_q256: x86::avx2_gather_d_q_256
__builtin_ia32_gatherdiv16sf: x86::avx512_gather_qps_512
__builtin_ia32_gatherdiv16si: x86::avx512_gather_qpi_512
__builtin_ia32_gatherdiv8df: x86::avx512_gather_qpd_512
__builtin_ia32_gatherdiv8di: x86::avx512_gather_qpq_512
__builtin_ia32_gatherpfdpd: x86::avx512_gatherpf_dpd_512
__builtin_ia32_gatherpfdps: x86::avx512_gatherpf_dps_512
__builtin_ia32_gatherpfqpd: x86::avx512_gatherpf_qpd_512
__builtin_ia32_gatherpfqps: x86::avx512_gatherpf_qps_512
__builtin_ia32_gatherq_d: x86::avx2_gather_q_d
__builtin_ia32_gatherq_d256: x86::avx2_gather_q_d_256
__builtin_ia32_gatherq_pd: x86::avx2_gather_q_pd
__builtin_ia32_gatherq_pd256: x86::avx2_gather_q_pd_256
__builtin_ia32_gatherq_ps: x86::avx2_gather_q_ps
__builtin_ia32_gatherq_ps256: x86::avx2_gather_q_ps_256
__builtin_ia32_gatherq_q: x86::avx2_gather_q_q
__builtin_ia32_gatherq_q256: x86::avx2_gather_q_q_256
__builtin_ia32_gathersiv16sf: x86::avx512_gather_dps_512
__builtin_ia32_gathersiv16si: x86::avx512_gather_dpi_512
__builtin_ia32_gathersiv8df: x86::avx512_gather_dpd_512
__builtin_ia32_gathersiv8di: x86::avx512_gather_dpq_512
__builtin_ia32_getexppd128_mask: x86::avx512_mask_getexp_pd_128
__builtin_ia32_getexppd256_mask: x86::avx512_mask_getexp_pd_256
__builtin_ia32_getexppd512_mask: x86::avx512_mask_getexp_pd_512
__builtin_ia32_getexpps128_mask: x86::avx512_mask_getexp_ps_128
__builtin_ia32_getexpps256_mask: x86::avx512_mask_getexp_ps_256
__builtin_ia32_getexpps512_mask: x86::avx512_mask_getexp_ps_512
__builtin_ia32_getexpsd128_round_mask: x86::avx512_mask_getexp_sd
__builtin_ia32_getexpss128_round_mask: x86::avx512_mask_getexp_ss
__builtin_ia32_getmantpd128_mask: x86::avx512_mask_getmant_pd_128
__builtin_ia32_getmantpd256_mask: x86::avx512_mask_getmant_pd_256
__builtin_ia32_getmantpd512_mask: x86::avx512_mask_getmant_pd_512
__builtin_ia32_getmantps128_mask: x86::avx512_mask_getmant_ps_128
__builtin_ia32_getmantps256_mask: x86::avx512_mask_getmant_ps_256
__builtin_ia32_getmantps512_mask: x86::avx512_mask_getmant_ps_512
__builtin_ia32_getmantsd_round_mask: x86::avx512_mask_getmant_sd
__builtin_ia32_getmantss_round_mask: x86::avx512_mask_getmant_ss
__builtin_ia32_haddpd: x86::sse3_hadd_pd
__builtin_ia32_haddpd256: x86::avx_hadd_pd_256
__builtin_ia32_haddps: x86::sse3_hadd_ps
__builtin_ia32_haddps256: x86::avx_hadd_ps_256
__builtin_ia32_hsubpd: x86::sse3_hsub_pd
__builtin_ia32_hsubpd256: x86::avx_hsub_pd_256
__builtin_ia32_hsubps: x86::sse3_hsub_ps
__builtin_ia32_hsubps256: x86::avx_hsub_ps_256
__builtin_ia32_insertf32x4_256_mask: x86::avx512_mask_insertf32x4_256
__builtin_ia32_insertf32x4_mask: x86::avx512_mask_insertf32x4_512
__builtin_ia32_insertf32x8_mask: x86::avx512_mask_insertf32x8_512
__builtin_ia32_insertf64x2_256_mask: x86::avx512_mask_insertf64x2_256
__builtin_ia32_insertf64x2_512_mask: x86::avx512_mask_insertf64x2_512
__builtin_ia32_insertf64x4_mask: x86::avx512_mask_insertf64x4_512
__builtin_ia32_inserti32x4_256_mask: x86::avx512_mask_inserti32x4_256
__builtin_ia32_inserti32x4_mask: x86::avx512_mask_inserti32x4_512
__builtin_ia32_inserti32x8_mask: x86::avx512_mask_inserti32x8_512
__builtin_ia32_inserti64x2_256_mask: x86::avx512_mask_inserti64x2_256
__builtin_ia32_inserti64x2_512_mask: x86::avx512_mask_inserti64x2_512
__builtin_ia32_inserti64x4_mask: x86::avx512_mask_inserti64x4_512
__builtin_ia32_insertps128: x86::sse41_insertps
__builtin_ia32_insertq: x86::sse4a_insertq
__builtin_ia32_insertqi: x86::sse4a_insertqi
__builtin_ia32_kandhi: x86::avx512_kand_w
__builtin_ia32_kandnhi: x86::avx512_kandn_w
__builtin_ia32_knothi: x86::avx512_knot_w
__builtin_ia32_korhi: x86::avx512_kor_w
__builtin_ia32_kortestchi: x86::avx512_kortestc_w
__builtin_ia32_kortestzhi: x86::avx512_kortestz_w
__builtin_ia32_kunpckdi: x86::avx512_kunpck_dq
__builtin_ia32_kunpckhi: x86::avx512_kunpck_bw
__builtin_ia32_kunpcksi: x86::avx512_kunpck_wd
__builtin_ia32_kxnorhi: x86::avx512_kxnor_w
__builtin_ia32_kxorhi: x86::avx512_kxor_w
__builtin_ia32_lddqu: x86::sse3_ldu_dq
__builtin_ia32_lddqu256: x86::avx_ldu_dq_256
__builtin_ia32_lfence: x86::sse2_lfence
__builtin_ia32_maskloadd: x86::avx2_maskload_d
__builtin_ia32_maskloadd256: x86::avx2_maskload_d_256
__builtin_ia32_maskloadpd: x86::avx_maskload_pd
__builtin_ia32_maskloadpd256: x86::avx_maskload_pd_256
__builtin_ia32_maskloadps: x86::avx_maskload_ps
__builtin_ia32_maskloadps256: x86::avx_maskload_ps_256
__builtin_ia32_maskloadq: x86::avx2_maskload_q
__builtin_ia32_maskloadq256: x86::avx2_maskload_q_256
__builtin_ia32_maskmovdqu: x86::sse2_maskmov_dqu
__builtin_ia32_maskstored: x86::avx2_maskstore_d
__builtin_ia32_maskstored256: x86::avx2_maskstore_d_256
__builtin_ia32_maskstorepd: x86::avx_maskstore_pd
__builtin_ia32_maskstorepd256: x86::avx_maskstore_pd_256
__builtin_ia32_maskstoreps: x86::avx_maskstore_ps
__builtin_ia32_maskstoreps256: x86::avx_maskstore_ps_256
__builtin_ia32_maskstoreq: x86::avx2_maskstore_q
__builtin_ia32_maskstoreq256: x86::avx2_maskstore_q_256
__builtin_ia32_maxpd: x86::sse2_max_pd
__builtin_ia32_maxpd256: x86::avx_max_pd_256
__builtin_ia32_maxpd256_mask: x86::avx512_mask_max_pd_256
__builtin_ia32_maxpd512_mask: x86::avx512_mask_max_pd_512
__builtin_ia32_maxpd_mask: x86::avx512_mask_max_pd_128
__builtin_ia32_maxps: x86::sse_max_ps
__builtin_ia32_maxps256: x86::avx_max_ps_256
__builtin_ia32_maxps256_mask: x86::avx512_mask_max_ps_256
__builtin_ia32_maxps512_mask: x86::avx512_mask_max_ps_512
__builtin_ia32_maxps_mask: x86::avx512_mask_max_ps_128
__builtin_ia32_maxsd: x86::sse2_max_sd
__builtin_ia32_maxsd_round_mask: x86::avx512_mask_max_sd_round
__builtin_ia32_maxss: x86::sse_max_ss
__builtin_ia32_maxss_round_mask: x86::avx512_mask_max_ss_round
__builtin_ia32_mfence: x86::sse2_mfence
__builtin_ia32_minpd: x86::sse2_min_pd
__builtin_ia32_minpd256: x86::avx_min_pd_256
__builtin_ia32_minpd256_mask: x86::avx512_mask_min_pd_256
__builtin_ia32_minpd512_mask: x86::avx512_mask_min_pd_512
__builtin_ia32_minpd_mask: x86::avx512_mask_min_pd_128
__builtin_ia32_minps: x86::sse_min_ps
__builtin_ia32_minps256: x86::avx_min_ps_256
__builtin_ia32_minps256_mask: x86::avx512_mask_min_ps_256
__builtin_ia32_minps512_mask: x86::avx512_mask_min_ps_512
__builtin_ia32_minps_mask: x86::avx512_mask_min_ps_128
__builtin_ia32_minsd: x86::sse2_min_sd
__builtin_ia32_minsd_round_mask: x86::avx512_mask_min_sd_round
__builtin_ia32_minss: x86::sse_min_ss
__builtin_ia32_minss_round_mask: x86::avx512_mask_min_ss_round
__builtin_ia32_monitor: x86::sse3_monitor
__builtin_ia32_monitorx: x86::monitorx
__builtin_ia32_movmskpd: x86::sse2_movmsk_pd
__builtin_ia32_movmskpd256: x86::avx_movmsk_pd_256
__builtin_ia32_movmskps: x86::sse_movmsk_ps
__builtin_ia32_movmskps256: x86::avx_movmsk_ps_256
__builtin_ia32_movntdqa: x86::sse41_movntdqa
__builtin_ia32_movntdqa256: x86::avx2_movntdqa
__builtin_ia32_movntdqa512: x86::avx512_movntdqa
__builtin_ia32_movsd_mask: x86::avx512_mask_move_sd
__builtin_ia32_movss_mask: x86::avx512_mask_move_ss
__builtin_ia32_mpsadbw128: x86::sse41_mpsadbw
__builtin_ia32_mpsadbw256: x86::avx2_mpsadbw
__builtin_ia32_mulpd256_mask: x86::avx512_mask_mul_pd_256
__builtin_ia32_mulpd512_mask: x86::avx512_mask_mul_pd_512
__builtin_ia32_mulpd_mask: x86::avx512_mask_mul_pd_128
__builtin_ia32_mulps256_mask: x86::avx512_mask_mul_ps_256
__builtin_ia32_mulps512_mask: x86::avx512_mask_mul_ps_512
__builtin_ia32_mulps_mask: x86::avx512_mask_mul_ps_128
__builtin_ia32_mulsd_round_mask: x86::avx512_mask_mul_sd_round
__builtin_ia32_mulss_round_mask: x86::avx512_mask_mul_ss_round
__builtin_ia32_mwait: x86::sse3_mwait
__builtin_ia32_mwaitx: x86::mwaitx
__builtin_ia32_orpd128_mask: x86::avx512_mask_or_pd_128
__builtin_ia32_orpd256_mask: x86::avx512_mask_or_pd_256
__builtin_ia32_orpd512_mask: x86::avx512_mask_or_pd_512
__builtin_ia32_orps128_mask: x86::avx512_mask_or_ps_128
__builtin_ia32_orps256_mask: x86::avx512_mask_or_ps_256
__builtin_ia32_orps512_mask: x86::avx512_mask_or_ps_512
__builtin_ia32_pabsb128: x86::ssse3_pabs_b_128
__builtin_ia32_pabsb128_mask: x86::avx512_mask_pabs_b_128
__builtin_ia32_pabsb256: x86::avx2_pabs_b
__builtin_ia32_pabsb256_mask: x86::avx512_mask_pabs_b_256
__builtin_ia32_pabsb512_mask: x86::avx512_mask_pabs_b_512
__builtin_ia32_pabsd128: x86::ssse3_pabs_d_128
__builtin_ia32_pabsd128_mask: x86::avx512_mask_pabs_d_128
__builtin_ia32_pabsd256: x86::avx2_pabs_d
__builtin_ia32_pabsd256_mask: x86::avx512_mask_pabs_d_256
__builtin_ia32_pabsd512_mask: x86::avx512_mask_pabs_d_512
__builtin_ia32_pabsq128_mask: x86::avx512_mask_pabs_q_128
__builtin_ia32_pabsq256_mask: x86::avx512_mask_pabs_q_256
__builtin_ia32_pabsq512_mask: x86::avx512_mask_pabs_q_512
__builtin_ia32_pabsw128: x86::ssse3_pabs_w_128
__builtin_ia32_pabsw128_mask: x86::avx512_mask_pabs_w_128
__builtin_ia32_pabsw256: x86::avx2_pabs_w
__builtin_ia32_pabsw256_mask: x86::avx512_mask_pabs_w_256
__builtin_ia32_pabsw512_mask: x86::avx512_mask_pabs_w_512
__builtin_ia32_packssdw128: x86::sse2_packssdw_128
__builtin_ia32_packssdw128_mask: x86::avx512_mask_packssdw_128
__builtin_ia32_packssdw256: x86::avx2_packssdw
__builtin_ia32_packssdw256_mask: x86::avx512_mask_packssdw_256
__builtin_ia32_packssdw512_mask: x86::avx512_mask_packssdw_512
__builtin_ia32_packsswb128: x86::sse2_packsswb_128
__builtin_ia32_packsswb128_mask: x86::avx512_mask_packsswb_128
__builtin_ia32_packsswb256: x86::avx2_packsswb
__builtin_ia32_packsswb256_mask: x86::avx512_mask_packsswb_256
__builtin_ia32_packsswb512_mask: x86::avx512_mask_packsswb_512
__builtin_ia32_packusdw128: x86::sse41_packusdw
__builtin_ia32_packusdw128_mask: x86::avx512_mask_packusdw_128
__builtin_ia32_packusdw256: x86::avx2_packusdw
__builtin_ia32_packusdw256_mask: x86::avx512_mask_packusdw_256
__builtin_ia32_packusdw512_mask: x86::avx512_mask_packusdw_512
__builtin_ia32_packuswb128: x86::sse2_packuswb_128
__builtin_ia32_packuswb128_mask: x86::avx512_mask_packuswb_128
__builtin_ia32_packuswb256: x86::avx2_packuswb
__builtin_ia32_packuswb256_mask: x86::avx512_mask_packuswb_256
__builtin_ia32_packuswb512_mask: x86::avx512_mask_packuswb_512
__builtin_ia32_paddb128_mask: x86::avx512_mask_padd_b_128
__builtin_ia32_paddb256_mask: x86::avx512_mask_padd_b_256
__builtin_ia32_paddb512_mask: x86::avx512_mask_padd_b_512
__builtin_ia32_paddd128_mask: x86::avx512_mask_padd_d_128
__builtin_ia32_paddd256_mask: x86::avx512_mask_padd_d_256
__builtin_ia32_paddd512_mask: x86::avx512_mask_padd_d_512
__builtin_ia32_paddq128_mask: x86::avx512_mask_padd_q_128
__builtin_ia32_paddq256_mask: x86::avx512_mask_padd_q_256
__builtin_ia32_paddq512_mask: x86::avx512_mask_padd_q_512
__builtin_ia32_paddsb128: x86::sse2_padds_b
__builtin_ia32_paddsb128_mask: x86::avx512_mask_padds_b_128
__builtin_ia32_paddsb256: x86::avx2_padds_b
__builtin_ia32_paddsb256_mask: x86::avx512_mask_padds_b_256
__builtin_ia32_paddsb512_mask: x86::avx512_mask_padds_b_512
__builtin_ia32_paddsw128: x86::sse2_padds_w
__builtin_ia32_paddsw128_mask: x86::avx512_mask_padds_w_128
__builtin_ia32_paddsw256: x86::avx2_padds_w
__builtin_ia32_paddsw256_mask: x86::avx512_mask_padds_w_256
__builtin_ia32_paddsw512_mask: x86::avx512_mask_padds_w_512
__builtin_ia32_paddusb128: x86::sse2_paddus_b
__builtin_ia32_paddusb128_mask: x86::avx512_mask_paddus_b_128
__builtin_ia32_paddusb256: x86::avx2_paddus_b
__builtin_ia32_paddusb256_mask: x86::avx512_mask_paddus_b_256
__builtin_ia32_paddusb512_mask: x86::avx512_mask_paddus_b_512
__builtin_ia32_paddusw128: x86::sse2_paddus_w
__builtin_ia32_paddusw128_mask: x86::avx512_mask_paddus_w_128
__builtin_ia32_paddusw256: x86::avx2_paddus_w
__builtin_ia32_paddusw256_mask: x86::avx512_mask_paddus_w_256
__builtin_ia32_paddusw512_mask: x86::avx512_mask_paddus_w_512
__builtin_ia32_paddw128_mask: x86::avx512_mask_padd_w_128
__builtin_ia32_paddw256_mask: x86::avx512_mask_padd_w_256
__builtin_ia32_paddw512_mask: x86::avx512_mask_padd_w_512
__builtin_ia32_pause: x86::sse2_pause
__builtin_ia32_pavgb128: x86::sse2_pavg_b
__builtin_ia32_pavgb128_mask: x86::avx512_mask_pavg_b_128
__builtin_ia32_pavgb256: x86::avx2_pavg_b
__builtin_ia32_pavgb256_mask: x86::avx512_mask_pavg_b_256
__builtin_ia32_pavgb512_mask: x86::avx512_mask_pavg_b_512
__builtin_ia32_pavgw128: x86::sse2_pavg_w
__builtin_ia32_pavgw128_mask: x86::avx512_mask_pavg_w_128
__builtin_ia32_pavgw256: x86::avx2_pavg_w
__builtin_ia32_pavgw256_mask: x86::avx512_mask_pavg_w_256
__builtin_ia32_pavgw512_mask: x86::avx512_mask_pavg_w_512
__builtin_ia32_pblendvb128: x86::sse41_pblendvb
__builtin_ia32_pblendvb256: x86::avx2_pblendvb
__builtin_ia32_pbroadcastb128_gpr_mask: x86::avx512_mask_pbroadcast_b_gpr_128
__builtin_ia32_pbroadcastb256_gpr_mask: x86::avx512_mask_pbroadcast_b_gpr_256
__builtin_ia32_pbroadcastb512_gpr_mask: x86::avx512_mask_pbroadcast_b_gpr_512
__builtin_ia32_pbroadcastd128_gpr_mask: x86::avx512_mask_pbroadcast_d_gpr_128
__builtin_ia32_pbroadcastd256_gpr_mask: x86::avx512_mask_pbroadcast_d_gpr_256
__builtin_ia32_pbroadcastd512_gpr_mask: x86::avx512_mask_pbroadcast_d_gpr_512
__builtin_ia32_pbroadcastq128_gpr_mask: x86::avx512_mask_pbroadcast_q_gpr_128
__builtin_ia32_pbroadcastq256_gpr_mask: x86::avx512_mask_pbroadcast_q_gpr_256
__builtin_ia32_pbroadcastq512_gpr_mask: x86::avx512_mask_pbroadcast_q_gpr_512
__builtin_ia32_pbroadcastq512_mem_mask: x86::avx512_mask_pbroadcast_q_mem_512
__builtin_ia32_pbroadcastw128_gpr_mask: x86::avx512_mask_pbroadcast_w_gpr_128
__builtin_ia32_pbroadcastw256_gpr_mask: x86::avx512_mask_pbroadcast_w_gpr_256
__builtin_ia32_pbroadcastw512_gpr_mask: x86::avx512_mask_pbroadcast_w_gpr_512
__builtin_ia32_pclmulqdq128: x86::pclmulqdq
__builtin_ia32_pcmpestri128: x86::sse42_pcmpestri128
__builtin_ia32_pcmpestria128: x86::sse42_pcmpestria128
__builtin_ia32_pcmpestric128: x86::sse42_pcmpestric128
__builtin_ia32_pcmpestrio128: x86::sse42_pcmpestrio128
__builtin_ia32_pcmpestris128: x86::sse42_pcmpestris128
__builtin_ia32_pcmpestriz128: x86::sse42_pcmpestriz128
__builtin_ia32_pcmpestrm128: x86::sse42_pcmpestrm128
__builtin_ia32_pcmpistri128: x86::sse42_pcmpistri128
__builtin_ia32_pcmpistria128: x86::sse42_pcmpistria128
__builtin_ia32_pcmpistric128: x86::sse42_pcmpistric128
__builtin_ia32_pcmpistrio128: x86::sse42_pcmpistrio128
__builtin_ia32_pcmpistris128: x86::sse42_pcmpistris128
__builtin_ia32_pcmpistriz128: x86::sse42_pcmpistriz128
__builtin_ia32_pcmpistrm128: x86::sse42_pcmpistrm128
__builtin_ia32_pdep_di: x86::bmi_pdep_64
__builtin_ia32_pdep_si: x86::bmi_pdep_32
__builtin_ia32_permti256: x86::avx2_vperm2i128
__builtin_ia32_permvardf256_mask: x86::avx512_mask_permvar_df_256
__builtin_ia32_permvardf512_mask: x86::avx512_mask_permvar_df_512
__builtin_ia32_permvardi256_mask: x86::avx512_mask_permvar_di_256
__builtin_ia32_permvardi512_mask: x86::avx512_mask_permvar_di_512
__builtin_ia32_permvarhi128_mask: x86::avx512_mask_permvar_hi_128
__builtin_ia32_permvarhi256_mask: x86::avx512_mask_permvar_hi_256
__builtin_ia32_permvarhi512_mask: x86::avx512_mask_permvar_hi_512
__builtin_ia32_permvarqi128_mask: x86::avx512_mask_permvar_qi_128
__builtin_ia32_permvarqi256_mask: x86::avx512_mask_permvar_qi_256
__builtin_ia32_permvarqi512_mask: x86::avx512_mask_permvar_qi_512
__builtin_ia32_permvarsf256: x86::avx2_permps
__builtin_ia32_permvarsf256_mask: x86::avx512_mask_permvar_sf_256
__builtin_ia32_permvarsf512_mask: x86::avx512_mask_permvar_sf_512
__builtin_ia32_permvarsi256: x86::avx2_permd
__builtin_ia32_permvarsi256_mask: x86::avx512_mask_permvar_si_256
__builtin_ia32_permvarsi512_mask: x86::avx512_mask_permvar_si_512
__builtin_ia32_pext_di: x86::bmi_pext_64
__builtin_ia32_pext_si: x86::bmi_pext_32
__builtin_ia32_phaddd128: x86::ssse3_phadd_d_128
__builtin_ia32_phaddd256: x86::avx2_phadd_d
__builtin_ia32_phaddsw128: x86::ssse3_phadd_sw_128
__builtin_ia32_phaddsw256: x86::avx2_phadd_sw
__builtin_ia32_phaddw128: x86::ssse3_phadd_w_128
__builtin_ia32_phaddw256: x86::avx2_phadd_w
__builtin_ia32_phminposuw128: x86::sse41_phminposuw
__builtin_ia32_phsubd128: x86::ssse3_phsub_d_128
__builtin_ia32_phsubd256: x86::avx2_phsub_d
__builtin_ia32_phsubsw128: x86::ssse3_phsub_sw_128
__builtin_ia32_phsubsw256: x86::avx2_phsub_sw
__builtin_ia32_phsubw128: x86::ssse3_phsub_w_128
__builtin_ia32_phsubw256: x86::avx2_phsub_w
__builtin_ia32_pmaddubsw128: x86::ssse3_pmadd_ub_sw_128
__builtin_ia32_pmaddubsw128_mask: x86::avx512_mask_pmaddubs_w_128
__builtin_ia32_pmaddubsw256: x86::avx2_pmadd_ub_sw
__builtin_ia32_pmaddubsw256_mask: x86::avx512_mask_pmaddubs_w_256
__builtin_ia32_pmaddubsw512_mask: x86::avx512_mask_pmaddubs_w_512
__builtin_ia32_pmaddwd128: x86::sse2_pmadd_wd
__builtin_ia32_pmaddwd128_mask: x86::avx512_mask_pmaddw_d_128
__builtin_ia32_pmaddwd256: x86::avx2_pmadd_wd
__builtin_ia32_pmaddwd256_mask: x86::avx512_mask_pmaddw_d_256
__builtin_ia32_pmaddwd512_mask: x86::avx512_mask_pmaddw_d_512
__builtin_ia32_pmaxsb128_mask: x86::avx512_mask_pmaxs_b_128
__builtin_ia32_pmaxsb256_mask: x86::avx512_mask_pmaxs_b_256
__builtin_ia32_pmaxsb512_mask: x86::avx512_mask_pmaxs_b_512
__builtin_ia32_pmaxsd128_mask: x86::avx512_mask_pmaxs_d_128
__builtin_ia32_pmaxsd256_mask: x86::avx512_mask_pmaxs_d_256
__builtin_ia32_pmaxsd512_mask: x86::avx512_mask_pmaxs_d_512
__builtin_ia32_pmaxsq128_mask: x86::avx512_mask_pmaxs_q_128
__builtin_ia32_pmaxsq256_mask: x86::avx512_mask_pmaxs_q_256
__builtin_ia32_pmaxsq512_mask: x86::avx512_mask_pmaxs_q_512
__builtin_ia32_pmaxsw128_mask: x86::avx512_mask_pmaxs_w_128
__builtin_ia32_pmaxsw256_mask: x86::avx512_mask_pmaxs_w_256
__builtin_ia32_pmaxsw512_mask: x86::avx512_mask_pmaxs_w_512
__builtin_ia32_pmaxub128_mask: x86::avx512_mask_pmaxu_b_128
__builtin_ia32_pmaxub256_mask: x86::avx512_mask_pmaxu_b_256
__builtin_ia32_pmaxub512_mask: x86::avx512_mask_pmaxu_b_512
__builtin_ia32_pmaxud128_mask: x86::avx512_mask_pmaxu_d_128
__builtin_ia32_pmaxud256_mask: x86::avx512_mask_pmaxu_d_256
__builtin_ia32_pmaxud512_mask: x86::avx512_mask_pmaxu_d_512
__builtin_ia32_pmaxuq128_mask: x86::avx512_mask_pmaxu_q_128
__builtin_ia32_pmaxuq256_mask: x86::avx512_mask_pmaxu_q_256
__builtin_ia32_pmaxuq512_mask: x86::avx512_mask_pmaxu_q_512
__builtin_ia32_pmaxuw128_mask: x86::avx512_mask_pmaxu_w_128
__builtin_ia32_pmaxuw256_mask: x86::avx512_mask_pmaxu_w_256
__builtin_ia32_pmaxuw512_mask: x86::avx512_mask_pmaxu_w_512
__builtin_ia32_pminsb128_mask: x86::avx512_mask_pmins_b_128
__builtin_ia32_pminsb256_mask: x86::avx512_mask_pmins_b_256
__builtin_ia32_pminsb512_mask: x86::avx512_mask_pmins_b_512
__builtin_ia32_pminsd128_mask: x86::avx512_mask_pmins_d_128
__builtin_ia32_pminsd256_mask: x86::avx512_mask_pmins_d_256
__builtin_ia32_pminsd512_mask: x86::avx512_mask_pmins_d_512
__builtin_ia32_pminsq128_mask: x86::avx512_mask_pmins_q_128
__builtin_ia32_pminsq256_mask: x86::avx512_mask_pmins_q_256
__builtin_ia32_pminsq512_mask: x86::avx512_mask_pmins_q_512
__builtin_ia32_pminsw128_mask: x86::avx512_mask_pmins_w_128
__builtin_ia32_pminsw256_mask: x86::avx512_mask_pmins_w_256
__builtin_ia32_pminsw512_mask: x86::avx512_mask_pmins_w_512
__builtin_ia32_pminub128_mask: x86::avx512_mask_pminu_b_128
__builtin_ia32_pminub256_mask: x86::avx512_mask_pminu_b_256
__builtin_ia32_pminub512_mask: x86::avx512_mask_pminu_b_512
__builtin_ia32_pminud128_mask: x86::avx512_mask_pminu_d_128
__builtin_ia32_pminud256_mask: x86::avx512_mask_pminu_d_256
__builtin_ia32_pminud512_mask: x86::avx512_mask_pminu_d_512
__builtin_ia32_pminuq128_mask: x86::avx512_mask_pminu_q_128
__builtin_ia32_pminuq256_mask: x86::avx512_mask_pminu_q_256
__builtin_ia32_pminuq512_mask: x86::avx512_mask_pminu_q_512
__builtin_ia32_pminuw128_mask: x86::avx512_mask_pminu_w_128
__builtin_ia32_pminuw256_mask: x86::avx512_mask_pminu_w_256
__builtin_ia32_pminuw512_mask: x86::avx512_mask_pminu_w_512
__builtin_ia32_pmovdb128_mask: x86::avx512_mask_pmov_db_128
__builtin_ia32_pmovdb128mem_mask: x86::avx512_mask_pmov_db_mem_128
__builtin_ia32_pmovdb256_mask: x86::avx512_mask_pmov_db_256
__builtin_ia32_pmovdb256mem_mask: x86::avx512_mask_pmov_db_mem_256
__builtin_ia32_pmovdb512_mask: x86::avx512_mask_pmov_db_512
__builtin_ia32_pmovdb512mem_mask: x86::avx512_mask_pmov_db_mem_512
__builtin_ia32_pmovdw128_mask: x86::avx512_mask_pmov_dw_128
__builtin_ia32_pmovdw128mem_mask: x86::avx512_mask_pmov_dw_mem_128
__builtin_ia32_pmovdw256_mask: x86::avx512_mask_pmov_dw_256
__builtin_ia32_pmovdw256mem_mask: x86::avx512_mask_pmov_dw_mem_256
__builtin_ia32_pmovdw512_mask: x86::avx512_mask_pmov_dw_512
__builtin_ia32_pmovdw512mem_mask: x86::avx512_mask_pmov_dw_mem_512
__builtin_ia32_pmovmskb128: x86::sse2_pmovmskb_128
__builtin_ia32_pmovmskb256: x86::avx2_pmovmskb
__builtin_ia32_pmovqb128_mask: x86::avx512_mask_pmov_qb_128
__builtin_ia32_pmovqb128mem_mask: x86::avx512_mask_pmov_qb_mem_128
__builtin_ia32_pmovqb256_mask: x86::avx512_mask_pmov_qb_256
__builtin_ia32_pmovqb256mem_mask: x86::avx512_mask_pmov_qb_mem_256
__builtin_ia32_pmovqb512_mask: x86::avx512_mask_pmov_qb_512
__builtin_ia32_pmovqb512mem_mask: x86::avx512_mask_pmov_qb_mem_512
__builtin_ia32_pmovqd128_mask: x86::avx512_mask_pmov_qd_128
__builtin_ia32_pmovqd128mem_mask: x86::avx512_mask_pmov_qd_mem_128
__builtin_ia32_pmovqd256_mask: x86::avx512_mask_pmov_qd_256
__builtin_ia32_pmovqd256mem_mask: x86::avx512_mask_pmov_qd_mem_256
__builtin_ia32_pmovqd512_mask: x86::avx512_mask_pmov_qd_512
__builtin_ia32_pmovqd512mem_mask: x86::avx512_mask_pmov_qd_mem_512
__builtin_ia32_pmovqw128_mask: x86::avx512_mask_pmov_qw_128
__builtin_ia32_pmovqw128mem_mask: x86::avx512_mask_pmov_qw_mem_128
__builtin_ia32_pmovqw256_mask: x86::avx512_mask_pmov_qw_256
__builtin_ia32_pmovqw256mem_mask: x86::avx512_mask_pmov_qw_mem_256
__builtin_ia32_pmovqw512_mask: x86::avx512_mask_pmov_qw_512
__builtin_ia32_pmovqw512mem_mask: x86::avx512_mask_pmov_qw_mem_512
__builtin_ia32_pmovsdb128_mask: x86::avx512_mask_pmovs_db_128
__builtin_ia32_pmovsdb128mem_mask: x86::avx512_mask_pmovs_db_mem_128
__builtin_ia32_pmovsdb256_mask: x86::avx512_mask_pmovs_db_256
__builtin_ia32_pmovsdb256mem_mask: x86::avx512_mask_pmovs_db_mem_256
__builtin_ia32_pmovsdb512_mask: x86::avx512_mask_pmovs_db_512
__builtin_ia32_pmovsdb512mem_mask: x86::avx512_mask_pmovs_db_mem_512
__builtin_ia32_pmovsdw128_mask: x86::avx512_mask_pmovs_dw_128
__builtin_ia32_pmovsdw128mem_mask: x86::avx512_mask_pmovs_dw_mem_128
__builtin_ia32_pmovsdw256_mask: x86::avx512_mask_pmovs_dw_256
__builtin_ia32_pmovsdw256mem_mask: x86::avx512_mask_pmovs_dw_mem_256
__builtin_ia32_pmovsdw512_mask: x86::avx512_mask_pmovs_dw_512
__builtin_ia32_pmovsdw512mem_mask: x86::avx512_mask_pmovs_dw_mem_512
__builtin_ia32_pmovsqb128_mask: x86::avx512_mask_pmovs_qb_128
__builtin_ia32_pmovsqb128mem_mask: x86::avx512_mask_pmovs_qb_mem_128
__builtin_ia32_pmovsqb256_mask: x86::avx512_mask_pmovs_qb_256
__builtin_ia32_pmovsqb256mem_mask: x86::avx512_mask_pmovs_qb_mem_256
__builtin_ia32_pmovsqb512_mask: x86::avx512_mask_pmovs_qb_512
__builtin_ia32_pmovsqb512mem_mask: x86::avx512_mask_pmovs_qb_mem_512
__builtin_ia32_pmovsqd128_mask: x86::avx512_mask_pmovs_qd_128
__builtin_ia32_pmovsqd128mem_mask: x86::avx512_mask_pmovs_qd_mem_128
__builtin_ia32_pmovsqd256_mask: x86::avx512_mask_pmovs_qd_256
__builtin_ia32_pmovsqd256mem_mask: x86::avx512_mask_pmovs_qd_mem_256
__builtin_ia32_pmovsqd512_mask: x86::avx512_mask_pmovs_qd_512
__builtin_ia32_pmovsqd512mem_mask: x86::avx512_mask_pmovs_qd_mem_512
__builtin_ia32_pmovsqw128_mask: x86::avx512_mask_pmovs_qw_128
__builtin_ia32_pmovsqw128mem_mask: x86::avx512_mask_pmovs_qw_mem_128
__builtin_ia32_pmovsqw256_mask: x86::avx512_mask_pmovs_qw_256
__builtin_ia32_pmovsqw256mem_mask: x86::avx512_mask_pmovs_qw_mem_256
__builtin_ia32_pmovsqw512_mask: x86::avx512_mask_pmovs_qw_512
__builtin_ia32_pmovsqw512mem_mask: x86::avx512_mask_pmovs_qw_mem_512
__builtin_ia32_pmovswb128_mask: x86::avx512_mask_pmovs_wb_128
__builtin_ia32_pmovswb128mem_mask: x86::avx512_mask_pmovs_wb_mem_128
__builtin_ia32_pmovswb256_mask: x86::avx512_mask_pmovs_wb_256
__builtin_ia32_pmovswb256mem_mask: x86::avx512_mask_pmovs_wb_mem_256
__builtin_ia32_pmovswb512_mask: x86::avx512_mask_pmovs_wb_512
__builtin_ia32_pmovswb512mem_mask: x86::avx512_mask_pmovs_wb_mem_512
__builtin_ia32_pmovsxbd128_mask: x86::avx512_mask_pmovsxb_d_128
__builtin_ia32_pmovsxbd256_mask: x86::avx512_mask_pmovsxb_d_256
__builtin_ia32_pmovsxbd512_mask: x86::avx512_mask_pmovsxb_d_512
__builtin_ia32_pmovsxbq128_mask: x86::avx512_mask_pmovsxb_q_128
__builtin_ia32_pmovsxbq256_mask: x86::avx512_mask_pmovsxb_q_256
__builtin_ia32_pmovsxbq512_mask: x86::avx512_mask_pmovsxb_q_512
__builtin_ia32_pmovsxbw128_mask: x86::avx512_mask_pmovsxb_w_128
__builtin_ia32_pmovsxbw256_mask: x86::avx512_mask_pmovsxb_w_256
__builtin_ia32_pmovsxbw512_mask: x86::avx512_mask_pmovsxb_w_512
__builtin_ia32_pmovsxdq128_mask: x86::avx512_mask_pmovsxd_q_128
__builtin_ia32_pmovsxdq256_mask: x86::avx512_mask_pmovsxd_q_256
__builtin_ia32_pmovsxdq512_mask: x86::avx512_mask_pmovsxd_q_512
__builtin_ia32_pmovsxwd128_mask: x86::avx512_mask_pmovsxw_d_128
__builtin_ia32_pmovsxwd256_mask: x86::avx512_mask_pmovsxw_d_256
__builtin_ia32_pmovsxwd512_mask: x86::avx512_mask_pmovsxw_d_512
__builtin_ia32_pmovsxwq128_mask: x86::avx512_mask_pmovsxw_q_128
__builtin_ia32_pmovsxwq256_mask: x86::avx512_mask_pmovsxw_q_256
__builtin_ia32_pmovsxwq512_mask: x86::avx512_mask_pmovsxw_q_512
__builtin_ia32_pmovusdb128_mask: x86::avx512_mask_pmovus_db_128
__builtin_ia32_pmovusdb128mem_mask: x86::avx512_mask_pmovus_db_mem_128
__builtin_ia32_pmovusdb256_mask: x86::avx512_mask_pmovus_db_256
__builtin_ia32_pmovusdb256mem_mask: x86::avx512_mask_pmovus_db_mem_256
__builtin_ia32_pmovusdb512_mask: x86::avx512_mask_pmovus_db_512
__builtin_ia32_pmovusdb512mem_mask: x86::avx512_mask_pmovus_db_mem_512
__builtin_ia32_pmovusdw128_mask: x86::avx512_mask_pmovus_dw_128
__builtin_ia32_pmovusdw128mem_mask: x86::avx512_mask_pmovus_dw_mem_128
__builtin_ia32_pmovusdw256_mask: x86::avx512_mask_pmovus_dw_256
__builtin_ia32_pmovusdw256mem_mask: x86::avx512_mask_pmovus_dw_mem_256
__builtin_ia32_pmovusdw512_mask: x86::avx512_mask_pmovus_dw_512
__builtin_ia32_pmovusdw512mem_mask: x86::avx512_mask_pmovus_dw_mem_512
__builtin_ia32_pmovusqb128_mask: x86::avx512_mask_pmovus_qb_128
__builtin_ia32_pmovusqb128mem_mask: x86::avx512_mask_pmovus_qb_mem_128
__builtin_ia32_pmovusqb256_mask: x86::avx512_mask_pmovus_qb_256
__builtin_ia32_pmovusqb256mem_mask: x86::avx512_mask_pmovus_qb_mem_256
__builtin_ia32_pmovusqb512_mask: x86::avx512_mask_pmovus_qb_512
__builtin_ia32_pmovusqb512mem_mask: x86::avx512_mask_pmovus_qb_mem_512
__builtin_ia32_pmovusqd128_mask: x86::avx512_mask_pmovus_qd_128
__builtin_ia32_pmovusqd128mem_mask: x86::avx512_mask_pmovus_qd_mem_128
__builtin_ia32_pmovusqd256_mask: x86::avx512_mask_pmovus_qd_256
__builtin_ia32_pmovusqd256mem_mask: x86::avx512_mask_pmovus_qd_mem_256
__builtin_ia32_pmovusqd512_mask: x86::avx512_mask_pmovus_qd_512
__builtin_ia32_pmovusqd512mem_mask: x86::avx512_mask_pmovus_qd_mem_512
__builtin_ia32_pmovusqw128_mask: x86::avx512_mask_pmovus_qw_128
__builtin_ia32_pmovusqw128mem_mask: x86::avx512_mask_pmovus_qw_mem_128
__builtin_ia32_pmovusqw256_mask: x86::avx512_mask_pmovus_qw_256
__builtin_ia32_pmovusqw256mem_mask: x86::avx512_mask_pmovus_qw_mem_256
__builtin_ia32_pmovusqw512_mask: x86::avx512_mask_pmovus_qw_512
__builtin_ia32_pmovusqw512mem_mask: x86::avx512_mask_pmovus_qw_mem_512
__builtin_ia32_pmovuswb128_mask: x86::avx512_mask_pmovus_wb_128
__builtin_ia32_pmovuswb128mem_mask: x86::avx512_mask_pmovus_wb_mem_128
__builtin_ia32_pmovuswb256_mask: x86::avx512_mask_pmovus_wb_256
__builtin_ia32_pmovuswb256mem_mask: x86::avx512_mask_pmovus_wb_mem_256
__builtin_ia32_pmovuswb512_mask: x86::avx512_mask_pmovus_wb_512
__builtin_ia32_pmovuswb512mem_mask: x86::avx512_mask_pmovus_wb_mem_512
__builtin_ia32_pmovwb128_mask: x86::avx512_mask_pmov_wb_128
__builtin_ia32_pmovwb128mem_mask: x86::avx512_mask_pmov_wb_mem_128
__builtin_ia32_pmovwb256_mask: x86::avx512_mask_pmov_wb_256
__builtin_ia32_pmovwb256mem_mask: x86::avx512_mask_pmov_wb_mem_256
__builtin_ia32_pmovwb512_mask: x86::avx512_mask_pmov_wb_512
__builtin_ia32_pmovwb512mem_mask: x86::avx512_mask_pmov_wb_mem_512
__builtin_ia32_pmovzxbd128_mask: x86::avx512_mask_pmovzxb_d_128
__builtin_ia32_pmovzxbd256_mask: x86::avx512_mask_pmovzxb_d_256
__builtin_ia32_pmovzxbd512: x86::avx512_pmovzxbd
__builtin_ia32_pmovzxbd512_mask: x86::avx512_mask_pmovzxb_d_512
__builtin_ia32_pmovzxbq128_mask: x86::avx512_mask_pmovzxb_q_128
__builtin_ia32_pmovzxbq256_mask: x86::avx512_mask_pmovzxb_q_256
__builtin_ia32_pmovzxbq512: x86::avx512_pmovzxbq
__builtin_ia32_pmovzxbq512_mask: x86::avx512_mask_pmovzxb_q_512
__builtin_ia32_pmovzxbw128_mask: x86::avx512_mask_pmovzxb_w_128
__builtin_ia32_pmovzxbw256_mask: x86::avx512_mask_pmovzxb_w_256
__builtin_ia32_pmovzxbw512_mask: x86::avx512_mask_pmovzxb_w_512
__builtin_ia32_pmovzxdq128_mask: x86::avx512_mask_pmovzxd_q_128
__builtin_ia32_pmovzxdq256_mask: x86::avx512_mask_pmovzxd_q_256
__builtin_ia32_pmovzxdq512: x86::avx512_pmovzxdq
__builtin_ia32_pmovzxdq512_mask: x86::avx512_mask_pmovzxd_q_512
__builtin_ia32_pmovzxwd128_mask: x86::avx512_mask_pmovzxw_d_128
__builtin_ia32_pmovzxwd256_mask: x86::avx512_mask_pmovzxw_d_256
__builtin_ia32_pmovzxwd512: x86::avx512_pmovzxwd
__builtin_ia32_pmovzxwd512_mask: x86::avx512_mask_pmovzxw_d_512
__builtin_ia32_pmovzxwq128_mask: x86::avx512_mask_pmovzxw_q_128
__builtin_ia32_pmovzxwq256_mask: x86::avx512_mask_pmovzxw_q_256
__builtin_ia32_pmovzxwq512: x86::avx512_pmovzxwq
__builtin_ia32_pmovzxwq512_mask: x86::avx512_mask_pmovzxw_q_512
__builtin_ia32_pmuldq128: x86::sse41_pmuldq
__builtin_ia32_pmuldq128_mask: x86::avx512_mask_pmul_dq_128
__builtin_ia32_pmuldq256: x86::avx2_pmul_dq
__builtin_ia32_pmuldq256_mask: x86::avx512_mask_pmul_dq_256
__builtin_ia32_pmuldq512_mask: x86::avx512_mask_pmul_dq_512
__builtin_ia32_pmulhrsw128: x86::ssse3_pmul_hr_sw_128
__builtin_ia32_pmulhrsw128_mask: x86::avx512_mask_pmul_hr_sw_128
__builtin_ia32_pmulhrsw256: x86::avx2_pmul_hr_sw
__builtin_ia32_pmulhrsw256_mask: x86::avx512_mask_pmul_hr_sw_256
__builtin_ia32_pmulhrsw512_mask: x86::avx512_mask_pmul_hr_sw_512
__builtin_ia32_pmulhuw128: x86::sse2_pmulhu_w
__builtin_ia32_pmulhuw128_mask: x86::avx512_mask_pmulhu_w_128
__builtin_ia32_pmulhuw256: x86::avx2_pmulhu_w
__builtin_ia32_pmulhuw256_mask: x86::avx512_mask_pmulhu_w_256
__builtin_ia32_pmulhuw512_mask: x86::avx512_mask_pmulhu_w_512
__builtin_ia32_pmulhw128: x86::sse2_pmulh_w
__builtin_ia32_pmulhw128_mask: x86::avx512_mask_pmulh_w_128
__builtin_ia32_pmulhw256: x86::avx2_pmulh_w
__builtin_ia32_pmulhw256_mask: x86::avx512_mask_pmulh_w_256
__builtin_ia32_pmulhw512_mask: x86::avx512_mask_pmulh_w_512
__builtin_ia32_pmulld128_mask: x86::avx512_mask_pmull_d_128
__builtin_ia32_pmulld256_mask: x86::avx512_mask_pmull_d_256
__builtin_ia32_pmulld512_mask: x86::avx512_mask_pmull_d_512
__builtin_ia32_pmullq128_mask: x86::avx512_mask_pmull_q_128
__builtin_ia32_pmullq256_mask: x86::avx512_mask_pmull_q_256
__builtin_ia32_pmullq512_mask: x86::avx512_mask_pmull_q_512
__builtin_ia32_pmullw128_mask: x86::avx512_mask_pmull_w_128
__builtin_ia32_pmullw256_mask: x86::avx512_mask_pmull_w_256
__builtin_ia32_pmullw512_mask: x86::avx512_mask_pmull_w_512
__builtin_ia32_pmuludq128: x86::sse2_pmulu_dq
__builtin_ia32_pmuludq128_mask: x86::avx512_mask_pmulu_dq_128
__builtin_ia32_pmuludq256: x86::avx2_pmulu_dq
__builtin_ia32_pmuludq256_mask: x86::avx512_mask_pmulu_dq_256
__builtin_ia32_pmuludq512_mask: x86::avx512_mask_pmulu_dq_512
__builtin_ia32_prold128_mask: x86::avx512_mask_prol_d_128
__builtin_ia32_prold256_mask: x86::avx512_mask_prol_d_256
__builtin_ia32_prold512_mask: x86::avx512_mask_prol_d_512
__builtin_ia32_prolq128_mask: x86::avx512_mask_prol_q_128
__builtin_ia32_prolq256_mask: x86::avx512_mask_prol_q_256
__builtin_ia32_prolq512_mask: x86::avx512_mask_prol_q_512
__builtin_ia32_prolvd128_mask: x86::avx512_mask_prolv_d_128
__builtin_ia32_prolvd256_mask: x86::avx512_mask_prolv_d_256
__builtin_ia32_prolvd512_mask: x86::avx512_mask_prolv_d_512
__builtin_ia32_prolvq128_mask: x86::avx512_mask_prolv_q_128
__builtin_ia32_prolvq256_mask: x86::avx512_mask_prolv_q_256
__builtin_ia32_prolvq512_mask: x86::avx512_mask_prolv_q_512
__builtin_ia32_prord128_mask: x86::avx512_mask_pror_d_128
__builtin_ia32_prord256_mask: x86::avx512_mask_pror_d_256
__builtin_ia32_prord512_mask: x86::avx512_mask_pror_d_512
__builtin_ia32_prorq128_mask: x86::avx512_mask_pror_q_128
__builtin_ia32_prorq256_mask: x86::avx512_mask_pror_q_256
__builtin_ia32_prorq512_mask: x86::avx512_mask_pror_q_512
__builtin_ia32_prorvd128_mask: x86::avx512_mask_prorv_d_128
__builtin_ia32_prorvd256_mask: x86::avx512_mask_prorv_d_256
__builtin_ia32_prorvd512_mask: x86::avx512_mask_prorv_d_512
__builtin_ia32_prorvq128_mask: x86::avx512_mask_prorv_q_128
__builtin_ia32_prorvq256_mask: x86::avx512_mask_prorv_q_256
__builtin_ia32_prorvq512_mask: x86::avx512_mask_prorv_q_512
__builtin_ia32_psadbw128: x86::sse2_psad_bw
__builtin_ia32_psadbw256: x86::avx2_psad_bw
__builtin_ia32_psadbw512: x86::avx512_psad_bw_512
__builtin_ia32_pshufb128: x86::ssse3_pshuf_b_128
__builtin_ia32_pshufb128_mask: x86::avx512_mask_pshuf_b_128
__builtin_ia32_pshufb256: x86::avx2_pshuf_b
__builtin_ia32_pshufb256_mask: x86::avx512_mask_pshuf_b_256
__builtin_ia32_pshufb512_mask: x86::avx512_mask_pshuf_b_512
__builtin_ia32_psignb128: x86::ssse3_psign_b_128
__builtin_ia32_psignb256: x86::avx2_psign_b
__builtin_ia32_psignd128: x86::ssse3_psign_d_128
__builtin_ia32_psignd256: x86::avx2_psign_d
__builtin_ia32_psignw128: x86::ssse3_psign_w_128
__builtin_ia32_psignw256: x86::avx2_psign_w
__builtin_ia32_pslld128: x86::sse2_psll_d
__builtin_ia32_pslld128_mask: x86::avx512_mask_psll_d_128
__builtin_ia32_pslld256: x86::avx2_psll_d
__builtin_ia32_pslld256_mask: x86::avx512_mask_psll_d_256
__builtin_ia32_pslld512_mask: x86::avx512_mask_psll_d
__builtin_ia32_pslldi128: x86::sse2_pslli_d
__builtin_ia32_pslldi128_mask: x86::avx512_mask_psll_di_128
__builtin_ia32_pslldi256: x86::avx2_pslli_d
__builtin_ia32_pslldi256_mask: x86::avx512_mask_psll_di_256
__builtin_ia32_pslldi512_mask: x86::avx512_mask_psll_di_512
__builtin_ia32_psllq128: x86::sse2_psll_q
__builtin_ia32_psllq128_mask: x86::avx512_mask_psll_q_128
__builtin_ia32_psllq256: x86::avx2_psll_q
__builtin_ia32_psllq256_mask: x86::avx512_mask_psll_q_256
__builtin_ia32_psllq512_mask: x86::avx512_mask_psll_q
__builtin_ia32_psllqi128: x86::sse2_pslli_q
__builtin_ia32_psllqi128_mask: x86::avx512_mask_psll_qi_128
__builtin_ia32_psllqi256: x86::avx2_pslli_q
__builtin_ia32_psllqi256_mask: x86::avx512_mask_psll_qi_256
__builtin_ia32_psllqi512_mask: x86::avx512_mask_psll_qi_512
__builtin_ia32_psllv16hi_mask: x86::avx512_mask_psllv16_hi
__builtin_ia32_psllv16si_mask: x86::avx512_mask_psllv_d
__builtin_ia32_psllv2di: x86::avx2_psllv_q
__builtin_ia32_psllv2di_mask: x86::avx512_mask_psllv2_di
__builtin_ia32_psllv32hi_mask: x86::avx512_mask_psllv32hi
__builtin_ia32_psllv4di: x86::avx2_psllv_q_256
__builtin_ia32_psllv4di_mask: x86::avx512_mask_psllv4_di
__builtin_ia32_psllv4si: x86::avx2_psllv_d
__builtin_ia32_psllv4si_mask: x86::avx512_mask_psllv4_si
__builtin_ia32_psllv8di_mask: x86::avx512_mask_psllv_q
__builtin_ia32_psllv8hi_mask: x86::avx512_mask_psllv8_hi
__builtin_ia32_psllv8si: x86::avx2_psllv_d_256
__builtin_ia32_psllv8si_mask: x86::avx512_mask_psllv8_si
__builtin_ia32_psllw128: x86::sse2_psll_w
__builtin_ia32_psllw128_mask: x86::avx512_mask_psll_w_128
__builtin_ia32_psllw256: x86::avx2_psll_w
__builtin_ia32_psllw256_mask: x86::avx512_mask_psll_w_256
__builtin_ia32_psllw512_mask: x86::avx512_mask_psll_w_512
__builtin_ia32_psllwi128: x86::sse2_pslli_w
__builtin_ia32_psllwi128_mask: x86::avx512_mask_psll_wi_128
__builtin_ia32_psllwi256: x86::avx2_pslli_w
__builtin_ia32_psllwi256_mask: x86::avx512_mask_psll_wi_256
__builtin_ia32_psllwi512_mask: x86::avx512_mask_psll_wi_512
__builtin_ia32_psrad128: x86::sse2_psra_d
__builtin_ia32_psrad128_mask: x86::avx512_mask_psra_d_128
__builtin_ia32_psrad256: x86::avx2_psra_d
__builtin_ia32_psrad256_mask: x86::avx512_mask_psra_d_256
__builtin_ia32_psrad512_mask: x86::avx512_mask_psra_d
__builtin_ia32_psradi128: x86::sse2_psrai_d
__builtin_ia32_psradi128_mask: x86::avx512_mask_psra_di_128
__builtin_ia32_psradi256: x86::avx2_psrai_d
__builtin_ia32_psradi256_mask: x86::avx512_mask_psra_di_256
__builtin_ia32_psradi512_mask: x86::avx512_mask_psra_di_512
__builtin_ia32_psraq128_mask: x86::avx512_mask_psra_q_128
__builtin_ia32_psraq256_mask: x86::avx512_mask_psra_q_256
__builtin_ia32_psraq512_mask: x86::avx512_mask_psra_q
__builtin_ia32_psraqi128_mask: x86::avx512_mask_psra_qi_128
__builtin_ia32_psraqi256_mask: x86::avx512_mask_psra_qi_256
__builtin_ia32_psraqi512_mask: x86::avx512_mask_psra_qi_512
__builtin_ia32_psrav16hi_mask: x86::avx512_mask_psrav16_hi
__builtin_ia32_psrav16si_mask: x86::avx512_mask_psrav_d
__builtin_ia32_psrav32hi_mask: x86::avx512_mask_psrav32_hi
__builtin_ia32_psrav4si: x86::avx2_psrav_d
__builtin_ia32_psrav4si_mask: x86::avx512_mask_psrav4_si
__builtin_ia32_psrav8di_mask: x86::avx512_mask_psrav_q
__builtin_ia32_psrav8hi_mask: x86::avx512_mask_psrav8_hi
__builtin_ia32_psrav8si: x86::avx2_psrav_d_256
__builtin_ia32_psrav8si_mask: x86::avx512_mask_psrav8_si
__builtin_ia32_psravq128_mask: x86::avx512_mask_psrav_q_128
__builtin_ia32_psravq256_mask: x86::avx512_mask_psrav_q_256
__builtin_ia32_psraw128: x86::sse2_psra_w
__builtin_ia32_psraw128_mask: x86::avx512_mask_psra_w_128
__builtin_ia32_psraw256: x86::avx2_psra_w
__builtin_ia32_psraw256_mask: x86::avx512_mask_psra_w_256
__builtin_ia32_psraw512_mask: x86::avx512_mask_psra_w_512
__builtin_ia32_psrawi128: x86::sse2_psrai_w
__builtin_ia32_psrawi128_mask: x86::avx512_mask_psra_wi_128
__builtin_ia32_psrawi256: x86::avx2_psrai_w
__builtin_ia32_psrawi256_mask: x86::avx512_mask_psra_wi_256
__builtin_ia32_psrawi512_mask: x86::avx512_mask_psra_wi_512
__builtin_ia32_psrld128: x86::sse2_psrl_d
__builtin_ia32_psrld128_mask: x86::avx512_mask_psrl_d_128
__builtin_ia32_psrld256: x86::avx2_psrl_d
__builtin_ia32_psrld256_mask: x86::avx512_mask_psrl_d_256
__builtin_ia32_psrld512_mask: x86::avx512_mask_psrl_d
__builtin_ia32_psrldi128: x86::sse2_psrli_d
__builtin_ia32_psrldi128_mask: x86::avx512_mask_psrl_di_128
__builtin_ia32_psrldi256: x86::avx2_psrli_d
__builtin_ia32_psrldi256_mask: x86::avx512_mask_psrl_di_256
__builtin_ia32_psrldi512_mask: x86::avx512_mask_psrl_di_512
__builtin_ia32_psrlq128: x86::sse2_psrl_q
__builtin_ia32_psrlq128_mask: x86::avx512_mask_psrl_q_128
__builtin_ia32_psrlq256: x86::avx2_psrl_q
__builtin_ia32_psrlq256_mask: x86::avx512_mask_psrl_q_256
__builtin_ia32_psrlq512_mask: x86::avx512_mask_psrl_q
__builtin_ia32_psrlqi128: x86::sse2_psrli_q
__builtin_ia32_psrlqi128_mask: x86::avx512_mask_psrl_qi_128
__builtin_ia32_psrlqi256: x86::avx2_psrli_q
__builtin_ia32_psrlqi256_mask: x86::avx512_mask_psrl_qi_256
__builtin_ia32_psrlqi512_mask: x86::avx512_mask_psrl_qi_512
__builtin_ia32_psrlv16hi_mask: x86::avx512_mask_psrlv16_hi
__builtin_ia32_psrlv16si_mask: x86::avx512_mask_psrlv_d
__builtin_ia32_psrlv2di: x86::avx2_psrlv_q
__builtin_ia32_psrlv2di_mask: x86::avx512_mask_psrlv2_di
__builtin_ia32_psrlv32hi_mask: x86::avx512_mask_psrlv32hi
__builtin_ia32_psrlv4di: x86::avx2_psrlv_q_256
__builtin_ia32_psrlv4di_mask: x86::avx512_mask_psrlv4_di
__builtin_ia32_psrlv4si: x86::avx2_psrlv_d
__builtin_ia32_psrlv4si_mask: x86::avx512_mask_psrlv4_si
__builtin_ia32_psrlv8di_mask: x86::avx512_mask_psrlv_q
__builtin_ia32_psrlv8hi_mask: x86::avx512_mask_psrlv8_hi
__builtin_ia32_psrlv8si: x86::avx2_psrlv_d_256
__builtin_ia32_psrlv8si_mask: x86::avx512_mask_psrlv8_si
__builtin_ia32_psrlw128: x86::sse2_psrl_w
__builtin_ia32_psrlw128_mask: x86::avx512_mask_psrl_w_128
__builtin_ia32_psrlw256: x86::avx2_psrl_w
__builtin_ia32_psrlw256_mask: x86::avx512_mask_psrl_w_256
__builtin_ia32_psrlw512_mask: x86::avx512_mask_psrl_w_512
__builtin_ia32_psrlwi128: x86::sse2_psrli_w
__builtin_ia32_psrlwi128_mask: x86::avx512_mask_psrl_wi_128
__builtin_ia32_psrlwi256: x86::avx2_psrli_w
__builtin_ia32_psrlwi256_mask: x86::avx512_mask_psrl_wi_256
__builtin_ia32_psrlwi512_mask: x86::avx512_mask_psrl_wi_512
__builtin_ia32_psubb128_mask: x86::avx512_mask_psub_b_128
__builtin_ia32_psubb256_mask: x86::avx512_mask_psub_b_256
__builtin_ia32_psubb512_mask: x86::avx512_mask_psub_b_512
__builtin_ia32_psubd128_mask: x86::avx512_mask_psub_d_128
__builtin_ia32_psubd256_mask: x86::avx512_mask_psub_d_256
__builtin_ia32_psubd512_mask: x86::avx512_mask_psub_d_512
__builtin_ia32_psubq128_mask: x86::avx512_mask_psub_q_128
__builtin_ia32_psubq256_mask: x86::avx512_mask_psub_q_256
__builtin_ia32_psubq512_mask: x86::avx512_mask_psub_q_512
__builtin_ia32_psubsb128: x86::sse2_psubs_b
__builtin_ia32_psubsb128_mask: x86::avx512_mask_psubs_b_128
__builtin_ia32_psubsb256: x86::avx2_psubs_b
__builtin_ia32_psubsb256_mask: x86::avx512_mask_psubs_b_256
__builtin_ia32_psubsb512_mask: x86::avx512_mask_psubs_b_512
__builtin_ia32_psubsw128: x86::sse2_psubs_w
__builtin_ia32_psubsw128_mask: x86::avx512_mask_psubs_w_128
__builtin_ia32_psubsw256: x86::avx2_psubs_w
__builtin_ia32_psubsw256_mask: x86::avx512_mask_psubs_w_256
__builtin_ia32_psubsw512_mask: x86::avx512_mask_psubs_w_512
__builtin_ia32_psubusb128: x86::sse2_psubus_b
__builtin_ia32_psubusb128_mask: x86::avx512_mask_psubus_b_128
__builtin_ia32_psubusb256: x86::avx2_psubus_b
__builtin_ia32_psubusb256_mask: x86::avx512_mask_psubus_b_256
__builtin_ia32_psubusb512_mask: x86::avx512_mask_psubus_b_512
__builtin_ia32_psubusw128: x86::sse2_psubus_w
__builtin_ia32_psubusw128_mask: x86::avx512_mask_psubus_w_128
__builtin_ia32_psubusw256: x86::avx2_psubus_w
__builtin_ia32_psubusw256_mask: x86::avx512_mask_psubus_w_256
__builtin_ia32_psubusw512_mask: x86::avx512_mask_psubus_w_512
__builtin_ia32_psubw128_mask: x86::avx512_mask_psub_w_128
__builtin_ia32_psubw256_mask: x86::avx512_mask_psub_w_256
__builtin_ia32_psubw512_mask: x86::avx512_mask_psub_w_512
__builtin_ia32_pternlogd128_mask: x86::avx512_mask_pternlog_d_128
__builtin_ia32_pternlogd128_maskz: x86::avx512_maskz_pternlog_d_128
__builtin_ia32_pternlogd256_mask: x86::avx512_mask_pternlog_d_256
__builtin_ia32_pternlogd256_maskz: x86::avx512_maskz_pternlog_d_256
__builtin_ia32_pternlogd512_mask: x86::avx512_mask_pternlog_d_512
__builtin_ia32_pternlogd512_maskz: x86::avx512_maskz_pternlog_d_512
__builtin_ia32_pternlogq128_mask: x86::avx512_mask_pternlog_q_128
__builtin_ia32_pternlogq128_maskz: x86::avx512_maskz_pternlog_q_128
__builtin_ia32_pternlogq256_mask: x86::avx512_mask_pternlog_q_256
__builtin_ia32_pternlogq256_maskz: x86::avx512_maskz_pternlog_q_256
__builtin_ia32_pternlogq512_mask: x86::avx512_mask_pternlog_q_512
__builtin_ia32_pternlogq512_maskz: x86::avx512_maskz_pternlog_q_512
__builtin_ia32_ptestc128: x86::sse41_ptestc
__builtin_ia32_ptestc256: x86::avx_ptestc_256
__builtin_ia32_ptestmb128: x86::avx512_ptestm_b_128
__builtin_ia32_ptestmb256: x86::avx512_ptestm_b_256
__builtin_ia32_ptestmb512: x86::avx512_ptestm_b_512
__builtin_ia32_ptestmd128: x86::avx512_ptestm_d_128
__builtin_ia32_ptestmd256: x86::avx512_ptestm_d_256
__builtin_ia32_ptestmd512: x86::avx512_ptestm_d_512
__builtin_ia32_ptestmq128: x86::avx512_ptestm_q_128
__builtin_ia32_ptestmq256: x86::avx512_ptestm_q_256
__builtin_ia32_ptestmq512: x86::avx512_ptestm_q_512
__builtin_ia32_ptestmw128: x86::avx512_ptestm_w_128
__builtin_ia32_ptestmw256: x86::avx512_ptestm_w_256
__builtin_ia32_ptestmw512: x86::avx512_ptestm_w_512
__builtin_ia32_ptestnmb128: x86::avx512_ptestnm_b_128
__builtin_ia32_ptestnmb256: x86::avx512_ptestnm_b_256
__builtin_ia32_ptestnmb512: x86::avx512_ptestnm_b_512
__builtin_ia32_ptestnmd128: x86::avx512_ptestnm_d_128
__builtin_ia32_ptestnmd256: x86::avx512_ptestnm_d_256
__builtin_ia32_ptestnmd512: x86::avx512_ptestnm_d_512
__builtin_ia32_ptestnmq128: x86::avx512_ptestnm_q_128
__builtin_ia32_ptestnmq256: x86::avx512_ptestnm_q_256
__builtin_ia32_ptestnmq512: x86::avx512_ptestnm_q_512
__builtin_ia32_ptestnmw128: x86::avx512_ptestnm_w_128
__builtin_ia32_ptestnmw256: x86::avx512_ptestnm_w_256
__builtin_ia32_ptestnmw512: x86::avx512_ptestnm_w_512
__builtin_ia32_ptestnzc128: x86::sse41_ptestnzc
__builtin_ia32_ptestnzc256: x86::avx_ptestnzc_256
__builtin_ia32_ptestz128: x86::sse41_ptestz
__builtin_ia32_ptestz256: x86::avx_ptestz_256
__builtin_ia32_rangepd128_mask: x86::avx512_mask_range_pd_128
__builtin_ia32_rangepd256_mask: x86::avx512_mask_range_pd_256
__builtin_ia32_rangepd512_mask: x86::avx512_mask_range_pd_512
__builtin_ia32_rangeps128_mask: x86::avx512_mask_range_ps_128
__builtin_ia32_rangeps256_mask: x86::avx512_mask_range_ps_256
__builtin_ia32_rangeps512_mask: x86::avx512_mask_range_ps_512
__builtin_ia32_rangesd128_round_mask: x86::avx512_mask_range_sd
__builtin_ia32_rangess128_round_mask: x86::avx512_mask_range_ss
__builtin_ia32_rcp14pd128_mask: x86::avx512_rcp14_pd_128
__builtin_ia32_rcp14pd256_mask: x86::avx512_rcp14_pd_256
__builtin_ia32_rcp14pd512_mask: x86::avx512_rcp14_pd_512
__builtin_ia32_rcp14ps128_mask: x86::avx512_rcp14_ps_128
__builtin_ia32_rcp14ps256_mask: x86::avx512_rcp14_ps_256
__builtin_ia32_rcp14ps512_mask: x86::avx512_rcp14_ps_512
__builtin_ia32_rcp14sd_mask: x86::avx512_rcp14_sd
__builtin_ia32_rcp14ss_mask: x86::avx512_rcp14_ss
__builtin_ia32_rcp28pd_mask: x86::avx512_rcp28_pd
__builtin_ia32_rcp28ps_mask: x86::avx512_rcp28_ps
__builtin_ia32_rcp28sd_round_mask: x86::avx512_rcp28_sd
__builtin_ia32_rcp28ss_round_mask: x86::avx512_rcp28_ss
__builtin_ia32_rcpps: x86::sse_rcp_ps
__builtin_ia32_rcpps256: x86::avx_rcp_ps_256
__builtin_ia32_rcpss: x86::sse_rcp_ss
__builtin_ia32_rdfsbase32: x86::rdfsbase_32
__builtin_ia32_rdfsbase64: x86::rdfsbase_64
__builtin_ia32_rdgsbase32: x86::rdgsbase_32
__builtin_ia32_rdgsbase64: x86::rdgsbase_64
__builtin_ia32_rdpkru: x86::rdpkru
__builtin_ia32_rdpmc: x86::rdpmc
__builtin_ia32_rdtsc: x86::rdtsc
__builtin_ia32_rdtscp: x86::rdtscp
__builtin_ia32_readeflags_u32: x86::flags_read_u32
__builtin_ia32_readeflags_u64: x86::flags_read_u64
__builtin_ia32_reducepd128_mask: x86::avx512_mask_reduce_pd_128
__builtin_ia32_reducepd256_mask: x86::avx512_mask_reduce_pd_256
__builtin_ia32_reducepd512_mask: x86::avx512_mask_reduce_pd_512
__builtin_ia32_reduceps128_mask: x86::avx512_mask_reduce_ps_128
__builtin_ia32_reduceps256_mask: x86::avx512_mask_reduce_ps_256
__builtin_ia32_reduceps512_mask: x86::avx512_mask_reduce_ps_512
__builtin_ia32_reducesd_mask: x86::avx512_mask_reduce_sd
__builtin_ia32_reducess_mask: x86::avx512_mask_reduce_ss
__builtin_ia32_rndscalepd_128_mask: x86::avx512_mask_rndscale_pd_128
__builtin_ia32_rndscalepd_256_mask: x86::avx512_mask_rndscale_pd_256
__builtin_ia32_rndscalepd_mask: x86::avx512_mask_rndscale_pd_512
__builtin_ia32_rndscaleps_128_mask: x86::avx512_mask_rndscale_ps_128
__builtin_ia32_rndscaleps_256_mask: x86::avx512_mask_rndscale_ps_256
__builtin_ia32_rndscaleps_mask: x86::avx512_mask_rndscale_ps_512
__builtin_ia32_rndscalesd_round_mask: x86::avx512_mask_rndscale_sd
__builtin_ia32_rndscaless_round_mask: x86::avx512_mask_rndscale_ss
__builtin_ia32_roundpd: x86::sse41_round_pd
__builtin_ia32_roundpd256: x86::avx_round_pd_256
__builtin_ia32_roundps: x86::sse41_round_ps
__builtin_ia32_roundps256: x86::avx_round_ps_256
__builtin_ia32_roundsd: x86::sse41_round_sd
__builtin_ia32_roundss: x86::sse41_round_ss
__builtin_ia32_rsqrt14pd128_mask: x86::avx512_rsqrt14_pd_128
__builtin_ia32_rsqrt14pd256_mask: x86::avx512_rsqrt14_pd_256
__builtin_ia32_rsqrt14pd512_mask: x86::avx512_rsqrt14_pd_512
__builtin_ia32_rsqrt14ps128_mask: x86::avx512_rsqrt14_ps_128
__builtin_ia32_rsqrt14ps256_mask: x86::avx512_rsqrt14_ps_256
__builtin_ia32_rsqrt14ps512_mask: x86::avx512_rsqrt14_ps_512
__builtin_ia32_rsqrt14sd_mask: x86::avx512_rsqrt14_sd
__builtin_ia32_rsqrt14ss_mask: x86::avx512_rsqrt14_ss
__builtin_ia32_rsqrt28pd_mask: x86::avx512_rsqrt28_pd
__builtin_ia32_rsqrt28ps_mask: x86::avx512_rsqrt28_ps
__builtin_ia32_rsqrt28sd_round_mask: x86::avx512_rsqrt28_sd
__builtin_ia32_rsqrt28ss_round_mask: x86::avx512_rsqrt28_ss
__builtin_ia32_rsqrtps: x86::sse_rsqrt_ps
__builtin_ia32_rsqrtps256: x86::avx_rsqrt_ps_256
__builtin_ia32_rsqrtss: x86::sse_rsqrt_ss
__builtin_ia32_scalefpd128_mask: x86::avx512_mask_scalef_pd_128
__builtin_ia32_scalefpd256_mask: x86::avx512_mask_scalef_pd_256
__builtin_ia32_scalefpd512_mask: x86::avx512_mask_scalef_pd_512
__builtin_ia32_scalefps128_mask: x86::avx512_mask_scalef_ps_128
__builtin_ia32_scalefps256_mask: x86::avx512_mask_scalef_ps_256
__builtin_ia32_scalefps512_mask: x86::avx512_mask_scalef_ps_512
__builtin_ia32_scalefsd_round_mask: x86::avx512_mask_scalef_sd
__builtin_ia32_scalefss_round_mask: x86::avx512_mask_scalef_ss
__builtin_ia32_scatterdiv16sf: x86::avx512_scatter_qps_512
__builtin_ia32_scatterdiv16si: x86::avx512_scatter_qpi_512
__builtin_ia32_scatterdiv2df: x86::avx512_scatterdiv2_df
__builtin_ia32_scatterdiv2di: x86::avx512_scatterdiv2_di
__builtin_ia32_scatterdiv4df: x86::avx512_scatterdiv4_df
__builtin_ia32_scatterdiv4di: x86::avx512_scatterdiv4_di
__builtin_ia32_scatterdiv4sf: x86::avx512_scatterdiv4_sf
__builtin_ia32_scatterdiv4si: x86::avx512_scatterdiv4_si
__builtin_ia32_scatterdiv8df: x86::avx512_scatter_qpd_512
__builtin_ia32_scatterdiv8di: x86::avx512_scatter_qpq_512
__builtin_ia32_scatterdiv8sf: x86::avx512_scatterdiv8_sf
__builtin_ia32_scatterdiv8si: x86::avx512_scatterdiv8_si
__builtin_ia32_scatterpfdpd: x86::avx512_scatterpf_dpd_512
__builtin_ia32_scatterpfdps: x86::avx512_scatterpf_dps_512
__builtin_ia32_scatterpfqpd: x86::avx512_scatterpf_qpd_512
__builtin_ia32_scatterpfqps: x86::avx512_scatterpf_qps_512
__builtin_ia32_scattersiv16sf: x86::avx512_scatter_dps_512
__builtin_ia32_scattersiv16si: x86::avx512_scatter_dpi_512
__builtin_ia32_scattersiv2df: x86::avx512_scattersiv2_df
__builtin_ia32_scattersiv2di: x86::avx512_scattersiv2_di
__builtin_ia32_scattersiv4df: x86::avx512_scattersiv4_df
__builtin_ia32_scattersiv4di: x86::avx512_scattersiv4_di
__builtin_ia32_scattersiv4sf: x86::avx512_scattersiv4_sf
__builtin_ia32_scattersiv4si: x86::avx512_scattersiv4_si
__builtin_ia32_scattersiv8df: x86::avx512_scatter_dpd_512
__builtin_ia32_scattersiv8di: x86::avx512_scatter_dpq_512
__builtin_ia32_scattersiv8sf: x86::avx512_scattersiv8_sf
__builtin_ia32_scattersiv8si: x86::avx512_scattersiv8_si
__builtin_ia32_sfence: x86::sse_sfence
__builtin_ia32_sha1msg1: x86::sha1msg1
__builtin_ia32_sha1msg2: x86::sha1msg2
__builtin_ia32_sha1nexte: x86::sha1nexte
__builtin_ia32_sha1rnds4: x86::sha1rnds4
__builtin_ia32_sha256msg1: x86::sha256msg1
__builtin_ia32_sha256msg2: x86::sha256msg2
__builtin_ia32_sha256rnds2: x86::sha256rnds2
__builtin_ia32_shuf_f32x4_256_mask: x86::avx512_mask_shuf_f32x4_256
__builtin_ia32_shuf_f32x4_mask: x86::avx512_mask_shuf_f32x4
__builtin_ia32_shuf_f64x2_256_mask: x86::avx512_mask_shuf_f64x2_256
__builtin_ia32_shuf_f64x2_mask: x86::avx512_mask_shuf_f64x2
__builtin_ia32_shuf_i32x4_256_mask: x86::avx512_mask_shuf_i32x4_256
__builtin_ia32_shuf_i32x4_mask: x86::avx512_mask_shuf_i32x4
__builtin_ia32_shuf_i64x2_256_mask: x86::avx512_mask_shuf_i64x2_256
__builtin_ia32_shuf_i64x2_mask: x86::avx512_mask_shuf_i64x2
__builtin_ia32_shufpd128_mask: x86::avx512_mask_shuf_pd_128
__builtin_ia32_shufpd256_mask: x86::avx512_mask_shuf_pd_256
__builtin_ia32_shufpd512_mask: x86::avx512_mask_shuf_pd_512
__builtin_ia32_shufps128_mask: x86::avx512_mask_shuf_ps_128
__builtin_ia32_shufps256_mask: x86::avx512_mask_shuf_ps_256
__builtin_ia32_shufps512_mask: x86::avx512_mask_shuf_ps_512
__builtin_ia32_sqrtpd: x86::sse2_sqrt_pd
__builtin_ia32_sqrtpd128_mask: x86::avx512_mask_sqrt_pd_128
__builtin_ia32_sqrtpd256: x86::avx_sqrt_pd_256
__builtin_ia32_sqrtpd256_mask: x86::avx512_mask_sqrt_pd_256
__builtin_ia32_sqrtpd512_mask: x86::avx512_mask_sqrt_pd_512
__builtin_ia32_sqrtps: x86::sse_sqrt_ps
__builtin_ia32_sqrtps128_mask: x86::avx512_mask_sqrt_ps_128
__builtin_ia32_sqrtps256: x86::avx_sqrt_ps_256
__builtin_ia32_sqrtps256_mask: x86::avx512_mask_sqrt_ps_256
__builtin_ia32_sqrtps512_mask: x86::avx512_mask_sqrt_ps_512
__builtin_ia32_sqrtsd: x86::sse2_sqrt_sd
__builtin_ia32_sqrtsd_round_mask: x86::avx512_mask_sqrt_sd
__builtin_ia32_sqrtss: x86::sse_sqrt_ss
__builtin_ia32_sqrtss_round_mask: x86::avx512_mask_sqrt_ss
__builtin_ia32_storess_mask: x86::avx512_mask_store_ss
__builtin_ia32_subborrow_u32: x86::subborrow_u32
__builtin_ia32_subborrow_u64: x86::subborrow_u64
__builtin_ia32_subpd128_mask: x86::avx512_mask_sub_pd_128
__builtin_ia32_subpd256_mask: x86::avx512_mask_sub_pd_256
__builtin_ia32_subpd512_mask: x86::avx512_mask_sub_pd_512
__builtin_ia32_subps128_mask: x86::avx512_mask_sub_ps_128
__builtin_ia32_subps256_mask: x86::avx512_mask_sub_ps_256
__builtin_ia32_subps512_mask: x86::avx512_mask_sub_ps_512
__builtin_ia32_subsd_round_mask: x86::avx512_mask_sub_sd_round
__builtin_ia32_subss_round_mask: x86::avx512_mask_sub_ss_round
__builtin_ia32_ucomieq: x86::sse_ucomieq_ss
__builtin_ia32_ucomige: x86::sse_ucomige_ss
__builtin_ia32_ucomigt: x86::sse_ucomigt_ss
__builtin_ia32_ucomile: x86::sse_ucomile_ss
__builtin_ia32_ucomilt: x86::sse_ucomilt_ss
__builtin_ia32_ucomineq: x86::sse_ucomineq_ss
__builtin_ia32_ucomisdeq: x86::sse2_ucomieq_sd
__builtin_ia32_ucomisdge: x86::sse2_ucomige_sd
__builtin_ia32_ucomisdgt: x86::sse2_ucomigt_sd
__builtin_ia32_ucomisdle: x86::sse2_ucomile_sd
__builtin_ia32_ucomisdlt: x86::sse2_ucomilt_sd
__builtin_ia32_ucomisdneq: x86::sse2_ucomineq_sd
__builtin_ia32_vbroadcastf128_pd256: x86::avx_vbroadcastf128_pd_256
__builtin_ia32_vbroadcastf128_ps256: x86::avx_vbroadcastf128_ps_256
__builtin_ia32_vbroadcastsd512: x86::avx512_vbroadcast_sd_512
__builtin_ia32_vbroadcastss512: x86::avx512_vbroadcast_ss_512
__builtin_ia32_vcomisd: x86::avx512_vcomi_sd
__builtin_ia32_vcomiss: x86::avx512_vcomi_ss
__builtin_ia32_vcvtph2ps: x86::vcvtph2ps_128
__builtin_ia32_vcvtph2ps256: x86::vcvtph2ps_256
__builtin_ia32_vcvtph2ps256_mask: x86::avx512_mask_vcvtph2ps_256
__builtin_ia32_vcvtph2ps512_mask: x86::avx512_mask_vcvtph2ps_512
__builtin_ia32_vcvtph2ps_mask: x86::avx512_mask_vcvtph2ps_128
__builtin_ia32_vcvtps2ph: x86::vcvtps2ph_128
__builtin_ia32_vcvtps2ph256: x86::vcvtps2ph_256
__builtin_ia32_vcvtps2ph256_mask: x86::avx512_mask_vcvtps2ph_256
__builtin_ia32_vcvtps2ph512_mask: x86::avx512_mask_vcvtps2ph_512
__builtin_ia32_vcvtps2ph_mask: x86::avx512_mask_vcvtps2ph_128
__builtin_ia32_vcvtsd2si32: x86::avx512_vcvtsd2si32
__builtin_ia32_vcvtsd2si64: x86::avx512_vcvtsd2si64
__builtin_ia32_vcvtsd2usi32: x86::avx512_vcvtsd2usi32
__builtin_ia32_vcvtsd2usi64: x86::avx512_vcvtsd2usi64
__builtin_ia32_vcvtss2si32: x86::avx512_vcvtss2si32
__builtin_ia32_vcvtss2si64: x86::avx512_vcvtss2si64
__builtin_ia32_vcvtss2usi32: x86::avx512_vcvtss2usi32
__builtin_ia32_vcvtss2usi64: x86::avx512_vcvtss2usi64
__builtin_ia32_vcvttsd2si32: x86::avx512_cvttsd2si
__builtin_ia32_vcvttsd2si64: x86::avx512_cvttsd2si64
__builtin_ia32_vcvttsd2usi32: x86::avx512_cvttsd2usi
__builtin_ia32_vcvttsd2usi64: x86::avx512_cvttsd2usi64
__builtin_ia32_vcvttss2si32: x86::avx512_cvttss2si
__builtin_ia32_vcvttss2si64: x86::avx512_cvttss2si64
__builtin_ia32_vcvttss2usi32: x86::avx512_cvttss2usi
__builtin_ia32_vcvttss2usi64: x86::avx512_cvttss2usi64
__builtin_ia32_vfmaddpd: x86::fma_vfmadd_pd
__builtin_ia32_vfmaddpd128_mask: x86::avx512_mask_vfmadd_pd_128
__builtin_ia32_vfmaddpd128_mask3: x86::avx512_mask3_vfmadd_pd_128
__builtin_ia32_vfmaddpd128_maskz: x86::avx512_maskz_vfmadd_pd_128
__builtin_ia32_vfmaddpd256: x86::fma_vfmadd_pd_256
__builtin_ia32_vfmaddpd256_mask: x86::avx512_mask_vfmadd_pd_256
__builtin_ia32_vfmaddpd256_mask3: x86::avx512_mask3_vfmadd_pd_256
__builtin_ia32_vfmaddpd256_maskz: x86::avx512_maskz_vfmadd_pd_256
__builtin_ia32_vfmaddpd512_mask: x86::avx512_mask_vfmadd_pd_512
__builtin_ia32_vfmaddpd512_mask3: x86::avx512_mask3_vfmadd_pd_512
__builtin_ia32_vfmaddpd512_maskz: x86::avx512_maskz_vfmadd_pd_512
__builtin_ia32_vfmaddps: x86::fma_vfmadd_ps
__builtin_ia32_vfmaddps128_mask: x86::avx512_mask_vfmadd_ps_128
__builtin_ia32_vfmaddps128_mask3: x86::avx512_mask3_vfmadd_ps_128
__builtin_ia32_vfmaddps128_maskz: x86::avx512_maskz_vfmadd_ps_128
__builtin_ia32_vfmaddps256: x86::fma_vfmadd_ps_256
__builtin_ia32_vfmaddps256_mask: x86::avx512_mask_vfmadd_ps_256
__builtin_ia32_vfmaddps256_mask3: x86::avx512_mask3_vfmadd_ps_256
__builtin_ia32_vfmaddps256_maskz: x86::avx512_maskz_vfmadd_ps_256
__builtin_ia32_vfmaddps512_mask: x86::avx512_mask_vfmadd_ps_512
__builtin_ia32_vfmaddps512_mask3: x86::avx512_mask3_vfmadd_ps_512
__builtin_ia32_vfmaddps512_maskz: x86::avx512_maskz_vfmadd_ps_512
__builtin_ia32_vfmaddsd: x86::fma_vfmadd_sd
__builtin_ia32_vfmaddsd3_mask: x86::avx512_mask_vfmadd_sd
__builtin_ia32_vfmaddsd3_mask3: x86::avx512_mask3_vfmadd_sd
__builtin_ia32_vfmaddsd3_maskz: x86::avx512_maskz_vfmadd_sd
__builtin_ia32_vfmaddss: x86::fma_vfmadd_ss
__builtin_ia32_vfmaddss3_mask: x86::avx512_mask_vfmadd_ss
__builtin_ia32_vfmaddss3_mask3: x86::avx512_mask3_vfmadd_ss
__builtin_ia32_vfmaddss3_maskz: x86::avx512_maskz_vfmadd_ss
__builtin_ia32_vfmaddsubpd: x86::fma_vfmaddsub_pd
__builtin_ia32_vfmaddsubpd128_mask: x86::avx512_mask_vfmaddsub_pd_128
__builtin_ia32_vfmaddsubpd128_mask3: x86::avx512_mask3_vfmaddsub_pd_128
__builtin_ia32_vfmaddsubpd128_maskz: x86::avx512_maskz_vfmaddsub_pd_128
__builtin_ia32_vfmaddsubpd256: x86::fma_vfmaddsub_pd_256
__builtin_ia32_vfmaddsubpd256_mask: x86::avx512_mask_vfmaddsub_pd_256
__builtin_ia32_vfmaddsubpd256_mask3: x86::avx512_mask3_vfmaddsub_pd_256
__builtin_ia32_vfmaddsubpd256_maskz: x86::avx512_maskz_vfmaddsub_pd_256
__builtin_ia32_vfmaddsubpd512_mask: x86::avx512_mask_vfmaddsub_pd_512
__builtin_ia32_vfmaddsubpd512_mask3: x86::avx512_mask3_vfmaddsub_pd_512
__builtin_ia32_vfmaddsubpd512_maskz: x86::avx512_maskz_vfmaddsub_pd_512
__builtin_ia32_vfmaddsubps: x86::fma_vfmaddsub_ps
__builtin_ia32_vfmaddsubps128_mask: x86::avx512_mask_vfmaddsub_ps_128
__builtin_ia32_vfmaddsubps128_mask3: x86::avx512_mask3_vfmaddsub_ps_128
__builtin_ia32_vfmaddsubps128_maskz: x86::avx512_maskz_vfmaddsub_ps_128
__builtin_ia32_vfmaddsubps256: x86::fma_vfmaddsub_ps_256
__builtin_ia32_vfmaddsubps256_mask: x86::avx512_mask_vfmaddsub_ps_256
__builtin_ia32_vfmaddsubps256_mask3: x86::avx512_mask3_vfmaddsub_ps_256
__builtin_ia32_vfmaddsubps256_maskz: x86::avx512_maskz_vfmaddsub_ps_256
__builtin_ia32_vfmaddsubps512_mask: x86::avx512_mask_vfmaddsub_ps_512
__builtin_ia32_vfmaddsubps512_mask3: x86::avx512_mask3_vfmaddsub_ps_512
__builtin_ia32_vfmaddsubps512_maskz: x86::avx512_maskz_vfmaddsub_ps_512
__builtin_ia32_vfmsubaddpd: x86::fma_vfmsubadd_pd
__builtin_ia32_vfmsubaddpd128_mask3: x86::avx512_mask3_vfmsubadd_pd_128
__builtin_ia32_vfmsubaddpd256: x86::fma_vfmsubadd_pd_256
__builtin_ia32_vfmsubaddpd256_mask3: x86::avx512_mask3_vfmsubadd_pd_256
__builtin_ia32_vfmsubaddpd512_mask3: x86::avx512_mask3_vfmsubadd_pd_512
__builtin_ia32_vfmsubaddps: x86::fma_vfmsubadd_ps
__builtin_ia32_vfmsubaddps128_mask3: x86::avx512_mask3_vfmsubadd_ps_128
__builtin_ia32_vfmsubaddps256: x86::fma_vfmsubadd_ps_256
__builtin_ia32_vfmsubaddps256_mask3: x86::avx512_mask3_vfmsubadd_ps_256
__builtin_ia32_vfmsubaddps512_mask3: x86::avx512_mask3_vfmsubadd_ps_512
__builtin_ia32_vfmsubpd: x86::fma_vfmsub_pd
__builtin_ia32_vfmsubpd128_mask3: x86::avx512_mask3_vfmsub_pd_128
__builtin_ia32_vfmsubpd256: x86::fma_vfmsub_pd_256
__builtin_ia32_vfmsubpd256_mask3: x86::avx512_mask3_vfmsub_pd_256
__builtin_ia32_vfmsubpd512_mask3: x86::avx512_mask3_vfmsub_pd_512
__builtin_ia32_vfmsubps: x86::fma_vfmsub_ps
__builtin_ia32_vfmsubps128_mask3: x86::avx512_mask3_vfmsub_ps_128
__builtin_ia32_vfmsubps256: x86::fma_vfmsub_ps_256
__builtin_ia32_vfmsubps256_mask3: x86::avx512_mask3_vfmsub_ps_256
__builtin_ia32_vfmsubps512_mask3: x86::avx512_mask3_vfmsub_ps_512
__builtin_ia32_vfmsubsd: x86::fma_vfmsub_sd
__builtin_ia32_vfmsubss: x86::fma_vfmsub_ss
__builtin_ia32_vfnmaddpd: x86::fma_vfnmadd_pd
__builtin_ia32_vfnmaddpd128_mask: x86::avx512_mask_vfnmadd_pd_128
__builtin_ia32_vfnmaddpd256: x86::fma_vfnmadd_pd_256
__builtin_ia32_vfnmaddpd256_mask: x86::avx512_mask_vfnmadd_pd_256
__builtin_ia32_vfnmaddpd512_mask: x86::avx512_mask_vfnmadd_pd_512
__builtin_ia32_vfnmaddps: x86::fma_vfnmadd_ps
__builtin_ia32_vfnmaddps128_mask: x86::avx512_mask_vfnmadd_ps_128
__builtin_ia32_vfnmaddps256: x86::fma_vfnmadd_ps_256
__builtin_ia32_vfnmaddps256_mask: x86::avx512_mask_vfnmadd_ps_256
__builtin_ia32_vfnmaddps512_mask: x86::avx512_mask_vfnmadd_ps_512
__builtin_ia32_vfnmaddsd: x86::fma_vfnmadd_sd
__builtin_ia32_vfnmaddss: x86::fma_vfnmadd_ss
__builtin_ia32_vfnmsubpd: x86::fma_vfnmsub_pd
__builtin_ia32_vfnmsubpd128_mask: x86::avx512_mask_vfnmsub_pd_128
__builtin_ia32_vfnmsubpd128_mask3: x86::avx512_mask3_vfnmsub_pd_128
__builtin_ia32_vfnmsubpd256: x86::fma_vfnmsub_pd_256
__builtin_ia32_vfnmsubpd256_mask: x86::avx512_mask_vfnmsub_pd_256
__builtin_ia32_vfnmsubpd256_mask3: x86::avx512_mask3_vfnmsub_pd_256
__builtin_ia32_vfnmsubpd512_mask: x86::avx512_mask_vfnmsub_pd_512
__builtin_ia32_vfnmsubpd512_mask3: x86::avx512_mask3_vfnmsub_pd_512
__builtin_ia32_vfnmsubps: x86::fma_vfnmsub_ps
__builtin_ia32_vfnmsubps128_mask: x86::avx512_mask_vfnmsub_ps_128
__builtin_ia32_vfnmsubps128_mask3: x86::avx512_mask3_vfnmsub_ps_128
__builtin_ia32_vfnmsubps256: x86::fma_vfnmsub_ps_256
__builtin_ia32_vfnmsubps256_mask: x86::avx512_mask_vfnmsub_ps_256
__builtin_ia32_vfnmsubps256_mask3: x86::avx512_mask3_vfnmsub_ps_256
__builtin_ia32_vfnmsubps512_mask: x86::avx512_mask_vfnmsub_ps_512
__builtin_ia32_vfnmsubps512_mask3: x86::avx512_mask3_vfnmsub_ps_512
__builtin_ia32_vfnmsubsd: x86::fma_vfnmsub_sd
__builtin_ia32_vfnmsubss: x86::fma_vfnmsub_ss
__builtin_ia32_vfrczpd: x86::xop_vfrcz_pd
__builtin_ia32_vfrczpd256: x86::xop_vfrcz_pd_256
__builtin_ia32_vfrczps: x86::xop_vfrcz_ps
__builtin_ia32_vfrczps256: x86::xop_vfrcz_ps_256
__builtin_ia32_vfrczsd: x86::xop_vfrcz_sd
__builtin_ia32_vfrczss: x86::xop_vfrcz_ss
__builtin_ia32_vpcmov: x86::xop_vpcmov
__builtin_ia32_vpcmov_256: x86::xop_vpcmov_256
__builtin_ia32_vpcomb: x86::xop_vpcomb
__builtin_ia32_vpcomd: x86::xop_vpcomd
__builtin_ia32_vpcomq: x86::xop_vpcomq
__builtin_ia32_vpcomub: x86::xop_vpcomub
__builtin_ia32_vpcomud: x86::xop_vpcomud
__builtin_ia32_vpcomuq: x86::xop_vpcomuq
__builtin_ia32_vpcomuw: x86::xop_vpcomuw
__builtin_ia32_vpcomw: x86::xop_vpcomw
__builtin_ia32_vpconflictdi_128_mask: x86::avx512_mask_conflict_q_128
__builtin_ia32_vpconflictdi_256_mask: x86::avx512_mask_conflict_q_256
__builtin_ia32_vpconflictdi_512_mask: x86::avx512_mask_conflict_q_512
__builtin_ia32_vpconflictsi_128_mask: x86::avx512_mask_conflict_d_128
__builtin_ia32_vpconflictsi_256_mask: x86::avx512_mask_conflict_d_256
__builtin_ia32_vpconflictsi_512_mask: x86::avx512_mask_conflict_d_512
__builtin_ia32_vperm2f128_pd256: x86::avx_vperm2f128_pd_256
__builtin_ia32_vperm2f128_ps256: x86::avx_vperm2f128_ps_256
__builtin_ia32_vperm2f128_si256: x86::avx_vperm2f128_si_256
__builtin_ia32_vpermi2vard128_mask: x86::avx512_mask_vpermi2var_d_128
__builtin_ia32_vpermi2vard256_mask: x86::avx512_mask_vpermi2var_d_256
__builtin_ia32_vpermi2vard512_mask: x86::avx512_mask_vpermi2var_d_512
__builtin_ia32_vpermi2varhi128_mask: x86::avx512_mask_vpermi2var_hi_128
__builtin_ia32_vpermi2varhi256_mask: x86::avx512_mask_vpermi2var_hi_256
__builtin_ia32_vpermi2varhi512_mask: x86::avx512_mask_vpermi2var_hi_512
__builtin_ia32_vpermi2varpd128_mask: x86::avx512_mask_vpermi2var_pd_128
__builtin_ia32_vpermi2varpd256_mask: x86::avx512_mask_vpermi2var_pd_256
__builtin_ia32_vpermi2varpd512_mask: x86::avx512_mask_vpermi2var_pd_512
__builtin_ia32_vpermi2varps128_mask: x86::avx512_mask_vpermi2var_ps_128
__builtin_ia32_vpermi2varps256_mask: x86::avx512_mask_vpermi2var_ps_256
__builtin_ia32_vpermi2varps512_mask: x86::avx512_mask_vpermi2var_ps_512
__builtin_ia32_vpermi2varq128_mask: x86::avx512_mask_vpermi2var_q_128
__builtin_ia32_vpermi2varq256_mask: x86::avx512_mask_vpermi2var_q_256
__builtin_ia32_vpermi2varq512_mask: x86::avx512_mask_vpermi2var_q_512
__builtin_ia32_vpermi2varqi128_mask: x86::avx512_mask_vpermi2var_qi_128
__builtin_ia32_vpermi2varqi256_mask: x86::avx512_mask_vpermi2var_qi_256
__builtin_ia32_vpermi2varqi512_mask: x86::avx512_mask_vpermi2var_qi_512
__builtin_ia32_vpermil2pd: x86::xop_vpermil2pd
__builtin_ia32_vpermil2pd256: x86::xop_vpermil2pd_256
__builtin_ia32_vpermil2ps: x86::xop_vpermil2ps
__builtin_ia32_vpermil2ps256: x86::xop_vpermil2ps_256
__builtin_ia32_vpermilvarpd: x86::avx_vpermilvar_pd
__builtin_ia32_vpermilvarpd256: x86::avx_vpermilvar_pd_256
__builtin_ia32_vpermilvarpd256_mask: x86::avx512_mask_vpermilvar_pd_256
__builtin_ia32_vpermilvarpd512_mask: x86::avx512_mask_vpermilvar_pd_512
__builtin_ia32_vpermilvarpd_mask: x86::avx512_mask_vpermilvar_pd_128
__builtin_ia32_vpermilvarps: x86::avx_vpermilvar_ps
__builtin_ia32_vpermilvarps256: x86::avx_vpermilvar_ps_256
__builtin_ia32_vpermilvarps256_mask: x86::avx512_mask_vpermilvar_ps_256
__builtin_ia32_vpermilvarps512_mask: x86::avx512_mask_vpermilvar_ps_512
__builtin_ia32_vpermilvarps_mask: x86::avx512_mask_vpermilvar_ps_128
__builtin_ia32_vpermt2vard128_mask: x86::avx512_mask_vpermt2var_d_128
__builtin_ia32_vpermt2vard128_maskz: x86::avx512_maskz_vpermt2var_d_128
__builtin_ia32_vpermt2vard256_mask: x86::avx512_mask_vpermt2var_d_256
__builtin_ia32_vpermt2vard256_maskz: x86::avx512_maskz_vpermt2var_d_256
__builtin_ia32_vpermt2vard512_mask: x86::avx512_mask_vpermt2var_d_512
__builtin_ia32_vpermt2vard512_maskz: x86::avx512_maskz_vpermt2var_d_512
__builtin_ia32_vpermt2varhi128_mask: x86::avx512_mask_vpermt2var_hi_128
__builtin_ia32_vpermt2varhi128_maskz: x86::avx512_maskz_vpermt2var_hi_128
__builtin_ia32_vpermt2varhi256_mask: x86::avx512_mask_vpermt2var_hi_256
__builtin_ia32_vpermt2varhi256_maskz: x86::avx512_maskz_vpermt2var_hi_256
__builtin_ia32_vpermt2varhi512_mask: x86::avx512_mask_vpermt2var_hi_512
__builtin_ia32_vpermt2varhi512_maskz: x86::avx512_maskz_vpermt2var_hi_512
__builtin_ia32_vpermt2varpd128_mask: x86::avx512_mask_vpermt2var_pd_128
__builtin_ia32_vpermt2varpd128_maskz: x86::avx512_maskz_vpermt2var_pd_128
__builtin_ia32_vpermt2varpd256_mask: x86::avx512_mask_vpermt2var_pd_256
__builtin_ia32_vpermt2varpd256_maskz: x86::avx512_maskz_vpermt2var_pd_256
__builtin_ia32_vpermt2varpd512_mask: x86::avx512_mask_vpermt2var_pd_512
__builtin_ia32_vpermt2varpd512_maskz: x86::avx512_maskz_vpermt2var_pd_512
__builtin_ia32_vpermt2varps128_mask: x86::avx512_mask_vpermt2var_ps_128
__builtin_ia32_vpermt2varps128_maskz: x86::avx512_maskz_vpermt2var_ps_128
__builtin_ia32_vpermt2varps256_mask: x86::avx512_mask_vpermt2var_ps_256
__builtin_ia32_vpermt2varps256_maskz: x86::avx512_maskz_vpermt2var_ps_256
__builtin_ia32_vpermt2varps512_mask: x86::avx512_mask_vpermt2var_ps_512
__builtin_ia32_vpermt2varps512_maskz: x86::avx512_maskz_vpermt2var_ps_512
__builtin_ia32_vpermt2varq128_mask: x86::avx512_mask_vpermt2var_q_128
__builtin_ia32_vpermt2varq128_maskz: x86::avx512_maskz_vpermt2var_q_128
__builtin_ia32_vpermt2varq256_mask: x86::avx512_mask_vpermt2var_q_256
__builtin_ia32_vpermt2varq256_maskz: x86::avx512_maskz_vpermt2var_q_256
__builtin_ia32_vpermt2varq512_mask: x86::avx512_mask_vpermt2var_q_512
__builtin_ia32_vpermt2varq512_maskz: x86::avx512_maskz_vpermt2var_q_512
__builtin_ia32_vpermt2varqi128_mask: x86::avx512_mask_vpermt2var_qi_128
__builtin_ia32_vpermt2varqi128_maskz: x86::avx512_maskz_vpermt2var_qi_128
__builtin_ia32_vpermt2varqi256_mask: x86::avx512_mask_vpermt2var_qi_256
__builtin_ia32_vpermt2varqi256_maskz: x86::avx512_maskz_vpermt2var_qi_256
__builtin_ia32_vpermt2varqi512_mask: x86::avx512_mask_vpermt2var_qi_512
__builtin_ia32_vpermt2varqi512_maskz: x86::avx512_maskz_vpermt2var_qi_512
__builtin_ia32_vphaddbd: x86::xop_vphaddbd
__builtin_ia32_vphaddbq: x86::xop_vphaddbq
__builtin_ia32_vphaddbw: x86::xop_vphaddbw
__builtin_ia32_vphadddq: x86::xop_vphadddq
__builtin_ia32_vphaddubd: x86::xop_vphaddubd
__builtin_ia32_vphaddubq: x86::xop_vphaddubq
__builtin_ia32_vphaddubw: x86::xop_vphaddubw
__builtin_ia32_vphaddudq: x86::xop_vphaddudq
__builtin_ia32_vphadduwd: x86::xop_vphadduwd
__builtin_ia32_vphadduwq: x86::xop_vphadduwq
__builtin_ia32_vphaddwd: x86::xop_vphaddwd
__builtin_ia32_vphaddwq: x86::xop_vphaddwq
__builtin_ia32_vphsubbw: x86::xop_vphsubbw
__builtin_ia32_vphsubdq: x86::xop_vphsubdq
__builtin_ia32_vphsubwd: x86::xop_vphsubwd
__builtin_ia32_vpmacsdd: x86::xop_vpmacsdd
__builtin_ia32_vpmacsdqh: x86::xop_vpmacsdqh
__builtin_ia32_vpmacsdql: x86::xop_vpmacsdql
__builtin_ia32_vpmacssdd: x86::xop_vpmacssdd
__builtin_ia32_vpmacssdqh: x86::xop_vpmacssdqh
__builtin_ia32_vpmacssdql: x86::xop_vpmacssdql
__builtin_ia32_vpmacsswd: x86::xop_vpmacsswd
__builtin_ia32_vpmacssww: x86::xop_vpmacssww
__builtin_ia32_vpmacswd: x86::xop_vpmacswd
__builtin_ia32_vpmacsww: x86::xop_vpmacsww
__builtin_ia32_vpmadcsswd: x86::xop_vpmadcsswd
__builtin_ia32_vpmadcswd: x86::xop_vpmadcswd
__builtin_ia32_vpmadd52huq128_mask: x86::avx512_mask_vpmadd52h_uq_128
__builtin_ia32_vpmadd52huq128_maskz: x86::avx512_maskz_vpmadd52h_uq_128
__builtin_ia32_vpmadd52huq256_mask: x86::avx512_mask_vpmadd52h_uq_256
__builtin_ia32_vpmadd52huq256_maskz: x86::avx512_maskz_vpmadd52h_uq_256
__builtin_ia32_vpmadd52huq512_mask: x86::avx512_mask_vpmadd52h_uq_512
__builtin_ia32_vpmadd52huq512_maskz: x86::avx512_maskz_vpmadd52h_uq_512
__builtin_ia32_vpmadd52luq128_mask: x86::avx512_mask_vpmadd52l_uq_128
__builtin_ia32_vpmadd52luq128_maskz: x86::avx512_maskz_vpmadd52l_uq_128
__builtin_ia32_vpmadd52luq256_mask: x86::avx512_mask_vpmadd52l_uq_256
__builtin_ia32_vpmadd52luq256_maskz: x86::avx512_maskz_vpmadd52l_uq_256
__builtin_ia32_vpmadd52luq512_mask: x86::avx512_mask_vpmadd52l_uq_512
__builtin_ia32_vpmadd52luq512_maskz: x86::avx512_maskz_vpmadd52l_uq_512
__builtin_ia32_vpmultishiftqb128_mask: x86::avx512_mask_pmultishift_qb_128
__builtin_ia32_vpmultishiftqb256_mask: x86::avx512_mask_pmultishift_qb_256
__builtin_ia32_vpmultishiftqb512_mask: x86::avx512_mask_pmultishift_qb_512
__builtin_ia32_vpperm: x86::xop_vpperm
__builtin_ia32_vprotb: x86::xop_vprotb
__builtin_ia32_vprotbi: x86::xop_vprotbi
__builtin_ia32_vprotd: x86::xop_vprotd
__builtin_ia32_vprotdi: x86::xop_vprotdi
__builtin_ia32_vprotq: x86::xop_vprotq
__builtin_ia32_vprotqi: x86::xop_vprotqi
__builtin_ia32_vprotw: x86::xop_vprotw
__builtin_ia32_vprotwi: x86::xop_vprotwi
__builtin_ia32_vpshab: x86::xop_vpshab
__builtin_ia32_vpshad: x86::xop_vpshad
__builtin_ia32_vpshaq: x86::xop_vpshaq
__builtin_ia32_vpshaw: x86::xop_vpshaw
__builtin_ia32_vpshlb: x86::xop_vpshlb
__builtin_ia32_vpshld: x86::xop_vpshld
__builtin_ia32_vpshlq: x86::xop_vpshlq
__builtin_ia32_vpshlw: x86::xop_vpshlw
__builtin_ia32_vtestcpd: x86::avx_vtestc_pd
__builtin_ia32_vtestcpd256: x86::avx_vtestc_pd_256
__builtin_ia32_vtestcps: x86::avx_vtestc_ps
__builtin_ia32_vtestcps256: x86::avx_vtestc_ps_256
__builtin_ia32_vtestnzcpd: x86::avx_vtestnzc_pd
__builtin_ia32_vtestnzcpd256: x86::avx_vtestnzc_pd_256
__builtin_ia32_vtestnzcps: x86::avx_vtestnzc_ps
__builtin_ia32_vtestnzcps256: x86::avx_vtestnzc_ps_256
__builtin_ia32_vtestzpd: x86::avx_vtestz_pd
__builtin_ia32_vtestzpd256: x86::avx_vtestz_pd_256
__builtin_ia32_vtestzps: x86::avx_vtestz_ps
__builtin_ia32_vtestzps256: x86::avx_vtestz_ps_256
__builtin_ia32_vzeroall: x86::avx_vzeroall
__builtin_ia32_vzeroupper: x86::avx_vzeroupper
__builtin_ia32_wrfsbase32: x86::wrfsbase_32
__builtin_ia32_wrfsbase64: x86::wrfsbase_64
__builtin_ia32_wrgsbase32: x86::wrgsbase_32
__builtin_ia32_wrgsbase64: x86::wrgsbase_64
__builtin_ia32_writeeflags_u32: x86::flags_write_u32
__builtin_ia32_writeeflags_u64: x86::flags_write_u64
__builtin_ia32_wrpkru: x86::wrpkru
__builtin_ia32_xabort: x86::xabort
__builtin_ia32_xbegin: x86::xbegin
__builtin_ia32_xend: x86::xend
__builtin_ia32_xorpd128_mask: x86::avx512_mask_xor_pd_128
__builtin_ia32_xorpd256_mask: x86::avx512_mask_xor_pd_256
__builtin_ia32_xorpd512_mask: x86::avx512_mask_xor_pd_512
__builtin_ia32_xorps128_mask: x86::avx512_mask_xor_ps_128
__builtin_ia32_xorps256_mask: x86::avx512_mask_xor_ps_256
__builtin_ia32_xorps512_mask: x86::avx512_mask_xor_ps_512
__builtin_ia32_xtest: x86::xtest
__builtin_init_trampoline: init_trampoline
__builtin_mips_addsc: mips::addsc
__builtin_mips_addu_ph: mips::addu_ph
__builtin_mips_addu_qb: mips::addu_qb
__builtin_mips_addu_s_ph: mips::addu_s_ph
__builtin_mips_addu_s_qb: mips::addu_s_qb
__builtin_mips_adduh_qb: mips::adduh_qb
__builtin_mips_adduh_r_qb: mips::adduh_r_qb
__builtin_mips_addwc: mips::addwc
__builtin_mips_append: mips::append
__builtin_mips_balign: mips::balign
__builtin_mips_bitrev: mips::bitrev
__builtin_mips_bposge32: mips::bposge32
__builtin_mips_cmpgdu_eq_qb: mips::cmpgdu_eq_qb
__builtin_mips_cmpgdu_le_qb: mips::cmpgdu_le_qb
__builtin_mips_cmpgdu_lt_qb: mips::cmpgdu_lt_qb
__builtin_mips_cmpgu_eq_qb: mips::cmpgu_eq_qb
__builtin_mips_cmpgu_le_qb: mips::cmpgu_le_qb
__builtin_mips_cmpgu_lt_qb: mips::cmpgu_lt_qb
__builtin_mips_cmpu_eq_qb: mips::cmpu_eq_qb
__builtin_mips_cmpu_le_qb: mips::cmpu_le_qb
__builtin_mips_cmpu_lt_qb: mips::cmpu_lt_qb
__builtin_mips_dlsa: mips::dlsa
__builtin_mips_dpa_w_ph: mips::dpa_w_ph
__builtin_mips_dpau_h_qbl: mips::dpau_h_qbl
__builtin_mips_dpau_h_qbr: mips::dpau_h_qbr
__builtin_mips_dpax_w_ph: mips::dpax_w_ph
__builtin_mips_dps_w_ph: mips::dps_w_ph
__builtin_mips_dpsu_h_qbl: mips::dpsu_h_qbl
__builtin_mips_dpsu_h_qbr: mips::dpsu_h_qbr
__builtin_mips_dpsx_w_ph: mips::dpsx_w_ph
__builtin_mips_extp: mips::extp
__builtin_mips_extpdp: mips::extpdp
__builtin_mips_extr_r_w: mips::extr_r_w
__builtin_mips_extr_rs_w: mips::extr_rs_w
__builtin_mips_extr_s_h: mips::extr_s_h
__builtin_mips_extr_w: mips::extr_w
__builtin_mips_insv: mips::insv
__builtin_mips_lbux: mips::lbux
__builtin_mips_lhx: mips::lhx
__builtin_mips_lsa: mips::lsa
__builtin_mips_lwx: mips::lwx
__builtin_mips_madd: mips::madd
__builtin_mips_maddu: mips::maddu
__builtin_mips_modsub: mips::modsub
__builtin_mips_msub: mips::msub
__builtin_mips_msubu: mips::msubu
__builtin_mips_mthlip: mips::mthlip
__builtin_mips_mul_ph: mips::mul_ph
__builtin_mips_mul_s_ph: mips::mul_s_ph
__builtin_mips_mulsa_w_ph: mips::mulsa_w_ph
__builtin_mips_mult: mips::mult
__builtin_mips_multu: mips::multu
__builtin_mips_pick_qb: mips::pick_qb
__builtin_mips_precr_qb_ph: mips::precr_qb_ph
__builtin_mips_precr_sra_ph_w: mips::precr_sra_ph_w
__builtin_mips_precr_sra_r_ph_w: mips::precr_sra_r_ph_w
__builtin_mips_prepend: mips::prepend
__builtin_mips_raddu_w_qb: mips::raddu_w_qb
__builtin_mips_rddsp: mips::rddsp
__builtin_mips_repl_qb: mips::repl_qb
__builtin_mips_shilo: mips::shilo
__builtin_mips_shll_qb: mips::shll_qb
__builtin_mips_shra_qb: mips::shra_qb
__builtin_mips_shra_r_qb: mips::shra_r_qb
__builtin_mips_shrl_ph: mips::shrl_ph
__builtin_mips_shrl_qb: mips::shrl_qb
__builtin_mips_subu_ph: mips::subu_ph
__builtin_mips_subu_qb: mips::subu_qb
__builtin_mips_subu_s_ph: mips::subu_s_ph
__builtin_mips_subu_s_qb: mips::subu_s_qb
__builtin_mips_subuh_qb: mips::subuh_qb
__builtin_mips_subuh_r_qb: mips::subuh_r_qb
__builtin_mips_wrdsp: mips::wrdsp
__builtin_msa_add_a_b: mips::add_a_b
__builtin_msa_add_a_d: mips::add_a_d
__builtin_msa_add_a_h: mips::add_a_h
__builtin_msa_add_a_w: mips::add_a_w
__builtin_msa_adds_a_b: mips::adds_a_b
__builtin_msa_adds_a_d: mips::adds_a_d
__builtin_msa_adds_a_h: mips::adds_a_h
__builtin_msa_adds_a_w: mips::adds_a_w
__builtin_msa_adds_s_b: mips::adds_s_b
__builtin_msa_adds_s_d: mips::adds_s_d
__builtin_msa_adds_s_h: mips::adds_s_h
__builtin_msa_adds_s_w: mips::adds_s_w
__builtin_msa_adds_u_b: mips::adds_u_b
__builtin_msa_adds_u_d: mips::adds_u_d
__builtin_msa_adds_u_h: mips::adds_u_h
__builtin_msa_adds_u_w: mips::adds_u_w
__builtin_msa_addv_b: mips::addv_b
__builtin_msa_addv_d: mips::addv_d
__builtin_msa_addv_h: mips::addv_h
__builtin_msa_addv_w: mips::addv_w
__builtin_msa_addvi_b: mips::addvi_b
__builtin_msa_addvi_d: mips::addvi_d
__builtin_msa_addvi_h: mips::addvi_h
__builtin_msa_addvi_w: mips::addvi_w
__builtin_msa_and_v: mips::and_v
__builtin_msa_andi_b: mips::andi_b
__builtin_msa_asub_s_b: mips::asub_s_b
__builtin_msa_asub_s_d: mips::asub_s_d
__builtin_msa_asub_s_h: mips::asub_s_h
__builtin_msa_asub_s_w: mips::asub_s_w
__builtin_msa_asub_u_b: mips::asub_u_b
__builtin_msa_asub_u_d: mips::asub_u_d
__builtin_msa_asub_u_h: mips::asub_u_h
__builtin_msa_asub_u_w: mips::asub_u_w
__builtin_msa_ave_s_b: mips::ave_s_b
__builtin_msa_ave_s_d: mips::ave_s_d
__builtin_msa_ave_s_h: mips::ave_s_h
__builtin_msa_ave_s_w: mips::ave_s_w
__builtin_msa_ave_u_b: mips::ave_u_b
__builtin_msa_ave_u_d: mips::ave_u_d
__builtin_msa_ave_u_h: mips::ave_u_h
__builtin_msa_ave_u_w: mips::ave_u_w
__builtin_msa_aver_s_b: mips::aver_s_b
__builtin_msa_aver_s_d: mips::aver_s_d
__builtin_msa_aver_s_h: mips::aver_s_h
__builtin_msa_aver_s_w: mips::aver_s_w
__builtin_msa_aver_u_b: mips::aver_u_b
__builtin_msa_aver_u_d: mips::aver_u_d
__builtin_msa_aver_u_h: mips::aver_u_h
__builtin_msa_aver_u_w: mips::aver_u_w
__builtin_msa_bclr_b: mips::bclr_b
__builtin_msa_bclr_d: mips::bclr_d
__builtin_msa_bclr_h: mips::bclr_h
__builtin_msa_bclr_w: mips::bclr_w
__builtin_msa_bclri_b: mips::bclri_b
__builtin_msa_bclri_d: mips::bclri_d
__builtin_msa_bclri_h: mips::bclri_h
__builtin_msa_bclri_w: mips::bclri_w
__builtin_msa_binsl_b: mips::binsl_b
__builtin_msa_binsl_d: mips::binsl_d
__builtin_msa_binsl_h: mips::binsl_h
__builtin_msa_binsl_w: mips::binsl_w
__builtin_msa_binsli_b: mips::binsli_b
__builtin_msa_binsli_d: mips::binsli_d
__builtin_msa_binsli_h: mips::binsli_h
__builtin_msa_binsli_w: mips::binsli_w
__builtin_msa_binsr_b: mips::binsr_b
__builtin_msa_binsr_d: mips::binsr_d
__builtin_msa_binsr_h: mips::binsr_h
__builtin_msa_binsr_w: mips::binsr_w
__builtin_msa_binsri_b: mips::binsri_b
__builtin_msa_binsri_d: mips::binsri_d
__builtin_msa_binsri_h: mips::binsri_h
__builtin_msa_binsri_w: mips::binsri_w
__builtin_msa_bmnz_v: mips::bmnz_v
__builtin_msa_bmnzi_b: mips::bmnzi_b
__builtin_msa_bmz_v: mips::bmz_v
__builtin_msa_bmzi_b: mips::bmzi_b
__builtin_msa_bneg_b: mips::bneg_b
__builtin_msa_bneg_d: mips::bneg_d
__builtin_msa_bneg_h: mips::bneg_h
__builtin_msa_bneg_w: mips::bneg_w
__builtin_msa_bnegi_b: mips::bnegi_b
__builtin_msa_bnegi_d: mips::bnegi_d
__builtin_msa_bnegi_h: mips::bnegi_h
__builtin_msa_bnegi_w: mips::bnegi_w
__builtin_msa_bnz_b: mips::bnz_b
__builtin_msa_bnz_d: mips::bnz_d
__builtin_msa_bnz_h: mips::bnz_h
__builtin_msa_bnz_v: mips::bnz_v
__builtin_msa_bnz_w: mips::bnz_w
__builtin_msa_bsel_v: mips::bsel_v
__builtin_msa_bseli_b: mips::bseli_b
__builtin_msa_bset_b: mips::bset_b
__builtin_msa_bset_d: mips::bset_d
__builtin_msa_bset_h: mips::bset_h
__builtin_msa_bset_w: mips::bset_w
__builtin_msa_bseti_b: mips::bseti_b
__builtin_msa_bseti_d: mips::bseti_d
__builtin_msa_bseti_h: mips::bseti_h
__builtin_msa_bseti_w: mips::bseti_w
__builtin_msa_bz_b: mips::bz_b
__builtin_msa_bz_d: mips::bz_d
__builtin_msa_bz_h: mips::bz_h
__builtin_msa_bz_v: mips::bz_v
__builtin_msa_bz_w: mips::bz_w
__builtin_msa_ceq_b: mips::ceq_b
__builtin_msa_ceq_d: mips::ceq_d
__builtin_msa_ceq_h: mips::ceq_h
__builtin_msa_ceq_w: mips::ceq_w
__builtin_msa_ceqi_b: mips::ceqi_b
__builtin_msa_ceqi_d: mips::ceqi_d
__builtin_msa_ceqi_h: mips::ceqi_h
__builtin_msa_ceqi_w: mips::ceqi_w
__builtin_msa_cfcmsa: mips::cfcmsa
__builtin_msa_cle_s_b: mips::cle_s_b
__builtin_msa_cle_s_d: mips::cle_s_d
__builtin_msa_cle_s_h: mips::cle_s_h
__builtin_msa_cle_s_w: mips::cle_s_w
__builtin_msa_cle_u_b: mips::cle_u_b
__builtin_msa_cle_u_d: mips::cle_u_d
__builtin_msa_cle_u_h: mips::cle_u_h
__builtin_msa_cle_u_w: mips::cle_u_w
__builtin_msa_clei_s_b: mips::clei_s_b
__builtin_msa_clei_s_d: mips::clei_s_d
__builtin_msa_clei_s_h: mips::clei_s_h
__builtin_msa_clei_s_w: mips::clei_s_w
__builtin_msa_clei_u_b: mips::clei_u_b
__builtin_msa_clei_u_d: mips::clei_u_d
__builtin_msa_clei_u_h: mips::clei_u_h
__builtin_msa_clei_u_w: mips::clei_u_w
__builtin_msa_clt_s_b: mips::clt_s_b
__builtin_msa_clt_s_d: mips::clt_s_d
__builtin_msa_clt_s_h: mips::clt_s_h
__builtin_msa_clt_s_w: mips::clt_s_w
__builtin_msa_clt_u_b: mips::clt_u_b
__builtin_msa_clt_u_d: mips::clt_u_d
__builtin_msa_clt_u_h: mips::clt_u_h
__builtin_msa_clt_u_w: mips::clt_u_w
__builtin_msa_clti_s_b: mips::clti_s_b
__builtin_msa_clti_s_d: mips::clti_s_d
__builtin_msa_clti_s_h: mips::clti_s_h
__builtin_msa_clti_s_w: mips::clti_s_w
__builtin_msa_clti_u_b: mips::clti_u_b
__builtin_msa_clti_u_d: mips::clti_u_d
__builtin_msa_clti_u_h: mips::clti_u_h
__builtin_msa_clti_u_w: mips::clti_u_w
__builtin_msa_copy_s_b: mips::copy_s_b
__builtin_msa_copy_s_d: mips::copy_s_d
__builtin_msa_copy_s_h: mips::copy_s_h
__builtin_msa_copy_s_w: mips::copy_s_w
__builtin_msa_copy_u_b: mips::copy_u_b
__builtin_msa_copy_u_d: mips::copy_u_d
__builtin_msa_copy_u_h: mips::copy_u_h
__builtin_msa_copy_u_w: mips::copy_u_w
__builtin_msa_ctcmsa: mips::ctcmsa
__builtin_msa_div_s_b: mips::div_s_b
__builtin_msa_div_s_d: mips::div_s_d
__builtin_msa_div_s_h: mips::div_s_h
__builtin_msa_div_s_w: mips::div_s_w
__builtin_msa_div_u_b: mips::div_u_b
__builtin_msa_div_u_d: mips::div_u_d
__builtin_msa_div_u_h: mips::div_u_h
__builtin_msa_div_u_w: mips::div_u_w
__builtin_msa_dotp_s_d: mips::dotp_s_d
__builtin_msa_dotp_s_h: mips::dotp_s_h
__builtin_msa_dotp_s_w: mips::dotp_s_w
__builtin_msa_dotp_u_d: mips::dotp_u_d
__builtin_msa_dotp_u_h: mips::dotp_u_h
__builtin_msa_dotp_u_w: mips::dotp_u_w
__builtin_msa_dpadd_s_d: mips::dpadd_s_d
__builtin_msa_dpadd_s_h: mips::dpadd_s_h
__builtin_msa_dpadd_s_w: mips::dpadd_s_w
__builtin_msa_dpadd_u_d: mips::dpadd_u_d
__builtin_msa_dpadd_u_h: mips::dpadd_u_h
__builtin_msa_dpadd_u_w: mips::dpadd_u_w
__builtin_msa_dpsub_s_d: mips::dpsub_s_d
__builtin_msa_dpsub_s_h: mips::dpsub_s_h
__builtin_msa_dpsub_s_w: mips::dpsub_s_w
__builtin_msa_dpsub_u_d: mips::dpsub_u_d
__builtin_msa_dpsub_u_h: mips::dpsub_u_h
__builtin_msa_dpsub_u_w: mips::dpsub_u_w
__builtin_msa_fadd_d: mips::fadd_d
__builtin_msa_fadd_w: mips::fadd_w
__builtin_msa_fcaf_d: mips::fcaf_d
__builtin_msa_fcaf_w: mips::fcaf_w
__builtin_msa_fceq_d: mips::fceq_d
__builtin_msa_fceq_w: mips::fceq_w
__builtin_msa_fclass_d: mips::fclass_d
__builtin_msa_fclass_w: mips::fclass_w
__builtin_msa_fcle_d: mips::fcle_d
__builtin_msa_fcle_w: mips::fcle_w
__builtin_msa_fclt_d: mips::fclt_d
__builtin_msa_fclt_w: mips::fclt_w
__builtin_msa_fcne_d: mips::fcne_d
__builtin_msa_fcne_w: mips::fcne_w
__builtin_msa_fcor_d: mips::fcor_d
__builtin_msa_fcor_w: mips::fcor_w
__builtin_msa_fcueq_d: mips::fcueq_d
__builtin_msa_fcueq_w: mips::fcueq_w
__builtin_msa_fcule_d: mips::fcule_d
__builtin_msa_fcule_w: mips::fcule_w
__builtin_msa_fcult_d: mips::fcult_d
__builtin_msa_fcult_w: mips::fcult_w
__builtin_msa_fcun_d: mips::fcun_d
__builtin_msa_fcun_w: mips::fcun_w
__builtin_msa_fcune_d: mips::fcune_d
__builtin_msa_fcune_w: mips::fcune_w
__builtin_msa_fdiv_d: mips::fdiv_d
__builtin_msa_fdiv_w: mips::fdiv_w
__builtin_msa_fexdo_w: mips::fexdo_w
__builtin_msa_fexp2_d: mips::fexp2_d
__builtin_msa_fexp2_w: mips::fexp2_w
__builtin_msa_fexupl_d: mips::fexupl_d
__builtin_msa_fexupr_d: mips::fexupr_d
__builtin_msa_ffint_s_d: mips::ffint_s_d
__builtin_msa_ffint_s_w: mips::ffint_s_w
__builtin_msa_ffint_u_d: mips::ffint_u_d
__builtin_msa_ffint_u_w: mips::ffint_u_w
__builtin_msa_ffql_d: mips::ffql_d
__builtin_msa_ffql_w: mips::ffql_w
__builtin_msa_ffqr_d: mips::ffqr_d
__builtin_msa_ffqr_w: mips::ffqr_w
__builtin_msa_fill_b: mips::fill_b
__builtin_msa_fill_d: mips::fill_d
__builtin_msa_fill_h: mips::fill_h
__builtin_msa_fill_w: mips::fill_w
__builtin_msa_flog2_d: mips::flog2_d
__builtin_msa_flog2_w: mips::flog2_w
__builtin_msa_fmadd_d: mips::fmadd_d
__builtin_msa_fmadd_w: mips::fmadd_w
__builtin_msa_fmax_a_d: mips::fmax_a_d
__builtin_msa_fmax_a_w: mips::fmax_a_w
__builtin_msa_fmax_d: mips::fmax_d
__builtin_msa_fmax_w: mips::fmax_w
__builtin_msa_fmin_a_d: mips::fmin_a_d
__builtin_msa_fmin_a_w: mips::fmin_a_w
__builtin_msa_fmin_d: mips::fmin_d
__builtin_msa_fmin_w: mips::fmin_w
__builtin_msa_fmsub_d: mips::fmsub_d
__builtin_msa_fmsub_w: mips::fmsub_w
__builtin_msa_fmul_d: mips::fmul_d
__builtin_msa_fmul_w: mips::fmul_w
__builtin_msa_frcp_d: mips::frcp_d
__builtin_msa_frcp_w: mips::frcp_w
__builtin_msa_frint_d: mips::frint_d
__builtin_msa_frint_w: mips::frint_w
__builtin_msa_frsqrt_d: mips::frsqrt_d
__builtin_msa_frsqrt_w: mips::frsqrt_w
__builtin_msa_fsaf_d: mips::fsaf_d
__builtin_msa_fsaf_w: mips::fsaf_w
__builtin_msa_fseq_d: mips::fseq_d
__builtin_msa_fseq_w: mips::fseq_w
__builtin_msa_fsle_d: mips::fsle_d
__builtin_msa_fsle_w: mips::fsle_w
__builtin_msa_fslt_d: mips::fslt_d
__builtin_msa_fslt_w: mips::fslt_w
__builtin_msa_fsne_d: mips::fsne_d
__builtin_msa_fsne_w: mips::fsne_w
__builtin_msa_fsor_d: mips::fsor_d
__builtin_msa_fsor_w: mips::fsor_w
__builtin_msa_fsqrt_d: mips::fsqrt_d
__builtin_msa_fsqrt_w: mips::fsqrt_w
__builtin_msa_fsub_d: mips::fsub_d
__builtin_msa_fsub_w: mips::fsub_w
__builtin_msa_fsueq_d: mips::fsueq_d
__builtin_msa_fsueq_w: mips::fsueq_w
__builtin_msa_fsule_d: mips::fsule_d
__builtin_msa_fsule_w: mips::fsule_w
__builtin_msa_fsult_d: mips::fsult_d
__builtin_msa_fsult_w: mips::fsult_w
__builtin_msa_fsun_d: mips::fsun_d
__builtin_msa_fsun_w: mips::fsun_w
__builtin_msa_fsune_d: mips::fsune_d
__builtin_msa_fsune_w: mips::fsune_w
__builtin_msa_ftint_s_d: mips::ftint_s_d
__builtin_msa_ftint_s_w: mips::ftint_s_w
__builtin_msa_ftint_u_d: mips::ftint_u_d
__builtin_msa_ftint_u_w: mips::ftint_u_w
__builtin_msa_ftq_h: mips::ftq_h
__builtin_msa_ftq_w: mips::ftq_w
__builtin_msa_ftrunc_s_d: mips::ftrunc_s_d
__builtin_msa_ftrunc_s_w: mips::ftrunc_s_w
__builtin_msa_ftrunc_u_d: mips::ftrunc_u_d
__builtin_msa_ftrunc_u_w: mips::ftrunc_u_w
__builtin_msa_hadd_s_d: mips::hadd_s_d
__builtin_msa_hadd_s_h: mips::hadd_s_h
__builtin_msa_hadd_s_w: mips::hadd_s_w
__builtin_msa_hadd_u_d: mips::hadd_u_d
__builtin_msa_hadd_u_h: mips::hadd_u_h
__builtin_msa_hadd_u_w: mips::hadd_u_w
__builtin_msa_hsub_s_d: mips::hsub_s_d
__builtin_msa_hsub_s_h: mips::hsub_s_h
__builtin_msa_hsub_s_w: mips::hsub_s_w
__builtin_msa_hsub_u_d: mips::hsub_u_d
__builtin_msa_hsub_u_h: mips::hsub_u_h
__builtin_msa_hsub_u_w: mips::hsub_u_w
__builtin_msa_ilvev_b: mips::ilvev_b
__builtin_msa_ilvev_d: mips::ilvev_d
__builtin_msa_ilvev_h: mips::ilvev_h
__builtin_msa_ilvev_w: mips::ilvev_w
__builtin_msa_ilvl_b: mips::ilvl_b
__builtin_msa_ilvl_d: mips::ilvl_d
__builtin_msa_ilvl_h: mips::ilvl_h
__builtin_msa_ilvl_w: mips::ilvl_w
__builtin_msa_ilvod_b: mips::ilvod_b
__builtin_msa_ilvod_d: mips::ilvod_d
__builtin_msa_ilvod_h: mips::ilvod_h
__builtin_msa_ilvod_w: mips::ilvod_w
__builtin_msa_ilvr_b: mips::ilvr_b
__builtin_msa_ilvr_d: mips::ilvr_d
__builtin_msa_ilvr_h: mips::ilvr_h
__builtin_msa_ilvr_w: mips::ilvr_w
__builtin_msa_insert_b: mips::insert_b
__builtin_msa_insert_d: mips::insert_d
__builtin_msa_insert_h: mips::insert_h
__builtin_msa_insert_w: mips::insert_w
__builtin_msa_insve_b: mips::insve_b
__builtin_msa_insve_d: mips::insve_d
__builtin_msa_insve_h: mips::insve_h
__builtin_msa_insve_w: mips::insve_w
__builtin_msa_ld_b: mips::ld_b
__builtin_msa_ld_d: mips::ld_d
__builtin_msa_ld_h: mips::ld_h
__builtin_msa_ld_w: mips::ld_w
__builtin_msa_ldi_b: mips::ldi_b
__builtin_msa_ldi_d: mips::ldi_d
__builtin_msa_ldi_h: mips::ldi_h
__builtin_msa_ldi_w: mips::ldi_w
__builtin_msa_madd_q_h: mips::madd_q_h
__builtin_msa_madd_q_w: mips::madd_q_w
__builtin_msa_maddr_q_h: mips::maddr_q_h
__builtin_msa_maddr_q_w: mips::maddr_q_w
__builtin_msa_maddv_b: mips::maddv_b
__builtin_msa_maddv_d: mips::maddv_d
__builtin_msa_maddv_h: mips::maddv_h
__builtin_msa_maddv_w: mips::maddv_w
__builtin_msa_max_a_b: mips::max_a_b
__builtin_msa_max_a_d: mips::max_a_d
__builtin_msa_max_a_h: mips::max_a_h
__builtin_msa_max_a_w: mips::max_a_w
__builtin_msa_max_s_b: mips::max_s_b
__builtin_msa_max_s_d: mips::max_s_d
__builtin_msa_max_s_h: mips::max_s_h
__builtin_msa_max_s_w: mips::max_s_w
__builtin_msa_max_u_b: mips::max_u_b
__builtin_msa_max_u_d: mips::max_u_d
__builtin_msa_max_u_h: mips::max_u_h
__builtin_msa_max_u_w: mips::max_u_w
__builtin_msa_maxi_s_b: mips::maxi_s_b
__builtin_msa_maxi_s_d: mips::maxi_s_d
__builtin_msa_maxi_s_h: mips::maxi_s_h
__builtin_msa_maxi_s_w: mips::maxi_s_w
__builtin_msa_maxi_u_b: mips::maxi_u_b
__builtin_msa_maxi_u_d: mips::maxi_u_d
__builtin_msa_maxi_u_h: mips::maxi_u_h
__builtin_msa_maxi_u_w: mips::maxi_u_w
__builtin_msa_min_a_b: mips::min_a_b
__builtin_msa_min_a_d: mips::min_a_d
__builtin_msa_min_a_h: mips::min_a_h
__builtin_msa_min_a_w: mips::min_a_w
__builtin_msa_min_s_b: mips::min_s_b
__builtin_msa_min_s_d: mips::min_s_d
__builtin_msa_min_s_h: mips::min_s_h
__builtin_msa_min_s_w: mips::min_s_w
__builtin_msa_min_u_b: mips::min_u_b
__builtin_msa_min_u_d: mips::min_u_d
__builtin_msa_min_u_h: mips::min_u_h
__builtin_msa_min_u_w: mips::min_u_w
__builtin_msa_mini_s_b: mips::mini_s_b
__builtin_msa_mini_s_d: mips::mini_s_d
__builtin_msa_mini_s_h: mips::mini_s_h
__builtin_msa_mini_s_w: mips::mini_s_w
__builtin_msa_mini_u_b: mips::mini_u_b
__builtin_msa_mini_u_d: mips::mini_u_d
__builtin_msa_mini_u_h: mips::mini_u_h
__builtin_msa_mini_u_w: mips::mini_u_w
__builtin_msa_mod_s_b: mips::mod_s_b
__builtin_msa_mod_s_d: mips::mod_s_d
__builtin_msa_mod_s_h: mips::mod_s_h
__builtin_msa_mod_s_w: mips::mod_s_w
__builtin_msa_mod_u_b: mips::mod_u_b
__builtin_msa_mod_u_d: mips::mod_u_d
__builtin_msa_mod_u_h: mips::mod_u_h
__builtin_msa_mod_u_w: mips::mod_u_w
__builtin_msa_move_v: mips::move_v
__builtin_msa_msub_q_h: mips::msub_q_h
__builtin_msa_msub_q_w: mips::msub_q_w
__builtin_msa_msubr_q_h: mips::msubr_q_h
__builtin_msa_msubr_q_w: mips::msubr_q_w
__builtin_msa_msubv_b: mips::msubv_b
__builtin_msa_msubv_d: mips::msubv_d
__builtin_msa_msubv_h: mips::msubv_h
__builtin_msa_msubv_w: mips::msubv_w
__builtin_msa_mul_q_h: mips::mul_q_h
__builtin_msa_mul_q_w: mips::mul_q_w
__builtin_msa_mulr_q_h: mips::mulr_q_h
__builtin_msa_mulr_q_w: mips::mulr_q_w
__builtin_msa_mulv_b: mips::mulv_b
__builtin_msa_mulv_d: mips::mulv_d
__builtin_msa_mulv_h: mips::mulv_h
__builtin_msa_mulv_w: mips::mulv_w
__builtin_msa_nloc_b: mips::nloc_b
__builtin_msa_nloc_d: mips::nloc_d
__builtin_msa_nloc_h: mips::nloc_h
__builtin_msa_nloc_w: mips::nloc_w
__builtin_msa_nlzc_b: mips::nlzc_b
__builtin_msa_nlzc_d: mips::nlzc_d
__builtin_msa_nlzc_h: mips::nlzc_h
__builtin_msa_nlzc_w: mips::nlzc_w
__builtin_msa_nor_v: mips::nor_v
__builtin_msa_nori_b: mips::nori_b
__builtin_msa_or_v: mips::or_v
__builtin_msa_ori_b: mips::ori_b
__builtin_msa_pckev_b: mips::pckev_b
__builtin_msa_pckev_d: mips::pckev_d
__builtin_msa_pckev_h: mips::pckev_h
__builtin_msa_pckev_w: mips::pckev_w
__builtin_msa_pckod_b: mips::pckod_b
__builtin_msa_pckod_d: mips::pckod_d
__builtin_msa_pckod_h: mips::pckod_h
__builtin_msa_pckod_w: mips::pckod_w
__builtin_msa_pcnt_b: mips::pcnt_b
__builtin_msa_pcnt_d: mips::pcnt_d
__builtin_msa_pcnt_h: mips::pcnt_h
__builtin_msa_pcnt_w: mips::pcnt_w
__builtin_msa_sat_s_b: mips::sat_s_b
__builtin_msa_sat_s_d: mips::sat_s_d
__builtin_msa_sat_s_h: mips::sat_s_h
__builtin_msa_sat_s_w: mips::sat_s_w
__builtin_msa_sat_u_b: mips::sat_u_b
__builtin_msa_sat_u_d: mips::sat_u_d
__builtin_msa_sat_u_h: mips::sat_u_h
__builtin_msa_sat_u_w: mips::sat_u_w
__builtin_msa_shf_b: mips::shf_b
__builtin_msa_shf_h: mips::shf_h
__builtin_msa_shf_w: mips::shf_w
__builtin_msa_sld_b: mips::sld_b
__builtin_msa_sld_d: mips::sld_d
__builtin_msa_sld_h: mips::sld_h
__builtin_msa_sld_w: mips::sld_w
__builtin_msa_sldi_b: mips::sldi_b
__builtin_msa_sldi_d: mips::sldi_d
__builtin_msa_sldi_h: mips::sldi_h
__builtin_msa_sldi_w: mips::sldi_w
__builtin_msa_sll_b: mips::sll_b
__builtin_msa_sll_d: mips::sll_d
__builtin_msa_sll_h: mips::sll_h
__builtin_msa_sll_w: mips::sll_w
__builtin_msa_slli_b: mips::slli_b
__builtin_msa_slli_d: mips::slli_d
__builtin_msa_slli_h: mips::slli_h
__builtin_msa_slli_w: mips::slli_w
__builtin_msa_splat_b: mips::splat_b
__builtin_msa_splat_d: mips::splat_d
__builtin_msa_splat_h: mips::splat_h
__builtin_msa_splat_w: mips::splat_w
__builtin_msa_splati_b: mips::splati_b
__builtin_msa_splati_d: mips::splati_d
__builtin_msa_splati_h: mips::splati_h
__builtin_msa_splati_w: mips::splati_w
__builtin_msa_sra_b: mips::sra_b
__builtin_msa_sra_d: mips::sra_d
__builtin_msa_sra_h: mips::sra_h
__builtin_msa_sra_w: mips::sra_w
__builtin_msa_srai_b: mips::srai_b
__builtin_msa_srai_d: mips::srai_d
__builtin_msa_srai_h: mips::srai_h
__builtin_msa_srai_w: mips::srai_w
__builtin_msa_srar_b: mips::srar_b
__builtin_msa_srar_d: mips::srar_d
__builtin_msa_srar_h: mips::srar_h
__builtin_msa_srar_w: mips::srar_w
__builtin_msa_srari_b: mips::srari_b
__builtin_msa_srari_d: mips::srari_d
__builtin_msa_srari_h: mips::srari_h
__builtin_msa_srari_w: mips::srari_w
__builtin_msa_srl_b: mips::srl_b
__builtin_msa_srl_d: mips::srl_d
__builtin_msa_srl_h: mips::srl_h
__builtin_msa_srl_w: mips::srl_w
__builtin_msa_srli_b: mips::srli_b
__builtin_msa_srli_d: mips::srli_d
__builtin_msa_srli_h: mips::srli_h
__builtin_msa_srli_w: mips::srli_w
__builtin_msa_srlr_b: mips::srlr_b
__builtin_msa_srlr_d: mips::srlr_d
__builtin_msa_srlr_h: mips::srlr_h
__builtin_msa_srlr_w: mips::srlr_w
__builtin_msa_srlri_b: mips::srlri_b
__builtin_msa_srlri_d: mips::srlri_d
__builtin_msa_srlri_h: mips::srlri_h
__builtin_msa_srlri_w: mips::srlri_w
__builtin_msa_st_b: mips::st_b
__builtin_msa_st_d: mips::st_d
__builtin_msa_st_h: mips::st_h
__builtin_msa_st_w: mips::st_w
__builtin_msa_subs_s_b: mips::subs_s_b
__builtin_msa_subs_s_d: mips::subs_s_d
__builtin_msa_subs_s_h: mips::subs_s_h
__builtin_msa_subs_s_w: mips::subs_s_w
__builtin_msa_subs_u_b: mips::subs_u_b
__builtin_msa_subs_u_d: mips::subs_u_d
__builtin_msa_subs_u_h: mips::subs_u_h
__builtin_msa_subs_u_w: mips::subs_u_w
__builtin_msa_subsus_u_b: mips::subsus_u_b
__builtin_msa_subsus_u_d: mips::subsus_u_d
__builtin_msa_subsus_u_h: mips::subsus_u_h
__builtin_msa_subsus_u_w: mips::subsus_u_w
__builtin_msa_subsuu_s_b: mips::subsuu_s_b
__builtin_msa_subsuu_s_d: mips::subsuu_s_d
__builtin_msa_subsuu_s_h: mips::subsuu_s_h
__builtin_msa_subsuu_s_w: mips::subsuu_s_w
__builtin_msa_subv_b: mips::subv_b
__builtin_msa_subv_d: mips::subv_d
__builtin_msa_subv_h: mips::subv_h
__builtin_msa_subv_w: mips::subv_w
__builtin_msa_subvi_b: mips::subvi_b
__builtin_msa_subvi_d: mips::subvi_d
__builtin_msa_subvi_h: mips::subvi_h
__builtin_msa_subvi_w: mips::subvi_w
__builtin_msa_vshf_b: mips::vshf_b
__builtin_msa_vshf_d: mips::vshf_d
__builtin_msa_vshf_h: mips::vshf_h
__builtin_msa_vshf_w: mips::vshf_w
__builtin_msa_xor_v: mips::xor_v
__builtin_msa_xori_b: mips::xori_b
__builtin_object_size: objectsize_v16i8_p0i8; objectsize_i8_p0i8; objectsize_v8i16_p0i8; objectsize_i16_p0i8; objectsize_v4i32_p0i8; objectsize_i32_p0i8; objectsize_v2i64_p0i8; objectsize_i64_p0i8
__builtin_qpx_qvfabs: ppc::qpx_qvfabs
__builtin_qpx_qvfadd: ppc::qpx_qvfadd
__builtin_qpx_qvfadds: ppc::qpx_qvfadds
__builtin_qpx_qvfcfid: ppc::qpx_qvfcfid
__builtin_qpx_qvfcfids: ppc::qpx_qvfcfids
__builtin_qpx_qvfcfidu: ppc::qpx_qvfcfidu
__builtin_qpx_qvfcfidus: ppc::qpx_qvfcfidus
__builtin_qpx_qvfcmpeq: ppc::qpx_qvfcmpeq
__builtin_qpx_qvfcmpgt: ppc::qpx_qvfcmpgt
__builtin_qpx_qvfcmplt: ppc::qpx_qvfcmplt
__builtin_qpx_qvfcpsgn: ppc::qpx_qvfcpsgn
__builtin_qpx_qvfctid: ppc::qpx_qvfctid
__builtin_qpx_qvfctidu: ppc::qpx_qvfctidu
__builtin_qpx_qvfctiduz: ppc::qpx_qvfctiduz
__builtin_qpx_qvfctidz: ppc::qpx_qvfctidz
__builtin_qpx_qvfctiw: ppc::qpx_qvfctiw
__builtin_qpx_qvfctiwu: ppc::qpx_qvfctiwu
__builtin_qpx_qvfctiwuz: ppc::qpx_qvfctiwuz
__builtin_qpx_qvfctiwz: ppc::qpx_qvfctiwz
__builtin_qpx_qvflogical: ppc::qpx_qvflogical
__builtin_qpx_qvfmadd: ppc::qpx_qvfmadd
__builtin_qpx_qvfmadds: ppc::qpx_qvfmadds
__builtin_qpx_qvfmsub: ppc::qpx_qvfmsub
__builtin_qpx_qvfmsubs: ppc::qpx_qvfmsubs
__builtin_qpx_qvfmul: ppc::qpx_qvfmul
__builtin_qpx_qvfmuls: ppc::qpx_qvfmuls
__builtin_qpx_qvfnabs: ppc::qpx_qvfnabs
__builtin_qpx_qvfneg: ppc::qpx_qvfneg
__builtin_qpx_qvfnmadd: ppc::qpx_qvfnmadd
__builtin_qpx_qvfnmadds: ppc::qpx_qvfnmadds
__builtin_qpx_qvfnmsub: ppc::qpx_qvfnmsub
__builtin_qpx_qvfnmsubs: ppc::qpx_qvfnmsubs
__builtin_qpx_qvfperm: ppc::qpx_qvfperm
__builtin_qpx_qvfre: ppc::qpx_qvfre
__builtin_qpx_qvfres: ppc::qpx_qvfres
__builtin_qpx_qvfrim: ppc::qpx_qvfrim
__builtin_qpx_qvfrin: ppc::qpx_qvfrin
__builtin_qpx_qvfrip: ppc::qpx_qvfrip
__builtin_qpx_qvfriz: ppc::qpx_qvfriz
__builtin_qpx_qvfrsp: ppc::qpx_qvfrsp
__builtin_qpx_qvfrsqrte: ppc::qpx_qvfrsqrte
__builtin_qpx_qvfrsqrtes: ppc::qpx_qvfrsqrtes
__builtin_qpx_qvfsel: ppc::qpx_qvfsel
__builtin_qpx_qvfsub: ppc::qpx_qvfsub
__builtin_qpx_qvfsubs: ppc::qpx_qvfsubs
__builtin_qpx_qvftstnan: ppc::qpx_qvftstnan
__builtin_qpx_qvfxmadd: ppc::qpx_qvfxmadd
__builtin_qpx_qvfxmadds: ppc::qpx_qvfxmadds
__builtin_qpx_qvfxmul: ppc::qpx_qvfxmul
__builtin_qpx_qvfxmuls: ppc::qpx_qvfxmuls
__builtin_qpx_qvfxxcpnmadd: ppc::qpx_qvfxxcpnmadd
__builtin_qpx_qvfxxcpnmadds: ppc::qpx_qvfxxcpnmadds
__builtin_qpx_qvfxxmadd: ppc::qpx_qvfxxmadd
__builtin_qpx_qvfxxmadds: ppc::qpx_qvfxxmadds
__builtin_qpx_qvfxxnpmadd: ppc::qpx_qvfxxnpmadd
__builtin_qpx_qvfxxnpmadds: ppc::qpx_qvfxxnpmadds
__builtin_qpx_qvgpci: ppc::qpx_qvgpci
__builtin_qpx_qvlfcd: ppc::qpx_qvlfcd
__builtin_qpx_qvlfcda: ppc::qpx_qvlfcda
__builtin_qpx_qvlfcs: ppc::qpx_qvlfcs
__builtin_qpx_qvlfcsa: ppc::qpx_qvlfcsa
__builtin_qpx_qvlfd: ppc::qpx_qvlfd
__builtin_qpx_qvlfda: ppc::qpx_qvlfda
__builtin_qpx_qvlfiwa: ppc::qpx_qvlfiwa
__builtin_qpx_qvlfiwaa: ppc::qpx_qvlfiwaa
__builtin_qpx_qvlfiwz: ppc::qpx_qvlfiwz
__builtin_qpx_qvlfiwza: ppc::qpx_qvlfiwza
__builtin_qpx_qvlfs: ppc::qpx_qvlfs
__builtin_qpx_qvlfsa: ppc::qpx_qvlfsa
__builtin_qpx_qvlpcld: ppc::qpx_qvlpcld
__builtin_qpx_qvlpcls: ppc::qpx_qvlpcls
__builtin_qpx_qvlpcrd: ppc::qpx_qvlpcrd
__builtin_qpx_qvlpcrs: ppc::qpx_qvlpcrs
__builtin_qpx_qvstfcd: ppc::qpx_qvstfcd
__builtin_qpx_qvstfcda: ppc::qpx_qvstfcda
__builtin_qpx_qvstfcs: ppc::qpx_qvstfcs
__builtin_qpx_qvstfcsa: ppc::qpx_qvstfcsa
__builtin_qpx_qvstfd: ppc::qpx_qvstfd
__builtin_qpx_qvstfda: ppc::qpx_qvstfda
__builtin_qpx_qvstfiw: ppc::qpx_qvstfiw
__builtin_qpx_qvstfiwa: ppc::qpx_qvstfiwa
__builtin_qpx_qvstfs: ppc::qpx_qvstfs
__builtin_qpx_qvstfsa: ppc::qpx_qvstfsa
__builtin_r600_group_barrier: r600::group_barrier
__builtin_r600_rat_store_typed: r600::rat_store_typed
__builtin_s390_: s390_vaq; s390_vacq; s390_vaccq; s390_vacccq; s390_vcksm; s390_vsl; s390_vslb; s390_vsra; s390_vsrab; s390_vsrl; s390_vsrlb; s390_vsq; s390_vsbiq; s390_vscbiq; s390_vsbcbiq; s390_vsumb; s390_vsumh; s390_vsumgh; s390_vsumgf; s390_vsumqf; s390_vsumqg; s390_vtm
__builtin_s390_lcbb: s390_lcbb
__builtin_s390_vlbb: s390_vlbb
__builtin_s390_vll: s390_vll
__builtin_s390_vpdi: s390_vpdi
__builtin_s390_vperm: s390_vperm
__builtin_s390_vsldb: s390_vsldb
__builtin_s390_vstl: s390_vstl
__builtin_set_texasr: ppc::set_texasr
__builtin_set_texasru: ppc::set_texasru
__builtin_set_tfhar: ppc::set_tfhar
__builtin_set_tfiar: ppc::set_tfiar
__builtin_setps: xcore::setps
__builtin_stack_restore: stackrestore
__builtin_stack_save: stacksave
__builtin_tabort: ppc::tabort
__builtin_tabortdc: ppc::tabortdc
__builtin_tabortdci: ppc::tabortdci
__builtin_tabortwc: ppc::tabortwc
__builtin_tabortwci: ppc::tabortwci
__builtin_tbegin: ppc::tbegin
__builtin_tcheck: ppc::tcheck
__builtin_tend: s390_tend; ppc::tend
__builtin_tendall: ppc::tendall
__builtin_thread_pointer: thread_pointer
__builtin_trap: trap
__builtin_trechkpt: ppc::trechkpt
__builtin_treclaim: ppc::treclaim
__builtin_tresume: ppc::tresume
__builtin_tsr: ppc::tsr
__builtin_tsuspend: ppc::tsuspend
__builtin_ttest: ppc::ttest
__builtin_tx_assist: s390_ppa_txassist
__builtin_tx_nesting_depth: s390_etnd
__builtin_unwind_init: eh_unwind_init
__builtin_vsx_xsmaxdp: ppc::vsx_xsmaxdp
__builtin_vsx_xsmindp: ppc::vsx_xsmindp
__builtin_vsx_xvcmpeqdp: ppc::vsx_xvcmpeqdp
__builtin_vsx_xvcmpeqdp_p: ppc::vsx_xvcmpeqdp_p
__builtin_vsx_xvcmpeqsp: ppc::vsx_xvcmpeqsp
__builtin_vsx_xvcmpeqsp_p: ppc::vsx_xvcmpeqsp_p
__builtin_vsx_xvcmpgedp: ppc::vsx_xvcmpgedp
__builtin_vsx_xvcmpgedp_p: ppc::vsx_xvcmpgedp_p
__builtin_vsx_xvcmpgesp: ppc::vsx_xvcmpgesp
__builtin_vsx_xvcmpgesp_p: ppc::vsx_xvcmpgesp_p
__builtin_vsx_xvcmpgtdp: ppc::vsx_xvcmpgtdp
__builtin_vsx_xvcmpgtdp_p: ppc::vsx_xvcmpgtdp_p
__builtin_vsx_xvcmpgtsp: ppc::vsx_xvcmpgtsp
__builtin_vsx_xvcmpgtsp_p: ppc::vsx_xvcmpgtsp_p
__builtin_vsx_xvdivdp: ppc::vsx_xvdivdp
__builtin_vsx_xvdivsp: ppc::vsx_xvdivsp
__builtin_vsx_xvmaxdp: ppc::vsx_xvmaxdp
__builtin_vsx_xvmaxsp: ppc::vsx_xvmaxsp
__builtin_vsx_xvmindp: ppc::vsx_xvmindp
__builtin_vsx_xvminsp: ppc::vsx_xvminsp
__builtin_vsx_xvredp: ppc::vsx_xvredp
__builtin_vsx_xvresp: ppc::vsx_xvresp
__builtin_vsx_xvrsqrtedp: ppc::vsx_xvrsqrtedp
__builtin_vsx_xvrsqrtesp: ppc::vsx_xvrsqrtesp
__builtin_vsx_xxleqv: ppc::vsx_xxleqv
__nvvm_abs_i: nvvm::abs_i
__nvvm_abs_ll: nvvm::abs_ll
__nvvm_add_rm_d: nvvm::add_rm_d
__nvvm_add_rm_f: nvvm::add_rm_f
__nvvm_add_rm_ftz_f: nvvm::add_rm_ftz_f
__nvvm_add_rn_d: nvvm::add_rn_d
__nvvm_add_rn_f: nvvm::add_rn_f
__nvvm_add_rn_ftz_f: nvvm::add_rn_ftz_f
__nvvm_add_rp_d: nvvm::add_rp_d
__nvvm_add_rp_f: nvvm::add_rp_f
__nvvm_add_rp_ftz_f: nvvm::add_rp_ftz_f
__nvvm_add_rz_d: nvvm::add_rz_d
__nvvm_add_rz_f: nvvm::add_rz_f
__nvvm_add_rz_ftz_f: nvvm::add_rz_ftz_f
__nvvm_bar0_and: nvvm::barrier0_and
__nvvm_bar0_or: nvvm::barrier0_or
__nvvm_bar0_popc: nvvm::barrier0_popc
__nvvm_bar_sync: nvvm::bar_sync
__nvvm_bitcast_d2ll: nvvm::bitcast_d2ll
__nvvm_bitcast_f2i: nvvm::bitcast_f2i
__nvvm_bitcast_i2f: nvvm::bitcast_i2f
__nvvm_bitcast_ll2d: nvvm::bitcast_ll2d
__nvvm_brev32: nvvm::brev32
__nvvm_brev64: nvvm::brev64
__nvvm_ceil_d: nvvm::ceil_d
__nvvm_ceil_f: nvvm::ceil_f
__nvvm_ceil_ftz_f: nvvm::ceil_ftz_f
__nvvm_clz_i: nvvm::clz_i
__nvvm_clz_ll: nvvm::clz_ll
__nvvm_cos_approx_f: nvvm::cos_approx_f
__nvvm_cos_approx_ftz_f: nvvm::cos_approx_ftz_f
__nvvm_d2f_rm: nvvm::d2f_rm
__nvvm_d2f_rm_ftz: nvvm::d2f_rm_ftz
__nvvm_d2f_rn: nvvm::d2f_rn
__nvvm_d2f_rn_ftz: nvvm::d2f_rn_ftz
__nvvm_d2f_rp: nvvm::d2f_rp
__nvvm_d2f_rp_ftz: nvvm::d2f_rp_ftz
__nvvm_d2f_rz: nvvm::d2f_rz
__nvvm_d2f_rz_ftz: nvvm::d2f_rz_ftz
__nvvm_d2i_hi: nvvm::d2i_hi
__nvvm_d2i_lo: nvvm::d2i_lo
__nvvm_d2i_rm: nvvm::d2i_rm
__nvvm_d2i_rn: nvvm::d2i_rn
__nvvm_d2i_rp: nvvm::d2i_rp
__nvvm_d2i_rz: nvvm::d2i_rz
__nvvm_d2ll_rm: nvvm::d2ll_rm
__nvvm_d2ll_rn: nvvm::d2ll_rn
__nvvm_d2ll_rp: nvvm::d2ll_rp
__nvvm_d2ll_rz: nvvm::d2ll_rz
__nvvm_d2ui_rm: nvvm::d2ui_rm
__nvvm_d2ui_rn: nvvm::d2ui_rn
__nvvm_d2ui_rp: nvvm::d2ui_rp
__nvvm_d2ui_rz: nvvm::d2ui_rz
__nvvm_d2ull_rm: nvvm::d2ull_rm
__nvvm_d2ull_rn: nvvm::d2ull_rn
__nvvm_d2ull_rp: nvvm::d2ull_rp
__nvvm_d2ull_rz: nvvm::d2ull_rz
__nvvm_div_approx_f: nvvm::div_approx_f
__nvvm_div_approx_ftz_f: nvvm::div_approx_ftz_f
__nvvm_div_rm_d: nvvm::div_rm_d
__nvvm_div_rm_f: nvvm::div_rm_f
__nvvm_div_rm_ftz_f: nvvm::div_rm_ftz_f
__nvvm_div_rn_d: nvvm::div_rn_d
__nvvm_div_rn_f: nvvm::div_rn_f
__nvvm_div_rn_ftz_f: nvvm::div_rn_ftz_f
__nvvm_div_rp_d: nvvm::div_rp_d
__nvvm_div_rp_f: nvvm::div_rp_f
__nvvm_div_rp_ftz_f: nvvm::div_rp_ftz_f
__nvvm_div_rz_d: nvvm::div_rz_d
__nvvm_div_rz_f: nvvm::div_rz_f
__nvvm_div_rz_ftz_f: nvvm::div_rz_ftz_f
__nvvm_ex2_approx_d: nvvm::ex2_approx_d
__nvvm_ex2_approx_f: nvvm::ex2_approx_f
__nvvm_ex2_approx_ftz_f: nvvm::ex2_approx_ftz_f
__nvvm_f2h_rn: nvvm::f2h_rn
__nvvm_f2h_rn_ftz: nvvm::f2h_rn_ftz
__nvvm_f2i_rm: nvvm::f2i_rm
__nvvm_f2i_rm_ftz: nvvm::f2i_rm_ftz
__nvvm_f2i_rn: nvvm::f2i_rn
__nvvm_f2i_rn_ftz: nvvm::f2i_rn_ftz
__nvvm_f2i_rp: nvvm::f2i_rp
__nvvm_f2i_rp_ftz: nvvm::f2i_rp_ftz
__nvvm_f2i_rz: nvvm::f2i_rz
__nvvm_f2i_rz_ftz: nvvm::f2i_rz_ftz
__nvvm_f2ll_rm: nvvm::f2ll_rm
__nvvm_f2ll_rm_ftz: nvvm::f2ll_rm_ftz
__nvvm_f2ll_rn: nvvm::f2ll_rn
__nvvm_f2ll_rn_ftz: nvvm::f2ll_rn_ftz
__nvvm_f2ll_rp: nvvm::f2ll_rp
__nvvm_f2ll_rp_ftz: nvvm::f2ll_rp_ftz
__nvvm_f2ll_rz: nvvm::f2ll_rz
__nvvm_f2ll_rz_ftz: nvvm::f2ll_rz_ftz
__nvvm_f2ui_rm: nvvm::f2ui_rm
__nvvm_f2ui_rm_ftz: nvvm::f2ui_rm_ftz
__nvvm_f2ui_rn: nvvm::f2ui_rn
__nvvm_f2ui_rn_ftz: nvvm::f2ui_rn_ftz
__nvvm_f2ui_rp: nvvm::f2ui_rp
__nvvm_f2ui_rp_ftz: nvvm::f2ui_rp_ftz
__nvvm_f2ui_rz: nvvm::f2ui_rz
__nvvm_f2ui_rz_ftz: nvvm::f2ui_rz_ftz
__nvvm_f2ull_rm: nvvm::f2ull_rm
__nvvm_f2ull_rm_ftz: nvvm::f2ull_rm_ftz
__nvvm_f2ull_rn: nvvm::f2ull_rn
__nvvm_f2ull_rn_ftz: nvvm::f2ull_rn_ftz
__nvvm_f2ull_rp: nvvm::f2ull_rp
__nvvm_f2ull_rp_ftz: nvvm::f2ull_rp_ftz
__nvvm_f2ull_rz: nvvm::f2ull_rz
__nvvm_f2ull_rz_ftz: nvvm::f2ull_rz_ftz
__nvvm_fabs_d: nvvm::fabs_d
__nvvm_fabs_f: nvvm::fabs_f
__nvvm_fabs_ftz_f: nvvm::fabs_ftz_f
__nvvm_floor_d: nvvm::floor_d
__nvvm_floor_f: nvvm::floor_f
__nvvm_floor_ftz_f: nvvm::floor_ftz_f
__nvvm_fma_rm_d: nvvm::fma_rm_d
__nvvm_fma_rm_f: nvvm::fma_rm_f
__nvvm_fma_rm_ftz_f: nvvm::fma_rm_ftz_f
__nvvm_fma_rn_d: nvvm::fma_rn_d
__nvvm_fma_rn_f: nvvm::fma_rn_f
__nvvm_fma_rn_ftz_f: nvvm::fma_rn_ftz_f
__nvvm_fma_rp_d: nvvm::fma_rp_d
__nvvm_fma_rp_f: nvvm::fma_rp_f
__nvvm_fma_rp_ftz_f: nvvm::fma_rp_ftz_f
__nvvm_fma_rz_d: nvvm::fma_rz_d
__nvvm_fma_rz_f: nvvm::fma_rz_f
__nvvm_fma_rz_ftz_f: nvvm::fma_rz_ftz_f
__nvvm_fmax_d: nvvm::fmax_d
__nvvm_fmax_f: nvvm::fmax_f
__nvvm_fmax_ftz_f: nvvm::fmax_ftz_f
__nvvm_fmin_d: nvvm::fmin_d
__nvvm_fmin_f: nvvm::fmin_f
__nvvm_fmin_ftz_f: nvvm::fmin_ftz_f
__nvvm_h2f: nvvm::h2f
__nvvm_i2d_rm: nvvm::i2d_rm
__nvvm_i2d_rn: nvvm::i2d_rn
__nvvm_i2d_rp: nvvm::i2d_rp
__nvvm_i2d_rz: nvvm::i2d_rz
__nvvm_i2f_rm: nvvm::i2f_rm
__nvvm_i2f_rn: nvvm::i2f_rn
__nvvm_i2f_rp: nvvm::i2f_rp
__nvvm_i2f_rz: nvvm::i2f_rz
__nvvm_isspacep_const: nvvm::isspacep_const
__nvvm_isspacep_global: nvvm::isspacep_global
__nvvm_isspacep_local: nvvm::isspacep_local
__nvvm_isspacep_shared: nvvm::isspacep_shared
__nvvm_istypep_sampler: nvvm::istypep_sampler
__nvvm_istypep_surface: nvvm::istypep_surface
__nvvm_istypep_texture: nvvm::istypep_texture
__nvvm_lg2_approx_d: nvvm::lg2_approx_d
__nvvm_lg2_approx_f: nvvm::lg2_approx_f
__nvvm_lg2_approx_ftz_f: nvvm::lg2_approx_ftz_f
__nvvm_ll2d_rm: nvvm::ll2d_rm
__nvvm_ll2d_rn: nvvm::ll2d_rn
__nvvm_ll2d_rp: nvvm::ll2d_rp
__nvvm_ll2d_rz: nvvm::ll2d_rz
__nvvm_ll2f_rm: nvvm::ll2f_rm
__nvvm_ll2f_rn: nvvm::ll2f_rn
__nvvm_ll2f_rp: nvvm::ll2f_rp
__nvvm_ll2f_rz: nvvm::ll2f_rz
__nvvm_lohi_i2d: nvvm::lohi_i2d
__nvvm_max_i: nvvm::max_i
__nvvm_max_ll: nvvm::max_ll
__nvvm_max_ui: nvvm::max_ui
__nvvm_max_ull: nvvm::max_ull
__nvvm_membar_cta: nvvm::membar_cta
__nvvm_membar_gl: nvvm::membar_gl
__nvvm_membar_sys: nvvm::membar_sys
__nvvm_min_i: nvvm::min_i
__nvvm_min_ll: nvvm::min_ll
__nvvm_min_ui: nvvm::min_ui
__nvvm_min_ull: nvvm::min_ull
__nvvm_mul24_i: nvvm::mul24_i
__nvvm_mul24_ui: nvvm::mul24_ui
__nvvm_mul_rm_d: nvvm::mul_rm_d
__nvvm_mul_rm_f: nvvm::mul_rm_f
__nvvm_mul_rm_ftz_f: nvvm::mul_rm_ftz_f
__nvvm_mul_rn_d: nvvm::mul_rn_d
__nvvm_mul_rn_f: nvvm::mul_rn_f
__nvvm_mul_rn_ftz_f: nvvm::mul_rn_ftz_f
__nvvm_mul_rp_d: nvvm::mul_rp_d
__nvvm_mul_rp_f: nvvm::mul_rp_f
__nvvm_mul_rp_ftz_f: nvvm::mul_rp_ftz_f
__nvvm_mul_rz_d: nvvm::mul_rz_d
__nvvm_mul_rz_f: nvvm::mul_rz_f
__nvvm_mul_rz_ftz_f: nvvm::mul_rz_ftz_f
__nvvm_mulhi_i: nvvm::mulhi_i
__nvvm_mulhi_ll: nvvm::mulhi_ll
__nvvm_mulhi_ui: nvvm::mulhi_ui
__nvvm_mulhi_ull: nvvm::mulhi_ull
__nvvm_popc_i: nvvm::popc_i
__nvvm_popc_ll: nvvm::popc_ll
__nvvm_prmt: nvvm::prmt
__nvvm_rcp_approx_ftz_d: nvvm::rcp_approx_ftz_d
__nvvm_rcp_rm_d: nvvm::rcp_rm_d
__nvvm_rcp_rm_f: nvvm::rcp_rm_f
__nvvm_rcp_rm_ftz_f: nvvm::rcp_rm_ftz_f
__nvvm_rcp_rn_d: nvvm::rcp_rn_d
__nvvm_rcp_rn_f: nvvm::rcp_rn_f
__nvvm_rcp_rn_ftz_f: nvvm::rcp_rn_ftz_f
__nvvm_rcp_rp_d: nvvm::rcp_rp_d
__nvvm_rcp_rp_f: nvvm::rcp_rp_f
__nvvm_rcp_rp_ftz_f: nvvm::rcp_rp_ftz_f
__nvvm_rcp_rz_d: nvvm::rcp_rz_d
__nvvm_rcp_rz_f: nvvm::rcp_rz_f
__nvvm_rcp_rz_ftz_f: nvvm::rcp_rz_ftz_f
__nvvm_read_ptx_sreg_: nvvm::read_ptx_sreg_laneid; nvvm::read_ptx_sreg_warpid; nvvm::read_ptx_sreg_nwarpid; nvvm::read_ptx_sreg_smid; nvvm::read_ptx_sreg_nsmid; nvvm::read_ptx_sreg_gridid; nvvm::read_ptx_sreg_lanemask_eq; nvvm::read_ptx_sreg_lanemask_le; nvvm::read_ptx_sreg_lanemask_lt; nvvm::read_ptx_sreg_lanemask_ge; nvvm::read_ptx_sreg_lanemask_gt; nvvm::read_ptx_sreg_clock; nvvm::read_ptx_sreg_clock64; nvvm::read_ptx_sreg_pm0; nvvm::read_ptx_sreg_pm1; nvvm::read_ptx_sreg_pm2; nvvm::read_ptx_sreg_pm3; nvvm::read_ptx_sreg_warpsize
__nvvm_read_ptx_sreg_envreg0: nvvm::read_ptx_sreg_envreg0
__nvvm_read_ptx_sreg_envreg1: nvvm::read_ptx_sreg_envreg1
__nvvm_read_ptx_sreg_envreg10: nvvm::read_ptx_sreg_envreg10
__nvvm_read_ptx_sreg_envreg11: nvvm::read_ptx_sreg_envreg11
__nvvm_read_ptx_sreg_envreg12: nvvm::read_ptx_sreg_envreg12
__nvvm_read_ptx_sreg_envreg13: nvvm::read_ptx_sreg_envreg13
__nvvm_read_ptx_sreg_envreg14: nvvm::read_ptx_sreg_envreg14
__nvvm_read_ptx_sreg_envreg15: nvvm::read_ptx_sreg_envreg15
__nvvm_read_ptx_sreg_envreg16: nvvm::read_ptx_sreg_envreg16
__nvvm_read_ptx_sreg_envreg17: nvvm::read_ptx_sreg_envreg17
__nvvm_read_ptx_sreg_envreg18: nvvm::read_ptx_sreg_envreg18
__nvvm_read_ptx_sreg_envreg19: nvvm::read_ptx_sreg_envreg19
__nvvm_read_ptx_sreg_envreg2: nvvm::read_ptx_sreg_envreg2
__nvvm_read_ptx_sreg_envreg20: nvvm::read_ptx_sreg_envreg20
__nvvm_read_ptx_sreg_envreg21: nvvm::read_ptx_sreg_envreg21
__nvvm_read_ptx_sreg_envreg22: nvvm::read_ptx_sreg_envreg22
__nvvm_read_ptx_sreg_envreg23: nvvm::read_ptx_sreg_envreg23
__nvvm_read_ptx_sreg_envreg24: nvvm::read_ptx_sreg_envreg24
__nvvm_read_ptx_sreg_envreg25: nvvm::read_ptx_sreg_envreg25
__nvvm_read_ptx_sreg_envreg26: nvvm::read_ptx_sreg_envreg26
__nvvm_read_ptx_sreg_envreg27: nvvm::read_ptx_sreg_envreg27
__nvvm_read_ptx_sreg_envreg28: nvvm::read_ptx_sreg_envreg28
__nvvm_read_ptx_sreg_envreg29: nvvm::read_ptx_sreg_envreg29
__nvvm_read_ptx_sreg_envreg3: nvvm::read_ptx_sreg_envreg3
__nvvm_read_ptx_sreg_envreg30: nvvm::read_ptx_sreg_envreg30
__nvvm_read_ptx_sreg_envreg31: nvvm::read_ptx_sreg_envreg31
__nvvm_read_ptx_sreg_envreg4: nvvm::read_ptx_sreg_envreg4
__nvvm_read_ptx_sreg_envreg5: nvvm::read_ptx_sreg_envreg5
__nvvm_read_ptx_sreg_envreg6: nvvm::read_ptx_sreg_envreg6
__nvvm_read_ptx_sreg_envreg7: nvvm::read_ptx_sreg_envreg7
__nvvm_read_ptx_sreg_envreg8: nvvm::read_ptx_sreg_envreg8
__nvvm_read_ptx_sreg_envreg9: nvvm::read_ptx_sreg_envreg9
__nvvm_rotate_b32: nvvm::rotate_b32
__nvvm_rotate_b64: nvvm::rotate_b64
__nvvm_rotate_right_b64: nvvm::rotate_right_b64
__nvvm_round_d: nvvm::round_d
__nvvm_round_f: nvvm::round_f
__nvvm_round_ftz_f: nvvm::round_ftz_f
__nvvm_rsqrt_approx_d: nvvm::rsqrt_approx_d
__nvvm_rsqrt_approx_f: nvvm::rsqrt_approx_f
__nvvm_rsqrt_approx_ftz_f: nvvm::rsqrt_approx_ftz_f
__nvvm_sad_i: nvvm::sad_i
__nvvm_sad_ui: nvvm::sad_ui
__nvvm_saturate_d: nvvm::saturate_d
__nvvm_saturate_f: nvvm::saturate_f
__nvvm_saturate_ftz_f: nvvm::saturate_ftz_f
__nvvm_shfl_bfly_f32: nvvm::shfl_bfly_f32
__nvvm_shfl_bfly_i32: nvvm::shfl_bfly_i32
__nvvm_shfl_down_f32: nvvm::shfl_down_f32
__nvvm_shfl_down_i32: nvvm::shfl_down_i32
__nvvm_shfl_idx_f32: nvvm::shfl_idx_f32
__nvvm_shfl_idx_i32: nvvm::shfl_idx_i32
__nvvm_shfl_up_f32: nvvm::shfl_up_f32
__nvvm_shfl_up_i32: nvvm::shfl_up_i32
__nvvm_sin_approx_f: nvvm::sin_approx_f
__nvvm_sin_approx_ftz_f: nvvm::sin_approx_ftz_f
__nvvm_sqrt_approx_f: nvvm::sqrt_approx_f
__nvvm_sqrt_approx_ftz_f: nvvm::sqrt_approx_ftz_f
__nvvm_sqrt_f: nvvm::sqrt_f
__nvvm_sqrt_rm_d: nvvm::sqrt_rm_d
__nvvm_sqrt_rm_f: nvvm::sqrt_rm_f
__nvvm_sqrt_rm_ftz_f: nvvm::sqrt_rm_ftz_f
__nvvm_sqrt_rn_d: nvvm::sqrt_rn_d
__nvvm_sqrt_rn_f: nvvm::sqrt_rn_f
__nvvm_sqrt_rn_ftz_f: nvvm::sqrt_rn_ftz_f
__nvvm_sqrt_rp_d: nvvm::sqrt_rp_d
__nvvm_sqrt_rp_f: nvvm::sqrt_rp_f
__nvvm_sqrt_rp_ftz_f: nvvm::sqrt_rp_ftz_f
__nvvm_sqrt_rz_d: nvvm::sqrt_rz_d
__nvvm_sqrt_rz_f: nvvm::sqrt_rz_f
__nvvm_sqrt_rz_ftz_f: nvvm::sqrt_rz_ftz_f
__nvvm_suq_array_size: nvvm::suq_array_size
__nvvm_suq_channel_data_type: nvvm::suq_channel_data_type
__nvvm_suq_channel_order: nvvm::suq_channel_order
__nvvm_suq_depth: nvvm::suq_depth
__nvvm_suq_height: nvvm::suq_height
__nvvm_suq_width: nvvm::suq_width
__nvvm_sust_b_1d_array_i16_clamp: nvvm::sust_b_1d_array_i16_clamp
__nvvm_sust_b_1d_array_i16_trap: nvvm::sust_b_1d_array_i16_trap
__nvvm_sust_b_1d_array_i16_zero: nvvm::sust_b_1d_array_i16_zero
__nvvm_sust_b_1d_array_i32_clamp: nvvm::sust_b_1d_array_i32_clamp
__nvvm_sust_b_1d_array_i32_trap: nvvm::sust_b_1d_array_i32_trap
__nvvm_sust_b_1d_array_i32_zero: nvvm::sust_b_1d_array_i32_zero
__nvvm_sust_b_1d_array_i64_clamp: nvvm::sust_b_1d_array_i64_clamp
__nvvm_sust_b_1d_array_i64_trap: nvvm::sust_b_1d_array_i64_trap
__nvvm_sust_b_1d_array_i64_zero: nvvm::sust_b_1d_array_i64_zero
__nvvm_sust_b_1d_array_i8_clamp: nvvm::sust_b_1d_array_i8_clamp
__nvvm_sust_b_1d_array_i8_trap: nvvm::sust_b_1d_array_i8_trap
__nvvm_sust_b_1d_array_i8_zero: nvvm::sust_b_1d_array_i8_zero
__nvvm_sust_b_1d_array_v2i16_clamp: nvvm::sust_b_1d_array_v2i16_clamp
__nvvm_sust_b_1d_array_v2i16_trap: nvvm::sust_b_1d_array_v2i16_trap
__nvvm_sust_b_1d_array_v2i16_zero: nvvm::sust_b_1d_array_v2i16_zero
__nvvm_sust_b_1d_array_v2i32_clamp: nvvm::sust_b_1d_array_v2i32_clamp
__nvvm_sust_b_1d_array_v2i32_trap: nvvm::sust_b_1d_array_v2i32_trap
__nvvm_sust_b_1d_array_v2i32_zero: nvvm::sust_b_1d_array_v2i32_zero
__nvvm_sust_b_1d_array_v2i64_clamp: nvvm::sust_b_1d_array_v2i64_clamp
__nvvm_sust_b_1d_array_v2i64_trap: nvvm::sust_b_1d_array_v2i64_trap
__nvvm_sust_b_1d_array_v2i64_zero: nvvm::sust_b_1d_array_v2i64_zero
__nvvm_sust_b_1d_array_v2i8_clamp: nvvm::sust_b_1d_array_v2i8_clamp
__nvvm_sust_b_1d_array_v2i8_trap: nvvm::sust_b_1d_array_v2i8_trap
__nvvm_sust_b_1d_array_v2i8_zero: nvvm::sust_b_1d_array_v2i8_zero
__nvvm_sust_b_1d_array_v4i16_clamp: nvvm::sust_b_1d_array_v4i16_clamp
__nvvm_sust_b_1d_array_v4i16_trap: nvvm::sust_b_1d_array_v4i16_trap
__nvvm_sust_b_1d_array_v4i16_zero: nvvm::sust_b_1d_array_v4i16_zero
__nvvm_sust_b_1d_array_v4i32_clamp: nvvm::sust_b_1d_array_v4i32_clamp
__nvvm_sust_b_1d_array_v4i32_trap: nvvm::sust_b_1d_array_v4i32_trap
__nvvm_sust_b_1d_array_v4i32_zero: nvvm::sust_b_1d_array_v4i32_zero
__nvvm_sust_b_1d_array_v4i8_clamp: nvvm::sust_b_1d_array_v4i8_clamp
__nvvm_sust_b_1d_array_v4i8_trap: nvvm::sust_b_1d_array_v4i8_trap
__nvvm_sust_b_1d_array_v4i8_zero: nvvm::sust_b_1d_array_v4i8_zero
__nvvm_sust_b_1d_i16_clamp: nvvm::sust_b_1d_i16_clamp
__nvvm_sust_b_1d_i16_trap: nvvm::sust_b_1d_i16_trap
__nvvm_sust_b_1d_i16_zero: nvvm::sust_b_1d_i16_zero
__nvvm_sust_b_1d_i32_clamp: nvvm::sust_b_1d_i32_clamp
__nvvm_sust_b_1d_i32_trap: nvvm::sust_b_1d_i32_trap
__nvvm_sust_b_1d_i32_zero: nvvm::sust_b_1d_i32_zero
__nvvm_sust_b_1d_i64_clamp: nvvm::sust_b_1d_i64_clamp
__nvvm_sust_b_1d_i64_trap: nvvm::sust_b_1d_i64_trap
__nvvm_sust_b_1d_i64_zero: nvvm::sust_b_1d_i64_zero
__nvvm_sust_b_1d_i8_clamp: nvvm::sust_b_1d_i8_clamp
__nvvm_sust_b_1d_i8_trap: nvvm::sust_b_1d_i8_trap
__nvvm_sust_b_1d_i8_zero: nvvm::sust_b_1d_i8_zero
__nvvm_sust_b_1d_v2i16_clamp: nvvm::sust_b_1d_v2i16_clamp
__nvvm_sust_b_1d_v2i16_trap: nvvm::sust_b_1d_v2i16_trap
__nvvm_sust_b_1d_v2i16_zero: nvvm::sust_b_1d_v2i16_zero
__nvvm_sust_b_1d_v2i32_clamp: nvvm::sust_b_1d_v2i32_clamp
__nvvm_sust_b_1d_v2i32_trap: nvvm::sust_b_1d_v2i32_trap
__nvvm_sust_b_1d_v2i32_zero: nvvm::sust_b_1d_v2i32_zero
__nvvm_sust_b_1d_v2i64_clamp: nvvm::sust_b_1d_v2i64_clamp
__nvvm_sust_b_1d_v2i64_trap: nvvm::sust_b_1d_v2i64_trap
__nvvm_sust_b_1d_v2i64_zero: nvvm::sust_b_1d_v2i64_zero
__nvvm_sust_b_1d_v2i8_clamp: nvvm::sust_b_1d_v2i8_clamp
__nvvm_sust_b_1d_v2i8_trap: nvvm::sust_b_1d_v2i8_trap
__nvvm_sust_b_1d_v2i8_zero: nvvm::sust_b_1d_v2i8_zero
__nvvm_sust_b_1d_v4i16_clamp: nvvm::sust_b_1d_v4i16_clamp
__nvvm_sust_b_1d_v4i16_trap: nvvm::sust_b_1d_v4i16_trap
__nvvm_sust_b_1d_v4i16_zero: nvvm::sust_b_1d_v4i16_zero
__nvvm_sust_b_1d_v4i32_clamp: nvvm::sust_b_1d_v4i32_clamp
__nvvm_sust_b_1d_v4i32_trap: nvvm::sust_b_1d_v4i32_trap
__nvvm_sust_b_1d_v4i32_zero: nvvm::sust_b_1d_v4i32_zero
__nvvm_sust_b_1d_v4i8_clamp: nvvm::sust_b_1d_v4i8_clamp
__nvvm_sust_b_1d_v4i8_trap: nvvm::sust_b_1d_v4i8_trap
__nvvm_sust_b_1d_v4i8_zero: nvvm::sust_b_1d_v4i8_zero
__nvvm_sust_b_2d_array_i16_clamp: nvvm::sust_b_2d_array_i16_clamp
__nvvm_sust_b_2d_array_i16_trap: nvvm::sust_b_2d_array_i16_trap
__nvvm_sust_b_2d_array_i16_zero: nvvm::sust_b_2d_array_i16_zero
__nvvm_sust_b_2d_array_i32_clamp: nvvm::sust_b_2d_array_i32_clamp
__nvvm_sust_b_2d_array_i32_trap: nvvm::sust_b_2d_array_i32_trap
__nvvm_sust_b_2d_array_i32_zero: nvvm::sust_b_2d_array_i32_zero
__nvvm_sust_b_2d_array_i64_clamp: nvvm::sust_b_2d_array_i64_clamp
__nvvm_sust_b_2d_array_i64_trap: nvvm::sust_b_2d_array_i64_trap
__nvvm_sust_b_2d_array_i64_zero: nvvm::sust_b_2d_array_i64_zero
__nvvm_sust_b_2d_array_i8_clamp: nvvm::sust_b_2d_array_i8_clamp
__nvvm_sust_b_2d_array_i8_trap: nvvm::sust_b_2d_array_i8_trap
__nvvm_sust_b_2d_array_i8_zero: nvvm::sust_b_2d_array_i8_zero
__nvvm_sust_b_2d_array_v2i16_clamp: nvvm::sust_b_2d_array_v2i16_clamp
__nvvm_sust_b_2d_array_v2i16_trap: nvvm::sust_b_2d_array_v2i16_trap
__nvvm_sust_b_2d_array_v2i16_zero: nvvm::sust_b_2d_array_v2i16_zero
__nvvm_sust_b_2d_array_v2i32_clamp: nvvm::sust_b_2d_array_v2i32_clamp
__nvvm_sust_b_2d_array_v2i32_trap: nvvm::sust_b_2d_array_v2i32_trap
__nvvm_sust_b_2d_array_v2i32_zero: nvvm::sust_b_2d_array_v2i32_zero
__nvvm_sust_b_2d_array_v2i64_clamp: nvvm::sust_b_2d_array_v2i64_clamp
__nvvm_sust_b_2d_array_v2i64_trap: nvvm::sust_b_2d_array_v2i64_trap
__nvvm_sust_b_2d_array_v2i64_zero: nvvm::sust_b_2d_array_v2i64_zero
__nvvm_sust_b_2d_array_v2i8_clamp: nvvm::sust_b_2d_array_v2i8_clamp
__nvvm_sust_b_2d_array_v2i8_trap: nvvm::sust_b_2d_array_v2i8_trap
__nvvm_sust_b_2d_array_v2i8_zero: nvvm::sust_b_2d_array_v2i8_zero
__nvvm_sust_b_2d_array_v4i16_clamp: nvvm::sust_b_2d_array_v4i16_clamp
__nvvm_sust_b_2d_array_v4i16_trap: nvvm::sust_b_2d_array_v4i16_trap
__nvvm_sust_b_2d_array_v4i16_zero: nvvm::sust_b_2d_array_v4i16_zero
__nvvm_sust_b_2d_array_v4i32_clamp: nvvm::sust_b_2d_array_v4i32_clamp
__nvvm_sust_b_2d_array_v4i32_trap: nvvm::sust_b_2d_array_v4i32_trap
__nvvm_sust_b_2d_array_v4i32_zero: nvvm::sust_b_2d_array_v4i32_zero
__nvvm_sust_b_2d_array_v4i8_clamp: nvvm::sust_b_2d_array_v4i8_clamp
__nvvm_sust_b_2d_array_v4i8_trap: nvvm::sust_b_2d_array_v4i8_trap
__nvvm_sust_b_2d_array_v4i8_zero: nvvm::sust_b_2d_array_v4i8_zero
__nvvm_sust_b_2d_i16_clamp: nvvm::sust_b_2d_i16_clamp
__nvvm_sust_b_2d_i16_trap: nvvm::sust_b_2d_i16_trap
__nvvm_sust_b_2d_i16_zero: nvvm::sust_b_2d_i16_zero
__nvvm_sust_b_2d_i32_clamp: nvvm::sust_b_2d_i32_clamp
__nvvm_sust_b_2d_i32_trap: nvvm::sust_b_2d_i32_trap
__nvvm_sust_b_2d_i32_zero: nvvm::sust_b_2d_i32_zero
__nvvm_sust_b_2d_i64_clamp: nvvm::sust_b_2d_i64_clamp
__nvvm_sust_b_2d_i64_trap: nvvm::sust_b_2d_i64_trap
__nvvm_sust_b_2d_i64_zero: nvvm::sust_b_2d_i64_zero
__nvvm_sust_b_2d_i8_clamp: nvvm::sust_b_2d_i8_clamp
__nvvm_sust_b_2d_i8_trap: nvvm::sust_b_2d_i8_trap
__nvvm_sust_b_2d_i8_zero: nvvm::sust_b_2d_i8_zero
__nvvm_sust_b_2d_v2i16_clamp: nvvm::sust_b_2d_v2i16_clamp
__nvvm_sust_b_2d_v2i16_trap: nvvm::sust_b_2d_v2i16_trap
__nvvm_sust_b_2d_v2i16_zero: nvvm::sust_b_2d_v2i16_zero
__nvvm_sust_b_2d_v2i32_clamp: nvvm::sust_b_2d_v2i32_clamp
__nvvm_sust_b_2d_v2i32_trap: nvvm::sust_b_2d_v2i32_trap
__nvvm_sust_b_2d_v2i32_zero: nvvm::sust_b_2d_v2i32_zero
__nvvm_sust_b_2d_v2i64_clamp: nvvm::sust_b_2d_v2i64_clamp
__nvvm_sust_b_2d_v2i64_trap: nvvm::sust_b_2d_v2i64_trap
__nvvm_sust_b_2d_v2i64_zero: nvvm::sust_b_2d_v2i64_zero
__nvvm_sust_b_2d_v2i8_clamp: nvvm::sust_b_2d_v2i8_clamp
__nvvm_sust_b_2d_v2i8_trap: nvvm::sust_b_2d_v2i8_trap
__nvvm_sust_b_2d_v2i8_zero: nvvm::sust_b_2d_v2i8_zero
__nvvm_sust_b_2d_v4i16_clamp: nvvm::sust_b_2d_v4i16_clamp
__nvvm_sust_b_2d_v4i16_trap: nvvm::sust_b_2d_v4i16_trap
__nvvm_sust_b_2d_v4i16_zero: nvvm::sust_b_2d_v4i16_zero
__nvvm_sust_b_2d_v4i32_clamp: nvvm::sust_b_2d_v4i32_clamp
__nvvm_sust_b_2d_v4i32_trap: nvvm::sust_b_2d_v4i32_trap
__nvvm_sust_b_2d_v4i32_zero: nvvm::sust_b_2d_v4i32_zero
__nvvm_sust_b_2d_v4i8_clamp: nvvm::sust_b_2d_v4i8_clamp
__nvvm_sust_b_2d_v4i8_trap: nvvm::sust_b_2d_v4i8_trap
__nvvm_sust_b_2d_v4i8_zero: nvvm::sust_b_2d_v4i8_zero
__nvvm_sust_b_3d_i16_clamp: nvvm::sust_b_3d_i16_clamp
__nvvm_sust_b_3d_i16_trap: nvvm::sust_b_3d_i16_trap
__nvvm_sust_b_3d_i16_zero: nvvm::sust_b_3d_i16_zero
__nvvm_sust_b_3d_i32_clamp: nvvm::sust_b_3d_i32_clamp
__nvvm_sust_b_3d_i32_trap: nvvm::sust_b_3d_i32_trap
__nvvm_sust_b_3d_i32_zero: nvvm::sust_b_3d_i32_zero
__nvvm_sust_b_3d_i64_clamp: nvvm::sust_b_3d_i64_clamp
__nvvm_sust_b_3d_i64_trap: nvvm::sust_b_3d_i64_trap
__nvvm_sust_b_3d_i64_zero: nvvm::sust_b_3d_i64_zero
__nvvm_sust_b_3d_i8_clamp: nvvm::sust_b_3d_i8_clamp
__nvvm_sust_b_3d_i8_trap: nvvm::sust_b_3d_i8_trap
__nvvm_sust_b_3d_i8_zero: nvvm::sust_b_3d_i8_zero
__nvvm_sust_b_3d_v2i16_clamp: nvvm::sust_b_3d_v2i16_clamp
__nvvm_sust_b_3d_v2i16_trap: nvvm::sust_b_3d_v2i16_trap
__nvvm_sust_b_3d_v2i16_zero: nvvm::sust_b_3d_v2i16_zero
__nvvm_sust_b_3d_v2i32_clamp: nvvm::sust_b_3d_v2i32_clamp
__nvvm_sust_b_3d_v2i32_trap: nvvm::sust_b_3d_v2i32_trap
__nvvm_sust_b_3d_v2i32_zero: nvvm::sust_b_3d_v2i32_zero
__nvvm_sust_b_3d_v2i64_clamp: nvvm::sust_b_3d_v2i64_clamp
__nvvm_sust_b_3d_v2i64_trap: nvvm::sust_b_3d_v2i64_trap
__nvvm_sust_b_3d_v2i64_zero: nvvm::sust_b_3d_v2i64_zero
__nvvm_sust_b_3d_v2i8_clamp: nvvm::sust_b_3d_v2i8_clamp
__nvvm_sust_b_3d_v2i8_trap: nvvm::sust_b_3d_v2i8_trap
__nvvm_sust_b_3d_v2i8_zero: nvvm::sust_b_3d_v2i8_zero
__nvvm_sust_b_3d_v4i16_clamp: nvvm::sust_b_3d_v4i16_clamp
__nvvm_sust_b_3d_v4i16_trap: nvvm::sust_b_3d_v4i16_trap
__nvvm_sust_b_3d_v4i16_zero: nvvm::sust_b_3d_v4i16_zero
__nvvm_sust_b_3d_v4i32_clamp: nvvm::sust_b_3d_v4i32_clamp
__nvvm_sust_b_3d_v4i32_trap: nvvm::sust_b_3d_v4i32_trap
__nvvm_sust_b_3d_v4i32_zero: nvvm::sust_b_3d_v4i32_zero
__nvvm_sust_b_3d_v4i8_clamp: nvvm::sust_b_3d_v4i8_clamp
__nvvm_sust_b_3d_v4i8_trap: nvvm::sust_b_3d_v4i8_trap
__nvvm_sust_b_3d_v4i8_zero: nvvm::sust_b_3d_v4i8_zero
__nvvm_sust_p_1d_array_i16_trap: nvvm::sust_p_1d_array_i16_trap
__nvvm_sust_p_1d_array_i32_trap: nvvm::sust_p_1d_array_i32_trap
__nvvm_sust_p_1d_array_i8_trap: nvvm::sust_p_1d_array_i8_trap
__nvvm_sust_p_1d_array_v2i16_trap: nvvm::sust_p_1d_array_v2i16_trap
__nvvm_sust_p_1d_array_v2i32_trap: nvvm::sust_p_1d_array_v2i32_trap
__nvvm_sust_p_1d_array_v2i8_trap: nvvm::sust_p_1d_array_v2i8_trap
__nvvm_sust_p_1d_array_v4i16_trap: nvvm::sust_p_1d_array_v4i16_trap
__nvvm_sust_p_1d_array_v4i32_trap: nvvm::sust_p_1d_array_v4i32_trap
__nvvm_sust_p_1d_array_v4i8_trap: nvvm::sust_p_1d_array_v4i8_trap
__nvvm_sust_p_1d_i16_trap: nvvm::sust_p_1d_i16_trap
__nvvm_sust_p_1d_i32_trap: nvvm::sust_p_1d_i32_trap
__nvvm_sust_p_1d_i8_trap: nvvm::sust_p_1d_i8_trap
__nvvm_sust_p_1d_v2i16_trap: nvvm::sust_p_1d_v2i16_trap
__nvvm_sust_p_1d_v2i32_trap: nvvm::sust_p_1d_v2i32_trap
__nvvm_sust_p_1d_v2i8_trap: nvvm::sust_p_1d_v2i8_trap
__nvvm_sust_p_1d_v4i16_trap: nvvm::sust_p_1d_v4i16_trap
__nvvm_sust_p_1d_v4i32_trap: nvvm::sust_p_1d_v4i32_trap
__nvvm_sust_p_1d_v4i8_trap: nvvm::sust_p_1d_v4i8_trap
__nvvm_sust_p_2d_array_i16_trap: nvvm::sust_p_2d_array_i16_trap
__nvvm_sust_p_2d_array_i32_trap: nvvm::sust_p_2d_array_i32_trap
__nvvm_sust_p_2d_array_i8_trap: nvvm::sust_p_2d_array_i8_trap
__nvvm_sust_p_2d_array_v2i16_trap: nvvm::sust_p_2d_array_v2i16_trap
__nvvm_sust_p_2d_array_v2i32_trap: nvvm::sust_p_2d_array_v2i32_trap
__nvvm_sust_p_2d_array_v2i8_trap: nvvm::sust_p_2d_array_v2i8_trap
__nvvm_sust_p_2d_array_v4i16_trap: nvvm::sust_p_2d_array_v4i16_trap
__nvvm_sust_p_2d_array_v4i32_trap: nvvm::sust_p_2d_array_v4i32_trap
__nvvm_sust_p_2d_array_v4i8_trap: nvvm::sust_p_2d_array_v4i8_trap
__nvvm_sust_p_2d_i16_trap: nvvm::sust_p_2d_i16_trap
__nvvm_sust_p_2d_i32_trap: nvvm::sust_p_2d_i32_trap
__nvvm_sust_p_2d_i8_trap: nvvm::sust_p_2d_i8_trap
__nvvm_sust_p_2d_v2i16_trap: nvvm::sust_p_2d_v2i16_trap
__nvvm_sust_p_2d_v2i32_trap: nvvm::sust_p_2d_v2i32_trap
__nvvm_sust_p_2d_v2i8_trap: nvvm::sust_p_2d_v2i8_trap
__nvvm_sust_p_2d_v4i16_trap: nvvm::sust_p_2d_v4i16_trap
__nvvm_sust_p_2d_v4i32_trap: nvvm::sust_p_2d_v4i32_trap
__nvvm_sust_p_2d_v4i8_trap: nvvm::sust_p_2d_v4i8_trap
__nvvm_sust_p_3d_i16_trap: nvvm::sust_p_3d_i16_trap
__nvvm_sust_p_3d_i32_trap: nvvm::sust_p_3d_i32_trap
__nvvm_sust_p_3d_i8_trap: nvvm::sust_p_3d_i8_trap
__nvvm_sust_p_3d_v2i16_trap: nvvm::sust_p_3d_v2i16_trap
__nvvm_sust_p_3d_v2i32_trap: nvvm::sust_p_3d_v2i32_trap
__nvvm_sust_p_3d_v2i8_trap: nvvm::sust_p_3d_v2i8_trap
__nvvm_sust_p_3d_v4i16_trap: nvvm::sust_p_3d_v4i16_trap
__nvvm_sust_p_3d_v4i32_trap: nvvm::sust_p_3d_v4i32_trap
__nvvm_sust_p_3d_v4i8_trap: nvvm::sust_p_3d_v4i8_trap
__nvvm_swap_lo_hi_b64: nvvm::swap_lo_hi_b64
__nvvm_trunc_d: nvvm::trunc_d
__nvvm_trunc_f: nvvm::trunc_f
__nvvm_trunc_ftz_f: nvvm::trunc_ftz_f
__nvvm_txq_array_size: nvvm::txq_array_size
__nvvm_txq_channel_data_type: nvvm::txq_channel_data_type
__nvvm_txq_channel_order: nvvm::txq_channel_order
__nvvm_txq_depth: nvvm::txq_depth
__nvvm_txq_height: nvvm::txq_height
__nvvm_txq_num_mipmap_levels: nvvm::txq_num_mipmap_levels
__nvvm_txq_num_samples: nvvm::txq_num_samples
__nvvm_txq_width: nvvm::txq_width
__nvvm_ui2d_rm: nvvm::ui2d_rm
__nvvm_ui2d_rn: nvvm::ui2d_rn
__nvvm_ui2d_rp: nvvm::ui2d_rp
__nvvm_ui2d_rz: nvvm::ui2d_rz
__nvvm_ui2f_rm: nvvm::ui2f_rm
__nvvm_ui2f_rn: nvvm::ui2f_rn
__nvvm_ui2f_rp: nvvm::ui2f_rp
__nvvm_ui2f_rz: nvvm::ui2f_rz
__nvvm_ull2d_rm: nvvm::ull2d_rm
__nvvm_ull2d_rn: nvvm::ull2d_rn
__nvvm_ull2d_rp: nvvm::ull2d_rp
__nvvm_ull2d_rz: nvvm::ull2d_rz
__nvvm_ull2f_rm: nvvm::ull2f_rm
__nvvm_ull2f_rn: nvvm::ull2f_rn
__nvvm_ull2f_rp: nvvm::ull2f_rp
__nvvm_ull2f_rz: nvvm::ull2f_rz
__syncthreads: nvvm::barrier0