libreda_db/netlist/
mod.rs

1// Copyright (c) 2020-2021 Thomas Kramer.
2// SPDX-FileCopyrightText: 2022 Thomas Kramer
3//
4// SPDX-License-Identifier: AGPL-3.0-or-later
5
6//! Traits for representation of circuit-level netlists.
7//!
8//! A netlist represents the connections of electrical components (here called 'circuits')
9//! such as standard-cells or macro blocks. Each of the circuits can be composed of instances of
10//! other circuits (recursion is not allowed).
11//! A circuit serves as a template for circuit instances. The circuit defines 'pins' which represent
12//! the electrical connectors to the circuit. Pins can be connected electrically by 'nets' which represent
13//! an electrical potential like a metal wire. Nets are local to a circuit.
14//!
15//! The way a netlist can be accessed and modified is defined by the following two traits:
16//! * [`NetlistBase`] defines basic functions for accessing and traversing a netlist.
17//! * [`NetlistEdit`] defines basic functions for building and modifying a netlist.
18//!
19//! The [`Chip`] data structure implements the both traits.
20//!
21//! [`Chip`]: crate::chip::Chip
22//! [`NetlistBase`]: trait@traits::NetlistBase
23//! [`NetlistEdit`]: trait@traits::NetlistEdit
24
25pub mod arc_id;
26pub mod direction;
27pub mod io;
28pub mod prelude;
29pub mod terminal_id;
30pub mod traits;
31pub mod util;