Crate libopencm3_sys[][src]

Modules

raw_c_types

Structs

__BindgenBitfieldUnit
__IncompleteArrayField
_usbd_device
_usbd_driver
_usbd_mass_storage
max_align_t
scb_exception_stack_frame
usb_audio_feature_unit_descriptor_2ch
usb_audio_feature_unit_descriptor_body
usb_audio_feature_unit_descriptor_head
usb_audio_feature_unit_descriptor_tail
usb_audio_format_continuous_sampling_frequency
usb_audio_format_discrete_sampling_frequency
usb_audio_format_type1_descriptor_1freq
usb_audio_format_type1_descriptor_head
usb_audio_header_descriptor_body
usb_audio_header_descriptor_head
usb_audio_input_terminal_descriptor
usb_audio_output_terminal_descriptor
usb_audio_stream_audio_endpoint_descriptor
usb_audio_stream_endpoint_descriptor
usb_audio_stream_interface_descriptor
usb_cdc_acm_descriptor
usb_cdc_call_management_descriptor
usb_cdc_header_descriptor
usb_cdc_line_coding
usb_cdc_notification
usb_cdc_union_descriptor
usb_config_descriptor
usb_device_descriptor
usb_device_qualifier_descriptor
usb_dfu_descriptor
usb_endpoint_descriptor
usb_hid_descriptor
usb_iface_assoc_descriptor
usb_interface
usb_interface_descriptor
usb_midi_element_descriptor
usb_midi_element_descriptor_body
usb_midi_element_descriptor_head
usb_midi_element_descriptor_tail
usb_midi_endpoint_descriptor
usb_midi_endpoint_descriptor_body
usb_midi_endpoint_descriptor_head
usb_midi_header_descriptor
usb_midi_in_jack_descriptor
usb_midi_out_jack_descriptor
usb_midi_out_jack_descriptor_body
usb_midi_out_jack_descriptor_head
usb_midi_out_jack_descriptor_tail
usb_setup_data
usb_string_descriptor
vector_table_t

Constants

ADC1
ADC2
ADC3
ADC1_BASE
ADC2_BASE
ADC3_BASE
ADC_ADC2DATA_LSB
ADC_ADC2DATA_MSK
ADC_CHANNEL0
ADC_CHANNEL1
ADC_CHANNEL2
ADC_CHANNEL3
ADC_CHANNEL4
ADC_CHANNEL5
ADC_CHANNEL6
ADC_CHANNEL7
ADC_CHANNEL8
ADC_CHANNEL9
ADC_CHANNEL10
ADC_CHANNEL11
ADC_CHANNEL12
ADC_CHANNEL13
ADC_CHANNEL14
ADC_CHANNEL15
ADC_CHANNEL16
ADC_CHANNEL17
ADC_CHANNEL18
ADC_CHANNEL_MASK
ADC_CHANNEL_TEMP
ADC_CHANNEL_VREF
ADC_CR1_AWDCH_CHANNEL0
ADC_CR1_AWDCH_CHANNEL1
ADC_CR1_AWDCH_CHANNEL2
ADC_CR1_AWDCH_CHANNEL3
ADC_CR1_AWDCH_CHANNEL4
ADC_CR1_AWDCH_CHANNEL5
ADC_CR1_AWDCH_CHANNEL6
ADC_CR1_AWDCH_CHANNEL7
ADC_CR1_AWDCH_CHANNEL8
ADC_CR1_AWDCH_CHANNEL9
ADC_CR1_AWDCH_CHANNEL10
ADC_CR1_AWDCH_CHANNEL11
ADC_CR1_AWDCH_CHANNEL12
ADC_CR1_AWDCH_CHANNEL13
ADC_CR1_AWDCH_CHANNEL14
ADC_CR1_AWDCH_CHANNEL15
ADC_CR1_AWDCH_CHANNEL16
ADC_CR1_AWDCH_CHANNEL17
ADC_CR1_AWDCH_MASK
ADC_CR1_AWDCH_MAX
ADC_CR1_AWDCH_SHIFT
ADC_CR1_AWDEN
ADC_CR1_AWDIE
ADC_CR1_AWDSGL
ADC_CR1_DISCEN
ADC_CR1_DISCNUM_1CHANNELS
ADC_CR1_DISCNUM_2CHANNELS
ADC_CR1_DISCNUM_3CHANNELS
ADC_CR1_DISCNUM_4CHANNELS
ADC_CR1_DISCNUM_5CHANNELS
ADC_CR1_DISCNUM_6CHANNELS
ADC_CR1_DISCNUM_7CHANNELS
ADC_CR1_DISCNUM_8CHANNELS
ADC_CR1_DISCNUM_MASK
ADC_CR1_DISCNUM_SHIFT
ADC_CR1_DUALMOD_ATM
ADC_CR1_DUALMOD_CISFIM
ADC_CR1_DUALMOD_CISSIM
ADC_CR1_DUALMOD_CRSATM
ADC_CR1_DUALMOD_CRSISM
ADC_CR1_DUALMOD_FIM
ADC_CR1_DUALMOD_IND
ADC_CR1_DUALMOD_ISM
ADC_CR1_DUALMOD_MASK
ADC_CR1_DUALMOD_RSM
ADC_CR1_DUALMOD_SHIFT
ADC_CR1_DUALMOD_SIM
ADC_CR1_EOCIE
ADC_CR1_JAUTO
ADC_CR1_JAWDEN
ADC_CR1_JDISCEN
ADC_CR1_JEOCIE
ADC_CR1_SCAN
ADC_CR2_ADON
ADC_CR2_ALIGN
ADC_CR2_ALIGN_LEFT
ADC_CR2_ALIGN_RIGHT
ADC_CR2_CAL
ADC_CR2_CONT
ADC_CR2_DMA
ADC_CR2_EXTSEL_EXTI11
ADC_CR2_EXTSEL_MASK
ADC_CR2_EXTSEL_SHIFT
ADC_CR2_EXTSEL_SWSTART
ADC_CR2_EXTSEL_TIM1_CC1
ADC_CR2_EXTSEL_TIM1_CC2
ADC_CR2_EXTSEL_TIM1_CC3
ADC_CR2_EXTSEL_TIM2_CC2
ADC_CR2_EXTSEL_TIM2_CC3
ADC_CR2_EXTSEL_TIM3_CC1
ADC_CR2_EXTSEL_TIM3_TRGO
ADC_CR2_EXTSEL_TIM4_CC4
ADC_CR2_EXTSEL_TIM5_CC1
ADC_CR2_EXTSEL_TIM5_CC3
ADC_CR2_EXTSEL_TIM8_CC1
ADC_CR2_EXTSEL_TIM8_TRGO
ADC_CR2_EXTTRIG
ADC_CR2_JEXTSEL_EXTI15
ADC_CR2_JEXTSEL_JSWSTART
ADC_CR2_JEXTSEL_MASK
ADC_CR2_JEXTSEL_SHIFT
ADC_CR2_JEXTSEL_TIM1_CC4
ADC_CR2_JEXTSEL_TIM1_TRGO
ADC_CR2_JEXTSEL_TIM2_CC1
ADC_CR2_JEXTSEL_TIM2_TRGO
ADC_CR2_JEXTSEL_TIM3_CC4
ADC_CR2_JEXTSEL_TIM4_CC3
ADC_CR2_JEXTSEL_TIM4_TRGO
ADC_CR2_JEXTSEL_TIM5_CC4
ADC_CR2_JEXTSEL_TIM5_TRGO
ADC_CR2_JEXTSEL_TIM8_CC2
ADC_CR2_JEXTSEL_TIM8_CC4
ADC_CR2_JEXTTRIG
ADC_CR2_JSWSTART
ADC_CR2_RSTCAL
ADC_CR2_SWSTART
ADC_CR2_TSVREFE
ADC_DATA_LSB
ADC_HT_LSB
ADC_HT_MSK
ADC_JDATA_LSB
ADC_JDATA_MSK
ADC_JOFFSET_LSB
ADC_JOFFSET_MSK
ADC_JSQR_JL_1CHANNELS
ADC_JSQR_JL_2CHANNELS
ADC_JSQR_JL_3CHANNELS
ADC_JSQR_JL_4CHANNELS
ADC_JSQR_JL_LSB
ADC_JSQR_JL_MSK
ADC_JSQR_JSQ1_LSB
ADC_JSQR_JSQ1_MSK
ADC_JSQR_JSQ2_LSB
ADC_JSQR_JSQ2_MSK
ADC_JSQR_JSQ3_LSB
ADC_JSQR_JSQ3_MSK
ADC_JSQR_JSQ4_LSB
ADC_JSQR_JSQ4_MSK
ADC_LT_LSB
ADC_LT_MSK
ADC_SMPR1_SMP10_LSB
ADC_SMPR1_SMP10_MSK
ADC_SMPR1_SMP11_LSB
ADC_SMPR1_SMP11_MSK
ADC_SMPR1_SMP12_LSB
ADC_SMPR1_SMP12_MSK
ADC_SMPR1_SMP13_LSB
ADC_SMPR1_SMP13_MSK
ADC_SMPR1_SMP14_LSB
ADC_SMPR1_SMP14_MSK
ADC_SMPR1_SMP15_LSB
ADC_SMPR1_SMP15_MSK
ADC_SMPR1_SMP16_LSB
ADC_SMPR1_SMP16_MSK
ADC_SMPR1_SMP17_LSB
ADC_SMPR1_SMP17_MSK
ADC_SMPR2_SMP0_LSB
ADC_SMPR2_SMP0_MSK
ADC_SMPR2_SMP1_LSB
ADC_SMPR2_SMP1_MSK
ADC_SMPR2_SMP2_LSB
ADC_SMPR2_SMP2_MSK
ADC_SMPR2_SMP3_LSB
ADC_SMPR2_SMP3_MSK
ADC_SMPR2_SMP4_LSB
ADC_SMPR2_SMP4_MSK
ADC_SMPR2_SMP5_LSB
ADC_SMPR2_SMP5_MSK
ADC_SMPR2_SMP6_LSB
ADC_SMPR2_SMP6_MSK
ADC_SMPR2_SMP7_LSB
ADC_SMPR2_SMP7_MSK
ADC_SMPR2_SMP8_LSB
ADC_SMPR2_SMP8_MSK
ADC_SMPR2_SMP9_LSB
ADC_SMPR2_SMP9_MSK
ADC_SMPR_SMP_13DOT5CYC
ADC_SMPR_SMP_1DOT5CYC
ADC_SMPR_SMP_239DOT5CYC
ADC_SMPR_SMP_28DOT5CYC
ADC_SMPR_SMP_41DOT5CYC
ADC_SMPR_SMP_55DOT5CYC
ADC_SMPR_SMP_71DOT5CYC
ADC_SMPR_SMP_7DOT5CYC
ADC_SQR1_L_LSB
ADC_SQR1_L_MSK
ADC_SQR1_SQ13_LSB
ADC_SQR1_SQ13_MSK
ADC_SQR1_SQ14_LSB
ADC_SQR1_SQ14_MSK
ADC_SQR1_SQ15_LSB
ADC_SQR1_SQ15_MSK
ADC_SQR1_SQ16_LSB
ADC_SQR1_SQ16_MSK
ADC_SQR2_SQ10_LSB
ADC_SQR2_SQ10_MSK
ADC_SQR2_SQ11_LSB
ADC_SQR2_SQ11_MSK
ADC_SQR2_SQ12_LSB
ADC_SQR2_SQ12_MSK
ADC_SQR2_SQ7_LSB
ADC_SQR2_SQ7_MSK
ADC_SQR2_SQ8_LSB
ADC_SQR2_SQ8_MSK
ADC_SQR2_SQ9_LSB
ADC_SQR2_SQ9_MSK
ADC_SQR3_SQ1_LSB
ADC_SQR3_SQ1_MSK
ADC_SQR3_SQ2_LSB
ADC_SQR3_SQ2_MSK
ADC_SQR3_SQ3_LSB
ADC_SQR3_SQ3_MSK
ADC_SQR3_SQ4_LSB
ADC_SQR3_SQ4_MSK
ADC_SQR3_SQ5_LSB
ADC_SQR3_SQ5_MSK
ADC_SQR3_SQ6_LSB
ADC_SQR3_SQ6_MSK
ADC_SQR_MAX_CHANNELS_REGULAR
ADC_SR_AWD
ADC_SR_EOC
ADC_SR_JEOC
ADC_SR_JSTRT
ADC_SR_STRT
AFIO_BASE
AFIO_EVCR_EVOE
AFIO_EVCR_PIN_Px0
AFIO_EVCR_PIN_Px1
AFIO_EVCR_PIN_Px2
AFIO_EVCR_PIN_Px3
AFIO_EVCR_PIN_Px4
AFIO_EVCR_PIN_Px5
AFIO_EVCR_PIN_Px6
AFIO_EVCR_PIN_Px7
AFIO_EVCR_PIN_Px8
AFIO_EVCR_PIN_Px9
AFIO_EVCR_PIN_Px10
AFIO_EVCR_PIN_Px11
AFIO_EVCR_PIN_Px12
AFIO_EVCR_PIN_Px13
AFIO_EVCR_PIN_Px14
AFIO_EVCR_PIN_Px15
AFIO_EVCR_PORT_PA
AFIO_EVCR_PORT_PB
AFIO_EVCR_PORT_PC
AFIO_EVCR_PORT_PD
AFIO_EVCR_PORT_PE
AFIO_EXTI0
AFIO_EXTI1
AFIO_EXTI2
AFIO_EXTI3
AFIO_EXTI4
AFIO_EXTI5
AFIO_EXTI6
AFIO_EXTI7
AFIO_EXTI8
AFIO_EXTI9
AFIO_EXTI10
AFIO_EXTI11
AFIO_EXTI12
AFIO_EXTI13
AFIO_EXTI14
AFIO_EXTI15
AFIO_MAPR1_TIM16_REMAP
AFIO_MAPR2_CEC_REMAP
AFIO_MAPR2_FSMC_NADV_DISCONNECT
AFIO_MAPR2_MISC_REMAP
AFIO_MAPR2_TIM10_REMAP
AFIO_MAPR2_TIM11_REMAP
AFIO_MAPR2_TIM12_REMAP
AFIO_MAPR2_TIM13_REMAP
AFIO_MAPR2_TIM14_REMAP
AFIO_MAPR2_TIM16_REMAP
AFIO_MAPR2_TIM17_REMAP
AFIO_MAPR2_TIM1_DMA_REMAP
AFIO_MAPR2_TIM76_DAC_DMA_REMAPE
AFIO_MAPR2_TIM9_REMAP
AFIO_MAPR_ADC1_ETRGINJ_REMAP
AFIO_MAPR_ADC1_ETRGREG_REMAP
AFIO_MAPR_ADC2_ETRGINJ_REMAP
AFIO_MAPR_ADC2_ETRGREG_REMAP
AFIO_MAPR_CAN1_REMAP_PORTA
AFIO_MAPR_CAN1_REMAP_PORTB
AFIO_MAPR_CAN1_REMAP_PORTD
AFIO_MAPR_CAN2_REMAP
AFIO_MAPR_ETH_REMAP
AFIO_MAPR_I2C1_REMAP
AFIO_MAPR_MII_RMII_SEL
AFIO_MAPR_PD01_REMAP
AFIO_MAPR_PTP_PPS_REMAP
AFIO_MAPR_SPI1_REMAP
AFIO_MAPR_SPI3_REMAP
AFIO_MAPR_SWJ_CFG_FULL_SWJ
AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST
AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF
AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON
AFIO_MAPR_SWJ_MASK
AFIO_MAPR_TIM1_REMAP_FULL_REMAP
AFIO_MAPR_TIM1_REMAP_NO_REMAP
AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP
AFIO_MAPR_TIM2ITR1_IREMAP
AFIO_MAPR_TIM2_REMAP_FULL_REMAP
AFIO_MAPR_TIM2_REMAP_NO_REMAP
AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1
AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2
AFIO_MAPR_TIM3_REMAP_FULL_REMAP
AFIO_MAPR_TIM3_REMAP_NO_REMAP
AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP
AFIO_MAPR_TIM4_REMAP
AFIO_MAPR_TIM5CH4_IREMAP
AFIO_MAPR_USART1_REMAP
AFIO_MAPR_USART2_REMAP
AFIO_MAPR_USART3_REMAP_FULL_REMAP
AFIO_MAPR_USART3_REMAP_NO_REMAP
AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP
BACKUP_REGS_BASE
BIT0
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
BIT13
BIT14
BIT15
BIT16
BIT17
BIT18
BIT19
BIT20
BIT21
BIT22
BIT23
BIT24
BIT25
BIT26
BIT27
BIT28
BIT29
BIT30
BIT31
BX_CAN1_BASE
BX_CAN2_BASE
CAN1
CAN2
CAN_BTR_BRP_MASK
CAN_BTR_LBKM
CAN_BTR_SILM
CAN_BTR_SJW_1TQ
CAN_BTR_SJW_2TQ
CAN_BTR_SJW_3TQ
CAN_BTR_SJW_4TQ
CAN_BTR_SJW_MASK
CAN_BTR_SJW_SHIFT
CAN_BTR_TS1_10TQ
CAN_BTR_TS1_11TQ
CAN_BTR_TS1_12TQ
CAN_BTR_TS1_13TQ
CAN_BTR_TS1_14TQ
CAN_BTR_TS1_15TQ
CAN_BTR_TS1_16TQ
CAN_BTR_TS1_1TQ
CAN_BTR_TS1_2TQ
CAN_BTR_TS1_3TQ
CAN_BTR_TS1_4TQ
CAN_BTR_TS1_5TQ
CAN_BTR_TS1_6TQ
CAN_BTR_TS1_7TQ
CAN_BTR_TS1_8TQ
CAN_BTR_TS1_9TQ
CAN_BTR_TS1_MASK
CAN_BTR_TS1_SHIFT
CAN_BTR_TS2_1TQ
CAN_BTR_TS2_2TQ
CAN_BTR_TS2_3TQ
CAN_BTR_TS2_4TQ
CAN_BTR_TS2_5TQ
CAN_BTR_TS2_6TQ
CAN_BTR_TS2_7TQ
CAN_BTR_TS2_8TQ
CAN_BTR_TS2_MASK
CAN_BTR_TS2_SHIFT
CAN_ESR_BOFF
CAN_ESR_EPVF
CAN_ESR_EWGF
CAN_ESR_LEC_ACK_ERROR
CAN_ESR_LEC_CRC_ERROR
CAN_ESR_LEC_DOM_ERROR
CAN_ESR_LEC_FORM_ERROR
CAN_ESR_LEC_MASK
CAN_ESR_LEC_NO_ERROR
CAN_ESR_LEC_REC_ERROR
CAN_ESR_LEC_SOFT_ERROR
CAN_ESR_LEC_STUFF_ERROR
CAN_ESR_REC_MASK
CAN_ESR_TEC_MASK
CAN_FIFO0
CAN_FIFO1
CAN_FMR_CAN2SB_MASK
CAN_FMR_CAN2SB_SHIFT
CAN_FMR_FINIT
CAN_IER_BOFIE
CAN_IER_EPVIE
CAN_IER_ERRIE
CAN_IER_EWGIE
CAN_IER_FFIE0
CAN_IER_FFIE1
CAN_IER_FMPIE0
CAN_IER_FMPIE1
CAN_IER_FOVIE0
CAN_IER_FOVIE1
CAN_IER_LECIE
CAN_IER_SLKIE
CAN_IER_TMEIE
CAN_IER_WKUIE
CAN_MBOX0
CAN_MBOX1
CAN_MBOX2
CAN_MCR_ABOM
CAN_MCR_AWUM
CAN_MCR_DBF
CAN_MCR_INRQ
CAN_MCR_NART
CAN_MCR_RESET
CAN_MCR_RFLM
CAN_MCR_SLEEP
CAN_MCR_TTCM
CAN_MCR_TXFP
CAN_MSR_ERRI
CAN_MSR_INAK
CAN_MSR_RX
CAN_MSR_RXM
CAN_MSR_SAMP
CAN_MSR_SLAK
CAN_MSR_SLAKI
CAN_MSR_TXM
CAN_MSR_WKUI
CAN_RDTxR_DLC_MASK
CAN_RDTxR_DLC_SHIFT
CAN_RDTxR_FMI_MASK
CAN_RDTxR_FMI_SHIFT
CAN_RDTxR_TIME_MASK
CAN_RDTxR_TIME_SHIFT
CAN_RF0R_FMP0_MASK
CAN_RF0R_FOVR0
CAN_RF0R_FULL0
CAN_RF0R_RFOM0
CAN_RF1R_FMP1_MASK
CAN_RF1R_FOVR1
CAN_RF1R_FULL1
CAN_RF1R_RFOM1
CAN_RIxR_EXID_MASK
CAN_RIxR_EXID_SHIFT
CAN_RIxR_IDE
CAN_RIxR_RTR
CAN_RIxR_STID_MASK
CAN_RIxR_STID_SHIFT
CAN_TDTxR_DLC_MASK
CAN_TDTxR_DLC_SHIFT
CAN_TDTxR_TGT
CAN_TDTxR_TIME_MASK
CAN_TDTxR_TIME_SHIFT
CAN_TIxR_EXID_MASK
CAN_TIxR_EXID_SHIFT
CAN_TIxR_IDE
CAN_TIxR_RTR
CAN_TIxR_STID_MASK
CAN_TIxR_STID_SHIFT
CAN_TIxR_TXRQ
CAN_TSR_ABRQ0
CAN_TSR_ABRQ1
CAN_TSR_ABRQ2
CAN_TSR_ALST0
CAN_TSR_ALST1
CAN_TSR_ALST2
CAN_TSR_CODE_MASK
CAN_TSR_LOW0
CAN_TSR_LOW1
CAN_TSR_LOW2
CAN_TSR_RQCP0
CAN_TSR_RQCP1
CAN_TSR_RQCP2
CAN_TSR_TERR0
CAN_TSR_TERR1
CAN_TSR_TERR2
CAN_TSR_TME0
CAN_TSR_TME1
CAN_TSR_TME2
CAN_TSR_TXOK0
CAN_TSR_TXOK1
CAN_TSR_TXOK2
CEC_BASE
CRC_BASE
CRC_CR_RESET
CS_ENDPOINT
CS_INTERFACE
DAC_BASE
DAC_CR_BOFF1
DAC_CR_BOFF2
DAC_CR_DMAEN1
DAC_CR_DMAEN2
DAC_CR_DMAUDRIE1
DAC_CR_DMAUDRIE2
DAC_CR_EN1
DAC_CR_EN2
DAC_CR_MAMP1_1
DAC_CR_MAMP1_2
DAC_CR_MAMP1_3
DAC_CR_MAMP1_4
DAC_CR_MAMP1_5
DAC_CR_MAMP1_6
DAC_CR_MAMP1_7
DAC_CR_MAMP1_8
DAC_CR_MAMP1_9
DAC_CR_MAMP1_10
DAC_CR_MAMP1_11
DAC_CR_MAMP1_12
DAC_CR_MAMP1_SHIFT
DAC_CR_MAMP2_1
DAC_CR_MAMP2_2
DAC_CR_MAMP2_3
DAC_CR_MAMP2_4
DAC_CR_MAMP2_5
DAC_CR_MAMP2_6
DAC_CR_MAMP2_7
DAC_CR_MAMP2_8
DAC_CR_MAMP2_9
DAC_CR_MAMP2_10
DAC_CR_MAMP2_11
DAC_CR_MAMP2_12
DAC_CR_MAMP2_SHIFT
DAC_CR_TEN1
DAC_CR_TEN2
DAC_CR_TSEL1_E9
DAC_CR_TSEL1_SHIFT
DAC_CR_TSEL1_SW
DAC_CR_TSEL1_T2
DAC_CR_TSEL1_T3
DAC_CR_TSEL1_T4
DAC_CR_TSEL1_T5
DAC_CR_TSEL1_T6
DAC_CR_TSEL1_T7
DAC_CR_TSEL1_T8
DAC_CR_TSEL1_T15
DAC_CR_TSEL2_E9
DAC_CR_TSEL2_SHIFT
DAC_CR_TSEL2_SW
DAC_CR_TSEL2_T2
DAC_CR_TSEL2_T3
DAC_CR_TSEL2_T4
DAC_CR_TSEL2_T5
DAC_CR_TSEL2_T6
DAC_CR_TSEL2_T7
DAC_CR_TSEL2_T8
DAC_CR_TSEL2_T15
DAC_CR_WAVE1_DIS
DAC_CR_WAVE1_NOISE
DAC_CR_WAVE1_SHIFT
DAC_CR_WAVE1_TRI
DAC_CR_WAVE2_DIS
DAC_CR_WAVE2_NOISE
DAC_CR_WAVE2_SHIFT
DAC_CR_WAVE2_TRI
DAC_DHR12L1_DACC1DHR_LSB
DAC_DHR12L1_DACC1DHR_MSK
DAC_DHR12L2_DACC2DHR_LSB
DAC_DHR12L2_DACC2DHR_MSK
DAC_DHR12LD_DACC1DHR_LSB
DAC_DHR12LD_DACC1DHR_MSK
DAC_DHR12LD_DACC2DHR_LSB
DAC_DHR12LD_DACC2DHR_MSK
DAC_DHR12R1_DACC1DHR_LSB
DAC_DHR12R1_DACC1DHR_MSK
DAC_DHR12R2_DACC2DHR_LSB
DAC_DHR12R2_DACC2DHR_MSK
DAC_DHR12RD_DACC1DHR_LSB
DAC_DHR12RD_DACC1DHR_MSK
DAC_DHR12RD_DACC2DHR_LSB
DAC_DHR12RD_DACC2DHR_MSK
DAC_DHR8R1_DACC1DHR_LSB
DAC_DHR8R1_DACC1DHR_MSK
DAC_DHR8R2_DACC2DHR_LSB
DAC_DHR8R2_DACC2DHR_MSK
DAC_DHR8RD_DACC1DHR_LSB
DAC_DHR8RD_DACC1DHR_MSK
DAC_DHR8RD_DACC2DHR_LSB
DAC_DHR8RD_DACC2DHR_MSK
DAC_DOR1_DACC1DOR_LSB
DAC_DOR1_DACC1DOR_MSK
DAC_DOR2_DACC2DOR_LSB
DAC_DOR2_DACC2DOR_MSK
DAC_SWTRIGR_SWTRIG1
DAC_SWTRIGR_SWTRIG2
DBGMCU_BASE
DESIG_FLASH_SIZE_BASE
DESIG_UNIQUE_ID_BASE
DFU_FUNCTIONAL
DMA1
DMA2
DMA1_BASE
DMA2_BASE
DMA_CCR_CIRC
DMA_CCR_DIR
DMA_CCR_EN
DMA_CCR_HTIE
DMA_CCR_MEM2MEM
DMA_CCR_MINC
DMA_CCR_MSIZE_16BIT
DMA_CCR_MSIZE_32BIT
DMA_CCR_MSIZE_8BIT
DMA_CCR_MSIZE_MASK
DMA_CCR_MSIZE_SHIFT
DMA_CCR_PINC
DMA_CCR_PL_HIGH
DMA_CCR_PL_LOW
DMA_CCR_PL_MASK
DMA_CCR_PL_MEDIUM
DMA_CCR_PL_SHIFT
DMA_CCR_PL_VERY_HIGH
DMA_CCR_PSIZE_16BIT
DMA_CCR_PSIZE_32BIT
DMA_CCR_PSIZE_8BIT
DMA_CCR_PSIZE_MASK
DMA_CCR_PSIZE_SHIFT
DMA_CCR_TCIE
DMA_CCR_TEIE
DMA_CHANNEL1
DMA_CHANNEL2
DMA_CHANNEL3
DMA_CHANNEL4
DMA_CHANNEL5
DMA_CHANNEL6
DMA_CHANNEL7
DMA_FLAGS
DMA_GIF
DMA_HTIF
DMA_IFCR_CGIF_BIT
DMA_IFCR_CHTIF_BIT
DMA_IFCR_CIF_BIT
DMA_IFCR_CTCIF_BIT
DMA_IFCR_CTEIF_BIT
DMA_ISR_GIF_BIT
DMA_ISR_HTIF_BIT
DMA_ISR_TCIF_BIT
DMA_ISR_TEIF_BIT
DMA_TCIF
DMA_TEIF
DWT_CTRL_NUMCOMP
DWT_CTRL_NUMCOMP_SHIFT
DWT_FUNCTIONx_FUNCTION
DWT_FUNCTIONx_FUNCTION_DISABLED
DWT_FUNCTIONx_MATCHED
DWT_MASKx_MASK
ETHERNET_BASE
EXTI0
EXTI1
EXTI2
EXTI3
EXTI4
EXTI5
EXTI6
EXTI7
EXTI8
EXTI9
EXTI10
EXTI11
EXTI12
EXTI13
EXTI14
EXTI15
EXTI16
EXTI17
EXTI18
EXTI19
EXTI20
EXTI21
EXTI22
EXTI23
EXTI24
EXTI25
EXTI26
EXTI27
EXTI28
EXTI29
EXTI30
EXTI31
EXTI32
EXTI33
EXTI34
EXTI35
EXTI36
EXTI37
EXTI_BASE
FLASH_ACR_HLFCYA
FLASH_ACR_LATENCY
FLASH_ACR_LATENCY_0WS
FLASH_ACR_LATENCY_1WS
FLASH_ACR_LATENCY_2WS
FLASH_ACR_LATENCY_SHIFT
FLASH_ACR_PRFTBE
FLASH_ACR_PRFTBS
FLASH_BASE
FLASH_CR_EOPIE
FLASH_CR_ERRIE
FLASH_CR_LOCK
FLASH_CR_MER
FLASH_CR_OPTER
FLASH_CR_OPTPG
FLASH_CR_OPTWRE
FLASH_CR_PER
FLASH_CR_PG
FLASH_CR_STRT
FLASH_MEM_INTERFACE_BASE
FLASH_OBR_NRST_STDBY
FLASH_OBR_NRST_STOP
FLASH_OBR_OPTERR
FLASH_OBR_RDPRT_EN
FLASH_OBR_RDPRT_SHIFT
FLASH_OBR_WDG_SW
FLASH_SR_BSY
FLASH_SR_EOP
FLASH_SR_PGERR
FLASH_SR_WRPRTERR
FSMC_BANK1_BASE
FSMC_BANK2_BASE
FSMC_BANK3_BASE
FSMC_BANK4_BASE
FSMC_BASE
FSMC_BCR_ASYNCWAIT
FSMC_BCR_BURSTEN
FSMC_BCR_CBURSTRW
FSMC_BCR_EXTMOD
FSMC_BCR_FACCEN
FSMC_BCR_MBKEN
FSMC_BCR_MTYP
FSMC_BCR_MUXEN
FSMC_BCR_MWID
FSMC_BCR_WAITCFG
FSMC_BCR_WAITEN
FSMC_BCR_WAITPOL
FSMC_BCR_WRAPMOD
FSMC_BCR_WREN
FSMC_BTR_ACCMOD
FSMC_BTR_ADDHLD
FSMC_BTR_ADDSET
FSMC_BTR_BUSTURN
FSMC_BTR_CLKDIV
FSMC_BTR_DATAST
FSMC_BTR_DATLAT
FSMC_BTx_ACCMOD_A
FSMC_BTx_ACCMOD_B
FSMC_BTx_ACCMOD_C
FSMC_BTx_ACCMOD_D
FSMC_BWTR_ACCMOD
FSMC_BWTR_ADDHLD
FSMC_BWTR_ADDSET
FSMC_BWTR_CLKDIV
FSMC_BWTR_DATAST
FSMC_BWTR_DATLAT
FSMC_ECCR_ECCX
FSMC_PATT_ATTHIZX
FSMC_PATT_ATTHOLDX
FSMC_PATT_ATTSETX
FSMC_PATT_ATTWAITX
FSMC_PCR_ECCEN
FSMC_PCR_ECCPS
FSMC_PCR_PBKEN
FSMC_PCR_PTYP
FSMC_PCR_PWAITEN
FSMC_PCR_PWID
FSMC_PCR_TAR
FSMC_PCR_TCLR
FSMC_PIO4_IOHIZX
FSMC_PIO4_IOHOLDX
FSMC_PIO4_IOSETX
FSMC_PIO4_IOWAITX
FSMC_PMEM_MEMHIZX
FSMC_PMEM_MEMHOLDX
FSMC_PMEM_MEMSETX
FSMC_PMEM_MEMWAITX
FSMC_SR_FEMPT
FSMC_SR_IFEN
FSMC_SR_IFS
FSMC_SR_ILEN
FSMC_SR_ILS
FSMC_SR_IREN
FSMC_SR_IRS
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIOA
GPIOB
GPIOC
GPIOD
GPIOE
GPIOF
GPIOG
GPIO_ALL
GPIO_BANK_CAN1_PB_RX
GPIO_BANK_CAN1_PB_TX
GPIO_BANK_CAN1_PD_RX
GPIO_BANK_CAN1_PD_TX
GPIO_BANK_CAN1_RX
GPIO_BANK_CAN1_TX
GPIO_BANK_CAN2_RE_RX
GPIO_BANK_CAN2_RE_TX
GPIO_BANK_CAN2_RX
GPIO_BANK_CAN2_TX
GPIO_BANK_CAN_PB_RX
GPIO_BANK_CAN_PB_TX
GPIO_BANK_CAN_PD_RX
GPIO_BANK_CAN_PD_TX
GPIO_BANK_CAN_RX
GPIO_BANK_CAN_TX
GPIO_BANK_ETH_RE_RXD0
GPIO_BANK_ETH_RE_RXD1
GPIO_BANK_ETH_RE_RXD2
GPIO_BANK_ETH_RE_RXD3
GPIO_BANK_ETH_RE_RX_DV_CRS_DV
GPIO_BANK_ETH_RXD0
GPIO_BANK_ETH_RXD1
GPIO_BANK_ETH_RXD2
GPIO_BANK_ETH_RXD3
GPIO_BANK_ETH_RX_DV_CRS_DV
GPIO_BANK_I2C1_RE_SCL
GPIO_BANK_I2C1_RE_SDA
GPIO_BANK_I2C1_RE_SMBAI
GPIO_BANK_I2C1_SCL
GPIO_BANK_I2C1_SDA
GPIO_BANK_I2C1_SMBAI
GPIO_BANK_I2C2_SCL
GPIO_BANK_I2C2_SDA
GPIO_BANK_I2C2_SMBAI
GPIO_BANK_JNTRST
GPIO_BANK_JTCK_SWCLK
GPIO_BANK_JTDI
GPIO_BANK_JTDO_TRACESWO
GPIO_BANK_JTMS_SWDIO
GPIO_BANK_SPI1_MISO
GPIO_BANK_SPI1_MOSI
GPIO_BANK_SPI1_NSS
GPIO_BANK_SPI1_RE_MISO
GPIO_BANK_SPI1_RE_MOSI
GPIO_BANK_SPI1_RE_NSS
GPIO_BANK_SPI1_RE_SCK
GPIO_BANK_SPI1_SCK
GPIO_BANK_SPI2_MISO
GPIO_BANK_SPI2_MOSI
GPIO_BANK_SPI2_NSS
GPIO_BANK_SPI2_SCK
GPIO_BANK_SPI3_MISO
GPIO_BANK_SPI3_MOSI
GPIO_BANK_SPI3_NSS
GPIO_BANK_SPI3_RE_MISO
GPIO_BANK_SPI3_RE_MOSI
GPIO_BANK_SPI3_RE_NSS
GPIO_BANK_SPI3_RE_SCK
GPIO_BANK_SPI3_SCK
GPIO_BANK_TIM2
GPIO_BANK_TIM4
GPIO_BANK_TIM5
GPIO_BANK_TIM1_BKIN
GPIO_BANK_TIM1_BKIN_CH123N
GPIO_BANK_TIM1_CH1
GPIO_BANK_TIM1_CH2
GPIO_BANK_TIM1_CH3
GPIO_BANK_TIM1_CH4
GPIO_BANK_TIM1_CH1N
GPIO_BANK_TIM1_CH2N
GPIO_BANK_TIM1_CH3N
GPIO_BANK_TIM1_ETR
GPIO_BANK_TIM1_ETR_CH1234
GPIO_BANK_TIM1_FR
GPIO_BANK_TIM1_FR_BKIN
GPIO_BANK_TIM1_FR_CH1
GPIO_BANK_TIM1_FR_CH2
GPIO_BANK_TIM1_FR_CH3
GPIO_BANK_TIM1_FR_CH4
GPIO_BANK_TIM1_FR_CH1N
GPIO_BANK_TIM1_FR_CH2N
GPIO_BANK_TIM1_FR_CH3N
GPIO_BANK_TIM1_FR_ETR
GPIO_BANK_TIM1_PR_BKIN
GPIO_BANK_TIM1_PR_CH1
GPIO_BANK_TIM1_PR_CH2
GPIO_BANK_TIM1_PR_CH3
GPIO_BANK_TIM1_PR_CH4
GPIO_BANK_TIM1_PR_CH1N
GPIO_BANK_TIM1_PR_CH23N
GPIO_BANK_TIM1_PR_CH2N
GPIO_BANK_TIM1_PR_CH3N
GPIO_BANK_TIM1_PR_ETR
GPIO_BANK_TIM1_PR_ETR_CH1234_BKIN_CH1N
GPIO_BANK_TIM2_CH2
GPIO_BANK_TIM2_CH3
GPIO_BANK_TIM2_CH4
GPIO_BANK_TIM2_CH1_ETR
GPIO_BANK_TIM2_FR_CH2
GPIO_BANK_TIM2_FR_CH3
GPIO_BANK_TIM2_FR_CH4
GPIO_BANK_TIM2_FR_CH234
GPIO_BANK_TIM2_FR_CH1_ETR
GPIO_BANK_TIM2_PR1_CH2
GPIO_BANK_TIM2_PR1_CH3
GPIO_BANK_TIM2_PR1_CH4
GPIO_BANK_TIM2_PR1_CH134
GPIO_BANK_TIM2_PR1_CH1_ETR
GPIO_BANK_TIM2_PR2_CH2
GPIO_BANK_TIM2_PR2_CH3
GPIO_BANK_TIM2_PR2_CH4
GPIO_BANK_TIM2_PR2_CH12
GPIO_BANK_TIM2_PR2_CH34
GPIO_BANK_TIM2_PR2_CH1_ETR
GPIO_BANK_TIM3_CH1
GPIO_BANK_TIM3_CH2
GPIO_BANK_TIM3_CH3
GPIO_BANK_TIM3_CH4
GPIO_BANK_TIM3_CH12
GPIO_BANK_TIM3_CH34
GPIO_BANK_TIM3_FR
GPIO_BANK_TIM3_FR_CH1
GPIO_BANK_TIM3_FR_CH2
GPIO_BANK_TIM3_FR_CH3
GPIO_BANK_TIM3_FR_CH4
GPIO_BANK_TIM3_PR
GPIO_BANK_TIM3_PR_CH1
GPIO_BANK_TIM3_PR_CH2
GPIO_BANK_TIM3_PR_CH3
GPIO_BANK_TIM3_PR_CH4
GPIO_BANK_TIM4_CH1
GPIO_BANK_TIM4_CH2
GPIO_BANK_TIM4_CH3
GPIO_BANK_TIM4_CH4
GPIO_BANK_TIM4_RE
GPIO_BANK_TIM4_RE_CH1
GPIO_BANK_TIM4_RE_CH2
GPIO_BANK_TIM4_RE_CH3
GPIO_BANK_TIM4_RE_CH4
GPIO_BANK_TIM5_CH1
GPIO_BANK_TIM5_CH2
GPIO_BANK_TIM5_CH3
GPIO_BANK_TIM5_CH4
GPIO_BANK_TRACECK
GPIO_BANK_TRACED0
GPIO_BANK_TRACED1
GPIO_BANK_TRACED2
GPIO_BANK_TRACED3
GPIO_BANK_UART4_RX
GPIO_BANK_UART4_TX
GPIO_BANK_UART5_RX
GPIO_BANK_UART5_TX
GPIO_BANK_USART1_RE_RX
GPIO_BANK_USART1_RE_TX
GPIO_BANK_USART1_RX
GPIO_BANK_USART1_TX
GPIO_BANK_USART2_CK
GPIO_BANK_USART2_CTS
GPIO_BANK_USART2_RE_CK
GPIO_BANK_USART2_RE_CTS
GPIO_BANK_USART2_RE_RTS
GPIO_BANK_USART2_RE_RX
GPIO_BANK_USART2_RE_TX
GPIO_BANK_USART2_RTS
GPIO_BANK_USART2_RX
GPIO_BANK_USART2_TX
GPIO_BANK_USART3_CK
GPIO_BANK_USART3_CTS
GPIO_BANK_USART3_FR_CK
GPIO_BANK_USART3_FR_CTS
GPIO_BANK_USART3_FR_RTS
GPIO_BANK_USART3_FR_RX
GPIO_BANK_USART3_FR_TX
GPIO_BANK_USART3_PR_CK
GPIO_BANK_USART3_PR_CTS
GPIO_BANK_USART3_PR_RTS
GPIO_BANK_USART3_PR_RX
GPIO_BANK_USART3_PR_TX
GPIO_BANK_USART3_RTS
GPIO_BANK_USART3_RX
GPIO_BANK_USART3_TX
GPIO_CAN1_PB_RX
GPIO_CAN1_PB_TX
GPIO_CAN1_PD_RX
GPIO_CAN1_PD_TX
GPIO_CAN1_RX
GPIO_CAN1_TX
GPIO_CAN2_RE_RX
GPIO_CAN2_RE_TX
GPIO_CAN2_RX
GPIO_CAN2_TX
GPIO_CAN_PB_RX
GPIO_CAN_PB_TX
GPIO_CAN_PD_RX
GPIO_CAN_PD_TX
GPIO_CAN_RX
GPIO_CAN_TX
GPIO_CNF_INPUT_ANALOG
GPIO_CNF_INPUT_FLOAT
GPIO_CNF_INPUT_PULL_UPDOWN
GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL
GPIO_CNF_OUTPUT_OPENDRAIN
GPIO_CNF_OUTPUT_PUSHPULL
GPIO_ETH_RE_RXD0
GPIO_ETH_RE_RXD1
GPIO_ETH_RE_RXD2
GPIO_ETH_RE_RXD3
GPIO_ETH_RE_RX_DV_CRS_DV
GPIO_ETH_RXD0
GPIO_ETH_RXD1
GPIO_ETH_RXD2
GPIO_ETH_RXD3
GPIO_ETH_RX_DV_CRS_DV
GPIO_I2C1_RE_SCL
GPIO_I2C1_RE_SDA
GPIO_I2C1_RE_SMBAI
GPIO_I2C1_SCL
GPIO_I2C1_SDA
GPIO_I2C1_SMBAI
GPIO_I2C2_SCL
GPIO_I2C2_SDA
GPIO_I2C2_SMBAI
GPIO_JNTRST
GPIO_JTCK_SWCLK
GPIO_JTDI
GPIO_JTDO_TRACESWO
GPIO_JTMS_SWDIO
GPIO_LCKK
GPIO_MODE_INPUT
GPIO_MODE_OUTPUT_10_MHZ
GPIO_MODE_OUTPUT_2_MHZ
GPIO_MODE_OUTPUT_50_MHZ
GPIO_PORT_A_BASE
GPIO_PORT_B_BASE
GPIO_PORT_C_BASE
GPIO_PORT_D_BASE
GPIO_PORT_E_BASE
GPIO_PORT_F_BASE
GPIO_PORT_G_BASE
GPIO_SPI1_MISO
GPIO_SPI1_MOSI
GPIO_SPI1_NSS
GPIO_SPI1_RE_MISO
GPIO_SPI1_RE_MOSI
GPIO_SPI1_RE_NSS
GPIO_SPI1_RE_SCK
GPIO_SPI1_SCK
GPIO_SPI2_MISO
GPIO_SPI2_MOSI
GPIO_SPI2_NSS
GPIO_SPI2_SCK
GPIO_SPI3_MISO
GPIO_SPI3_MOSI
GPIO_SPI3_NSS
GPIO_SPI3_RE_MISO
GPIO_SPI3_RE_MOSI
GPIO_SPI3_RE_NSS
GPIO_SPI3_RE_SCK
GPIO_SPI3_SCK
GPIO_TIM1_BKIN
GPIO_TIM1_CH1
GPIO_TIM1_CH2
GPIO_TIM1_CH3
GPIO_TIM1_CH4
GPIO_TIM1_CH1N
GPIO_TIM1_CH2N
GPIO_TIM1_CH3N
GPIO_TIM1_ETR
GPIO_TIM1_FR_BKIN
GPIO_TIM1_FR_CH1
GPIO_TIM1_FR_CH2
GPIO_TIM1_FR_CH3
GPIO_TIM1_FR_CH4
GPIO_TIM1_FR_CH1N
GPIO_TIM1_FR_CH2N
GPIO_TIM1_FR_CH3N
GPIO_TIM1_FR_ETR
GPIO_TIM1_PR_BKIN
GPIO_TIM1_PR_CH1
GPIO_TIM1_PR_CH2
GPIO_TIM1_PR_CH3
GPIO_TIM1_PR_CH4
GPIO_TIM1_PR_CH1N
GPIO_TIM1_PR_CH2N
GPIO_TIM1_PR_CH3N
GPIO_TIM1_PR_ETR
GPIO_TIM2_CH2
GPIO_TIM2_CH3
GPIO_TIM2_CH4
GPIO_TIM2_CH1_ETR
GPIO_TIM2_FR_CH2
GPIO_TIM2_FR_CH3
GPIO_TIM2_FR_CH4
GPIO_TIM2_FR_CH1_ETR
GPIO_TIM2_PR1_CH2
GPIO_TIM2_PR1_CH3
GPIO_TIM2_PR1_CH4
GPIO_TIM2_PR1_CH1_ETR
GPIO_TIM2_PR2_CH2
GPIO_TIM2_PR2_CH3
GPIO_TIM2_PR2_CH4
GPIO_TIM2_PR2_CH1_ETR
GPIO_TIM3_CH1
GPIO_TIM3_CH2
GPIO_TIM3_CH3
GPIO_TIM3_CH4
GPIO_TIM3_FR_CH1
GPIO_TIM3_FR_CH2
GPIO_TIM3_FR_CH3
GPIO_TIM3_FR_CH4
GPIO_TIM3_PR_CH1
GPIO_TIM3_PR_CH2
GPIO_TIM3_PR_CH3
GPIO_TIM3_PR_CH4
GPIO_TIM4_CH1
GPIO_TIM4_CH2
GPIO_TIM4_CH3
GPIO_TIM4_CH4
GPIO_TIM4_RE_CH1
GPIO_TIM4_RE_CH2
GPIO_TIM4_RE_CH3
GPIO_TIM4_RE_CH4
GPIO_TIM5_CH1
GPIO_TIM5_CH2
GPIO_TIM5_CH3
GPIO_TIM5_CH4
GPIO_TRACECK
GPIO_TRACED0
GPIO_TRACED1
GPIO_TRACED2
GPIO_TRACED3
GPIO_UART4_RX
GPIO_UART4_TX
GPIO_UART5_RX
GPIO_UART5_TX
GPIO_USART1_RE_RX
GPIO_USART1_RE_TX
GPIO_USART1_RX
GPIO_USART1_TX
GPIO_USART2_CK
GPIO_USART2_CTS
GPIO_USART2_RE_CK
GPIO_USART2_RE_CTS
GPIO_USART2_RE_RTS
GPIO_USART2_RE_RX
GPIO_USART2_RE_TX
GPIO_USART2_RTS
GPIO_USART2_RX
GPIO_USART2_TX
GPIO_USART3_CK
GPIO_USART3_CTS
GPIO_USART3_FR_CK
GPIO_USART3_FR_CTS
GPIO_USART3_FR_RTS
GPIO_USART3_FR_RX
GPIO_USART3_FR_TX
GPIO_USART3_PR_CK
GPIO_USART3_PR_CTS
GPIO_USART3_PR_RTS
GPIO_USART3_PR_RX
GPIO_USART3_PR_TX
GPIO_USART3_RTS
GPIO_USART3_RX
GPIO_USART3_TX
I2C1
I2C2
I2C1_BASE
I2C2_BASE
I2C_CCR_DUTY
I2C_CCR_DUTY_16_DIV_9
I2C_CCR_DUTY_DIV2
I2C_CCR_FS
I2C_CR1_ACK
I2C_CR1_ALERT
I2C_CR1_ENARP
I2C_CR1_ENGC
I2C_CR1_ENPEC
I2C_CR1_NOSTRETCH
I2C_CR1_PE
I2C_CR1_PEC
I2C_CR1_POS
I2C_CR1_SMBTYPE
I2C_CR1_SMBUS
I2C_CR1_START
I2C_CR1_STOP
I2C_CR1_SWRST
I2C_CR2_DMAEN
I2C_CR2_FREQ_10MHZ
I2C_CR2_FREQ_11MHZ
I2C_CR2_FREQ_12MHZ
I2C_CR2_FREQ_13MHZ
I2C_CR2_FREQ_14MHZ
I2C_CR2_FREQ_15MHZ
I2C_CR2_FREQ_16MHZ
I2C_CR2_FREQ_17MHZ
I2C_CR2_FREQ_18MHZ
I2C_CR2_FREQ_19MHZ
I2C_CR2_FREQ_20MHZ
I2C_CR2_FREQ_21MHZ
I2C_CR2_FREQ_22MHZ
I2C_CR2_FREQ_23MHZ
I2C_CR2_FREQ_24MHZ
I2C_CR2_FREQ_25MHZ
I2C_CR2_FREQ_26MHZ
I2C_CR2_FREQ_27MHZ
I2C_CR2_FREQ_28MHZ
I2C_CR2_FREQ_29MHZ
I2C_CR2_FREQ_2MHZ
I2C_CR2_FREQ_30MHZ
I2C_CR2_FREQ_31MHZ
I2C_CR2_FREQ_32MHZ
I2C_CR2_FREQ_33MHZ
I2C_CR2_FREQ_34MHZ
I2C_CR2_FREQ_35MHZ
I2C_CR2_FREQ_36MHZ
I2C_CR2_FREQ_37MHZ
I2C_CR2_FREQ_38MHZ
I2C_CR2_FREQ_39MHZ
I2C_CR2_FREQ_3MHZ
I2C_CR2_FREQ_40MHZ
I2C_CR2_FREQ_41MHZ
I2C_CR2_FREQ_42MHZ
I2C_CR2_FREQ_4MHZ
I2C_CR2_FREQ_5MHZ
I2C_CR2_FREQ_6MHZ
I2C_CR2_FREQ_7MHZ
I2C_CR2_FREQ_8MHZ
I2C_CR2_FREQ_9MHZ
I2C_CR2_ITBUFEN
I2C_CR2_ITERREN
I2C_CR2_ITEVTEN
I2C_CR2_LAST
I2C_OAR1_ADDMODE
I2C_OAR1_ADDMODE_10BIT
I2C_OAR1_ADDMODE_7BIT
I2C_OAR2_ENDUAL
I2C_READ
I2C_SR1_ADD10
I2C_SR1_ADDR
I2C_SR1_AF
I2C_SR1_ARLO
I2C_SR1_BERR
I2C_SR1_BTF
I2C_SR1_OVR
I2C_SR1_PECERR
I2C_SR1_RxNE
I2C_SR1_SB
I2C_SR1_SMBALERT
I2C_SR1_STOPF
I2C_SR1_TIMEOUT
I2C_SR1_TxE
I2C_SR2_BUSY
I2C_SR2_DUALF
I2C_SR2_GENCALL
I2C_SR2_MSL
I2C_SR2_SMBDEFAULT
I2C_SR2_SMBHOST
I2C_SR2_TRA
I2C_WRITE
INFO_BASE
INT16_MAX
INT16_MIN
INT32_MAX
INT32_MIN
INT8_MAX
INT8_MIN
INTPTR_MAX
INTPTR_MIN
INT_FAST16_MAX
INT_FAST16_MIN
INT_FAST32_MAX
INT_FAST32_MIN
INT_FAST8_MAX
INT_FAST8_MIN
INT_LEAST16_MAX
INT_LEAST16_MIN
INT_LEAST32_MAX
INT_LEAST32_MIN
INT_LEAST8_MAX
INT_LEAST8_MIN
IWDG_BASE
IWDG_KR_RESET
IWDG_KR_START
IWDG_KR_UNLOCK
IWDG_PR_DIV4
IWDG_PR_DIV8
IWDG_PR_DIV16
IWDG_PR_DIV32
IWDG_PR_DIV64
IWDG_PR_DIV128
IWDG_PR_DIV256
IWDG_PR_LSB
IWDG_SR_PVU
IWDG_SR_RVU
MPU_BASE
MPU_CTRL_ENABLE
MPU_CTRL_HFNMIENA
MPU_CTRL_PRIVDEFENA
MPU_RASR_ATTRS
MPU_RASR_ATTRS_LSB
MPU_RASR_ATTR_AP
MPU_RASR_ATTR_AP_PNO_UNO
MPU_RASR_ATTR_AP_PRO_UNO
MPU_RASR_ATTR_AP_PRO_URO
MPU_RASR_ATTR_AP_PRW_UNO
MPU_RASR_ATTR_AP_PRW_URO
MPU_RASR_ATTR_AP_PRW_URW
MPU_RASR_ATTR_B
MPU_RASR_ATTR_C
MPU_RASR_ATTR_S
MPU_RASR_ATTR_SCB
MPU_RASR_ATTR_TEX
MPU_RASR_ATTR_XN
MPU_RASR_ENABLE
MPU_RASR_SIZE
MPU_RASR_SIZE_LSB
MPU_RASR_SRD
MPU_RASR_SRD_LSB
MPU_RBAR_ADDR
MPU_RBAR_REGION
MPU_RBAR_REGION_LSB
MPU_RBAR_VALID
MPU_RNR_REGION
MPU_RNR_REGION_LSB
MPU_TYPE_DREGION
MPU_TYPE_DREGION_LSB
MPU_TYPE_IREGION
MPU_TYPE_IREGION_LSB
MPU_TYPE_SEPARATE
NVIC_ADC1_2_IRQ
NVIC_ADC3_IRQ
NVIC_BASE
NVIC_CAN2_RX0_IRQ
NVIC_CAN2_RX1_IRQ
NVIC_CAN2_SCE_IRQ
NVIC_CAN2_TX_IRQ
NVIC_CAN_RX1_IRQ
NVIC_CAN_SCE_IRQ
NVIC_DMA1_CHANNEL1_IRQ
NVIC_DMA1_CHANNEL2_IRQ
NVIC_DMA1_CHANNEL3_IRQ
NVIC_DMA1_CHANNEL4_IRQ
NVIC_DMA1_CHANNEL5_IRQ
NVIC_DMA1_CHANNEL6_IRQ
NVIC_DMA1_CHANNEL7_IRQ
NVIC_DMA2_CHANNEL1_IRQ
NVIC_DMA2_CHANNEL2_IRQ
NVIC_DMA2_CHANNEL3_IRQ
NVIC_DMA2_CHANNEL4_5_IRQ
NVIC_DMA2_CHANNEL5_IRQ
NVIC_ETH_IRQ
NVIC_ETH_WKUP_IRQ
NVIC_EXTI0_IRQ
NVIC_EXTI15_10_IRQ
NVIC_EXTI1_IRQ
NVIC_EXTI2_IRQ
NVIC_EXTI3_IRQ
NVIC_EXTI4_IRQ
NVIC_EXTI9_5_IRQ
NVIC_FLASH_IRQ
NVIC_FSMC_IRQ
NVIC_HARD_FAULT_IRQ
NVIC_I2C1_ER_IRQ
NVIC_I2C1_EV_IRQ
NVIC_I2C2_ER_IRQ
NVIC_I2C2_EV_IRQ
NVIC_IRQ_COUNT
NVIC_NMI_IRQ
NVIC_OTG_FS_IRQ
NVIC_PENDSV_IRQ
NVIC_PVD_IRQ
NVIC_RCC_IRQ
NVIC_RTC_ALARM_IRQ
NVIC_RTC_IRQ
NVIC_SDIO_IRQ
NVIC_SPI1_IRQ
NVIC_SPI2_IRQ
NVIC_SPI3_IRQ
NVIC_SV_CALL_IRQ
NVIC_SYSTICK_IRQ
NVIC_TAMPER_IRQ
NVIC_TIM1_BRK_IRQ
NVIC_TIM1_CC_IRQ
NVIC_TIM1_TRG_COM_IRQ
NVIC_TIM1_UP_IRQ
NVIC_TIM2_IRQ
NVIC_TIM3_IRQ
NVIC_TIM4_IRQ
NVIC_TIM5_IRQ
NVIC_TIM6_IRQ
NVIC_TIM7_IRQ
NVIC_TIM8_BRK_IRQ
NVIC_TIM8_CC_IRQ
NVIC_TIM8_TRG_COM_IRQ
NVIC_TIM8_UP_IRQ
NVIC_UART4_IRQ
NVIC_UART5_IRQ
NVIC_USART1_IRQ
NVIC_USART2_IRQ
NVIC_USART3_IRQ
NVIC_USB_HP_CAN_TX_IRQ
NVIC_USB_LP_CAN_RX0_IRQ
NVIC_USB_WAKEUP_IRQ
NVIC_WWDG_IRQ
PERIPH_BASE
PERIPH_BASE_AHB
PERIPH_BASE_APB1
PERIPH_BASE_APB2
POWER_CONTROL_BASE
PPBI_BASE
PTRDIFF_MAX
PTRDIFF_MIN
PWR_CR_CSBF
PWR_CR_CWUF
PWR_CR_DBP
PWR_CR_LPDS
PWR_CR_PDDS
PWR_CR_PLS_2V2
PWR_CR_PLS_2V3
PWR_CR_PLS_2V4
PWR_CR_PLS_2V5
PWR_CR_PLS_2V6
PWR_CR_PLS_2V7
PWR_CR_PLS_2V8
PWR_CR_PLS_2V9
PWR_CR_PLS_LSB
PWR_CR_PLS_MASK
PWR_CR_PVDE
PWR_CSR_EWUP
PWR_CSR_PVDO
PWR_CSR_SBF
PWR_CSR_WUF
RCC_AHBENR_CRCEN
RCC_AHBENR_DMA1EN
RCC_AHBENR_DMA2EN
RCC_AHBENR_ETHMACEN
RCC_AHBENR_ETHMACENRX
RCC_AHBENR_ETHMACENTX
RCC_AHBENR_FLITFEN
RCC_AHBENR_FSMCEN
RCC_AHBENR_OTGFSEN
RCC_AHBENR_SDIOEN
RCC_AHBENR_SRAMEN
RCC_AHBRSTR_ETHMACRST
RCC_AHBRSTR_OTGFSRST
RCC_APB1ENR_BKPEN
RCC_APB1ENR_CAN1EN
RCC_APB1ENR_CAN2EN
RCC_APB1ENR_CANEN
RCC_APB1ENR_DACEN
RCC_APB1ENR_I2C1EN
RCC_APB1ENR_I2C2EN
RCC_APB1ENR_PWREN
RCC_APB1ENR_SPI2EN
RCC_APB1ENR_SPI3EN
RCC_APB1ENR_TIM2EN
RCC_APB1ENR_TIM3EN
RCC_APB1ENR_TIM4EN
RCC_APB1ENR_TIM5EN
RCC_APB1ENR_TIM6EN
RCC_APB1ENR_TIM7EN
RCC_APB1ENR_UART4EN
RCC_APB1ENR_UART5EN
RCC_APB1ENR_USART2EN
RCC_APB1ENR_USART3EN
RCC_APB1ENR_USBEN
RCC_APB1ENR_WWDGEN
RCC_APB1RSTR_BKPRST
RCC_APB1RSTR_CAN1RST
RCC_APB1RSTR_CAN2RST
RCC_APB1RSTR_CANRST
RCC_APB1RSTR_DACRST
RCC_APB1RSTR_I2C1RST
RCC_APB1RSTR_I2C2RST
RCC_APB1RSTR_PWRRST
RCC_APB1RSTR_SPI2RST
RCC_APB1RSTR_SPI3RST
RCC_APB1RSTR_TIM2RST
RCC_APB1RSTR_TIM3RST
RCC_APB1RSTR_TIM4RST
RCC_APB1RSTR_TIM5RST
RCC_APB1RSTR_TIM6RST
RCC_APB1RSTR_TIM7RST
RCC_APB1RSTR_UART4RST
RCC_APB1RSTR_UART5RST
RCC_APB1RSTR_USART2RST
RCC_APB1RSTR_USART3RST
RCC_APB1RSTR_USBRST
RCC_APB1RSTR_WWDGRST
RCC_APB2ENR_ADC1EN
RCC_APB2ENR_ADC2EN
RCC_APB2ENR_ADC3EN
RCC_APB2ENR_AFIOEN
RCC_APB2ENR_IOPAEN
RCC_APB2ENR_IOPBEN
RCC_APB2ENR_IOPCEN
RCC_APB2ENR_IOPDEN
RCC_APB2ENR_IOPEEN
RCC_APB2ENR_IOPFEN
RCC_APB2ENR_IOPGEN
RCC_APB2ENR_SPI1EN
RCC_APB2ENR_TIM15EN
RCC_APB2ENR_TIM16EN
RCC_APB2ENR_TIM17EN
RCC_APB2ENR_TIM1EN
RCC_APB2ENR_TIM8EN
RCC_APB2ENR_USART1EN
RCC_APB2RSTR_ADC1RST
RCC_APB2RSTR_ADC2RST
RCC_APB2RSTR_ADC3RST
RCC_APB2RSTR_AFIORST
RCC_APB2RSTR_IOPARST
RCC_APB2RSTR_IOPBRST
RCC_APB2RSTR_IOPCRST
RCC_APB2RSTR_IOPDRST
RCC_APB2RSTR_IOPERST
RCC_APB2RSTR_IOPFRST
RCC_APB2RSTR_IOPGRST
RCC_APB2RSTR_SPI1RST
RCC_APB2RSTR_TIM15RST
RCC_APB2RSTR_TIM16RST
RCC_APB2RSTR_TIM17RST
RCC_APB2RSTR_TIM1RST
RCC_APB2RSTR_TIM8RST
RCC_APB2RSTR_USART1RST
RCC_BASE
RCC_BDCR_BDRST
RCC_BDCR_LSEBYP
RCC_BDCR_LSEON
RCC_BDCR_LSERDY
RCC_BDCR_RTCEN
RCC_CFGR2_I2S2SRC
RCC_CFGR2_I2S2SRC_PLL3_VCO_CLK
RCC_CFGR2_I2S2SRC_SYSCLK
RCC_CFGR2_I2S3SRC_PLL3_VCO_CLK
RCC_CFGR2_I2S3SRC_SYSCLK
RCC_CFGR2_PLL2MUL
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL8
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL9
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL10
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL11
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL12
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL13
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL14
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL16
RCC_CFGR2_PLL2MUL_PLL2_CLK_MUL20
RCC_CFGR2_PLL2MUL_SHIFT
RCC_CFGR2_PLL3MUL
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL8
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL9
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL10
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL11
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL12
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL13
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL14
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL16
RCC_CFGR2_PLL3MUL_PLL3_CLK_MUL20
RCC_CFGR2_PLL3MUL_SHIFT
RCC_CFGR2_PREDIV1
RCC_CFGR2_PREDIV2
RCC_CFGR2_PREDIV1SRC
RCC_CFGR2_PREDIV1SRC_HSE_CLK
RCC_CFGR2_PREDIV1SRC_PLL2_CLK
RCC_CFGR2_PREDIV1_SHIFT
RCC_CFGR2_PREDIV2_DIV2
RCC_CFGR2_PREDIV2_DIV3
RCC_CFGR2_PREDIV2_DIV4
RCC_CFGR2_PREDIV2_DIV5
RCC_CFGR2_PREDIV2_DIV6
RCC_CFGR2_PREDIV2_DIV7
RCC_CFGR2_PREDIV2_DIV8
RCC_CFGR2_PREDIV2_DIV9
RCC_CFGR2_PREDIV2_DIV10
RCC_CFGR2_PREDIV2_DIV11
RCC_CFGR2_PREDIV2_DIV12
RCC_CFGR2_PREDIV2_DIV13
RCC_CFGR2_PREDIV2_DIV14
RCC_CFGR2_PREDIV2_DIV15
RCC_CFGR2_PREDIV2_DIV16
RCC_CFGR2_PREDIV2_NODIV
RCC_CFGR2_PREDIV2_SHIFT
RCC_CFGR2_PREDIV_DIV2
RCC_CFGR2_PREDIV_DIV3
RCC_CFGR2_PREDIV_DIV4
RCC_CFGR2_PREDIV_DIV5
RCC_CFGR2_PREDIV_DIV6
RCC_CFGR2_PREDIV_DIV7
RCC_CFGR2_PREDIV_DIV8
RCC_CFGR2_PREDIV_DIV9
RCC_CFGR2_PREDIV_DIV10
RCC_CFGR2_PREDIV_DIV11
RCC_CFGR2_PREDIV_DIV12
RCC_CFGR2_PREDIV_DIV13
RCC_CFGR2_PREDIV_DIV14
RCC_CFGR2_PREDIV_DIV15
RCC_CFGR2_PREDIV_DIV16
RCC_CFGR2_PREDIV_NODIV
RCC_CFGR_ADCPRE
RCC_CFGR_ADCPRE_PCLK2_DIV2
RCC_CFGR_ADCPRE_PCLK2_DIV4
RCC_CFGR_ADCPRE_PCLK2_DIV6
RCC_CFGR_ADCPRE_PCLK2_DIV8
RCC_CFGR_ADCPRE_SHIFT
RCC_CFGR_HPRE
RCC_CFGR_HPRE_SHIFT
RCC_CFGR_HPRE_SYSCLK_DIV2
RCC_CFGR_HPRE_SYSCLK_DIV4
RCC_CFGR_HPRE_SYSCLK_DIV8
RCC_CFGR_HPRE_SYSCLK_DIV16
RCC_CFGR_HPRE_SYSCLK_DIV64
RCC_CFGR_HPRE_SYSCLK_DIV128
RCC_CFGR_HPRE_SYSCLK_DIV256
RCC_CFGR_HPRE_SYSCLK_DIV512
RCC_CFGR_HPRE_SYSCLK_NODIV
RCC_CFGR_MCO_HSE
RCC_CFGR_MCO_HSI
RCC_CFGR_MCO_MASK
RCC_CFGR_MCO_NOCLK
RCC_CFGR_MCO_PLL2
RCC_CFGR_MCO_PLL3
RCC_CFGR_MCO_PLL3_DIV2
RCC_CFGR_MCO_PLL_DIV2
RCC_CFGR_MCO_SHIFT
RCC_CFGR_MCO_SYSCLK
RCC_CFGR_MCO_XT1
RCC_CFGR_OTGFSPRE
RCC_CFGR_PLLMUL
RCC_CFGR_PLLMUL_PLL_CLK_MUL2
RCC_CFGR_PLLMUL_PLL_CLK_MUL3
RCC_CFGR_PLLMUL_PLL_CLK_MUL4
RCC_CFGR_PLLMUL_PLL_CLK_MUL5
RCC_CFGR_PLLMUL_PLL_CLK_MUL6
RCC_CFGR_PLLMUL_PLL_CLK_MUL7
RCC_CFGR_PLLMUL_PLL_CLK_MUL8
RCC_CFGR_PLLMUL_PLL_CLK_MUL9
RCC_CFGR_PLLMUL_PLL_CLK_MUL10
RCC_CFGR_PLLMUL_PLL_CLK_MUL11
RCC_CFGR_PLLMUL_PLL_CLK_MUL12
RCC_CFGR_PLLMUL_PLL_CLK_MUL13
RCC_CFGR_PLLMUL_PLL_CLK_MUL14
RCC_CFGR_PLLMUL_PLL_CLK_MUL15
RCC_CFGR_PLLMUL_PLL_CLK_MUL16
RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5
RCC_CFGR_PLLMUL_SHIFT
RCC_CFGR_PLLSRC
RCC_CFGR_PLLSRC_HSE_CLK
RCC_CFGR_PLLSRC_HSI_CLK_DIV2
RCC_CFGR_PLLSRC_PREDIV1_CLK
RCC_CFGR_PLLXTPRE
RCC_CFGR_PLLXTPRE_HSE_CLK
RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2
RCC_CFGR_PPRE1
RCC_CFGR_PPRE2
RCC_CFGR_PPRE1_HCLK_DIV2
RCC_CFGR_PPRE1_HCLK_DIV4
RCC_CFGR_PPRE1_HCLK_DIV8
RCC_CFGR_PPRE1_HCLK_DIV16
RCC_CFGR_PPRE1_HCLK_NODIV
RCC_CFGR_PPRE1_SHIFT
RCC_CFGR_PPRE2_HCLK_DIV2
RCC_CFGR_PPRE2_HCLK_DIV4
RCC_CFGR_PPRE2_HCLK_DIV8
RCC_CFGR_PPRE2_HCLK_DIV16
RCC_CFGR_PPRE2_HCLK_NODIV
RCC_CFGR_PPRE2_SHIFT
RCC_CFGR_SW
RCC_CFGR_SWS
RCC_CFGR_SWS_SHIFT
RCC_CFGR_SWS_SYSCLKSEL_HSECLK
RCC_CFGR_SWS_SYSCLKSEL_HSICLK
RCC_CFGR_SWS_SYSCLKSEL_PLLCLK
RCC_CFGR_SW_SHIFT
RCC_CFGR_SW_SYSCLKSEL_HSECLK
RCC_CFGR_SW_SYSCLKSEL_HSICLK
RCC_CFGR_SW_SYSCLKSEL_PLLCLK
RCC_CFGR_USBPRE
RCC_CFGR_USBPRE_PLL_CLK_DIV1_5
RCC_CFGR_USBPRE_PLL_CLK_NODIV
RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2
RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3
RCC_CIR_CSSC
RCC_CIR_CSSF
RCC_CIR_HSERDYC
RCC_CIR_HSERDYF
RCC_CIR_HSERDYIE
RCC_CIR_HSIRDYC
RCC_CIR_HSIRDYF
RCC_CIR_HSIRDYIE
RCC_CIR_LSERDYC
RCC_CIR_LSERDYF
RCC_CIR_LSERDYIE
RCC_CIR_LSIRDYC
RCC_CIR_LSIRDYF
RCC_CIR_LSIRDYIE
RCC_CIR_PLL2RDYC
RCC_CIR_PLL2RDYF
RCC_CIR_PLL2RDYIE
RCC_CIR_PLL3RDYC
RCC_CIR_PLL3RDYF
RCC_CIR_PLL3RDYIE
RCC_CIR_PLLRDYC
RCC_CIR_PLLRDYF
RCC_CIR_PLLRDYIE
RCC_CR_CSSON
RCC_CR_HSEBYP
RCC_CR_HSEON
RCC_CR_HSERDY
RCC_CR_HSION
RCC_CR_HSIRDY
RCC_CR_PLL2ON
RCC_CR_PLL2RDY
RCC_CR_PLL3ON
RCC_CR_PLL3RDY
RCC_CR_PLLON
RCC_CR_PLLRDY
RCC_CSR_IWDGRSTF
RCC_CSR_LPWRRSTF
RCC_CSR_LSION
RCC_CSR_LSIRDY
RCC_CSR_PINRSTF
RCC_CSR_PORRSTF
RCC_CSR_RESET_FLAGS
RCC_CSR_RMVF
RCC_CSR_SFTRSTF
RCC_CSR_WWDGRSTF
RTC_BASE
RTC_CRH_ALRIE
RTC_CRH_OWIE
RTC_CRH_SECIE
RTC_CRL_ALRF
RTC_CRL_CNF
RTC_CRL_OWF
RTC_CRL_RSF
RTC_CRL_RTOFF
RTC_CRL_SECF
SCB_AIRCR_ENDIANESS
SCB_AIRCR_SYSRESETREQ
SCB_AIRCR_VECTCLRACTIVE
SCB_AIRCR_VECTKEY
SCB_AIRCR_VECTKEYSTAT
SCB_AIRCR_VECTKEYSTAT_LSB
SCB_BASE
SCB_CCR_STKALIGN
SCB_CCR_UNALIGN_TRP
SCB_CPUID_CONSTANT
SCB_CPUID_CONSTANT_ARMV6
SCB_CPUID_CONSTANT_ARMV7
SCB_CPUID_CONSTANT_LSB
SCB_CPUID_IMPLEMENTER
SCB_CPUID_IMPLEMENTER_LSB
SCB_CPUID_PARTNO
SCB_CPUID_PARTNO_LSB
SCB_CPUID_REVISION
SCB_CPUID_REVISION_LSB
SCB_CPUID_VARIANT
SCB_CPUID_VARIANT_LSB
SCB_ICSR_ISRPENDING
SCB_ICSR_ISRPREEMPT
SCB_ICSR_NMIPENDSET
SCB_ICSR_PENDSTCLR
SCB_ICSR_PENDSTSET
SCB_ICSR_PENDSVCLR
SCB_ICSR_PENDSVSET
SCB_ICSR_RETOBASE
SCB_ICSR_VECTACTIVE
SCB_ICSR_VECTACTIVE_LSB
SCB_ICSR_VECTPENDING
SCB_ICSR_VECTPENDING_LSB
SCB_SCR_SEVONPEND
SCB_SCR_SLEEPDEEP
SCB_SCR_SLEEPONEXIT
SCB_SHCSR_SVCALLPENDED
SCB_SHPR_PRI_10_RESERVED
SCB_SHPR_PRI_11_SVCALL
SCB_SHPR_PRI_12_RESERVED
SCB_SHPR_PRI_13_RESERVED
SCB_SHPR_PRI_14_PENDSV
SCB_SHPR_PRI_15_SYSTICK
SCB_SHPR_PRI_4_MEMMANAGE
SCB_SHPR_PRI_5_BUSFAULT
SCB_SHPR_PRI_6_USAGEFAULT
SCB_SHPR_PRI_7_RESERVED
SCB_SHPR_PRI_8_RESERVED
SCB_SHPR_PRI_9_RESERVED
SCS_BASE
SCS_DCRSR_REGSEL_MASK
SCS_DCRSR_REGSEL_MSP
SCS_DCRSR_REGSEL_PSP
SCS_DCRSR_REGSEL_XPSR
SCS_DEMCR_MON_REQ
SCS_DEMCR_MON_STEP
SCS_DEMCR_TRCENA
SCS_DEMCR_VC_BUSERR
SCS_DEMCR_VC_CHKERR
SCS_DEMCR_VC_CORERESET
SCS_DEMCR_VC_HARDERR
SCS_DEMCR_VC_INTERR
SCS_DEMCR_VC_MMERR
SCS_DEMCR_VC_MON_EN
SCS_DEMCR_VC_MON_PEND
SCS_DEMCR_VC_NOCPERR
SCS_DEMCR_VC_STATERR
SCS_DHCSR_C_DEBUGEN
SCS_DHCSR_C_HALT
SCS_DHCSR_C_MASKINTS
SCS_DHCSR_C_SNAPSTALL
SCS_DHCSR_C_STEP
SCS_DHCSR_DBGKEY
SCS_DHCSR_S_HALT
SCS_DHCSR_S_LOCKUP
SCS_DHCSR_S_REGRDY
SCS_DHCSR_S_RESET_ST
SCS_DHCSR_S_RETIRE_ST
SCS_DHCSR_S_SLEEP
SCS_DWT_CTRL_CYCCNTENA
SCS_LAR_KEY
SCS_LSR_SLI
SCS_LSR_SLK
SCS_SYST_CSR_CLKSOURCE
SCS_SYST_CSR_COUNTFLAG
SCS_SYST_CSR_ENABLE
SCS_SYST_CSR_TICKINT
SCS_SYST_SYST_CALIB_REF_NOT_IMPLEMENTED
SCS_SYST_SYST_CALIB_TENMS_MASK
SCS_SYST_SYST_CALIB_VALUE_INEXACT
SDIO_BASE
SIG_ATOMIC_MAX
SIG_ATOMIC_MIN
SIZE_MAX
SPI1
SPI2
SPI3
SPI1_BASE
SPI2_BASE
SPI3_BASE
SPI_CR1_BAUDRATE_FPCLK_DIV_2
SPI_CR1_BAUDRATE_FPCLK_DIV_4
SPI_CR1_BAUDRATE_FPCLK_DIV_8
SPI_CR1_BAUDRATE_FPCLK_DIV_16
SPI_CR1_BAUDRATE_FPCLK_DIV_32
SPI_CR1_BAUDRATE_FPCLK_DIV_64
SPI_CR1_BAUDRATE_FPCLK_DIV_128
SPI_CR1_BAUDRATE_FPCLK_DIV_256
SPI_CR1_BIDIMODE
SPI_CR1_BIDIMODE_1LINE_BIDIR
SPI_CR1_BIDIMODE_2LINE_UNIDIR
SPI_CR1_BIDIOE
SPI_CR1_BR_FPCLK_DIV_2
SPI_CR1_BR_FPCLK_DIV_4
SPI_CR1_BR_FPCLK_DIV_8
SPI_CR1_BR_FPCLK_DIV_16
SPI_CR1_BR_FPCLK_DIV_32
SPI_CR1_BR_FPCLK_DIV_64
SPI_CR1_BR_FPCLK_DIV_128
SPI_CR1_BR_FPCLK_DIV_256
SPI_CR1_CPHA
SPI_CR1_CPHA_CLK_TRANSITION_1
SPI_CR1_CPHA_CLK_TRANSITION_2
SPI_CR1_CPOL
SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE
SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE
SPI_CR1_CRCEN
SPI_CR1_CRCNEXT
SPI_CR1_DFF
SPI_CR1_DFF_16BIT
SPI_CR1_DFF_8BIT
SPI_CR1_LSBFIRST
SPI_CR1_MSBFIRST
SPI_CR1_MSTR
SPI_CR1_RXONLY
SPI_CR1_SPE
SPI_CR1_SSI
SPI_CR1_SSM
SPI_CR2_ERRIE
SPI_CR2_RXDMAEN
SPI_CR2_RXNEIE
SPI_CR2_SSOE
SPI_CR2_TXDMAEN
SPI_CR2_TXEIE
SPI_I2SCFGR_CHLEN
SPI_I2SCFGR_CKPOL
SPI_I2SCFGR_DATLEN_16BIT
SPI_I2SCFGR_DATLEN_24BIT
SPI_I2SCFGR_DATLEN_32BIT
SPI_I2SCFGR_DATLEN_LSB
SPI_I2SCFGR_I2SCFG_LSB
SPI_I2SCFGR_I2SCFG_MASTER_RECEIVE
SPI_I2SCFGR_I2SCFG_MASTER_TRANSMIT
SPI_I2SCFGR_I2SCFG_SLAVE_RECEIVE
SPI_I2SCFGR_I2SCFG_SLAVE_TRANSMIT
SPI_I2SCFGR_I2SE
SPI_I2SCFGR_I2SMOD
SPI_I2SCFGR_I2SSTD_I2S_PHILIPS
SPI_I2SCFGR_I2SSTD_LSB
SPI_I2SCFGR_I2SSTD_LSB_JUSTIFIED
SPI_I2SCFGR_I2SSTD_MSB_JUSTIFIED
SPI_I2SCFGR_I2SSTD_PCM
SPI_I2SCFGR_PCMSYNC
SPI_I2SPR_MCKOE
SPI_I2SPR_ODD
SPI_SR_BSY
SPI_SR_CHSIDE
SPI_SR_CRCERR
SPI_SR_MODF
SPI_SR_OVR
SPI_SR_RXNE
SPI_SR_TXE
SPI_SR_UDR
STK_CALIB_NOREF
STK_CALIB_SKEW
STK_CALIB_TENMS
STK_CSR_CLKSOURCE
STK_CSR_CLKSOURCE_AHB
STK_CSR_CLKSOURCE_AHB_DIV8
STK_CSR_CLKSOURCE_LSB
STK_CSR_COUNTFLAG
STK_CSR_ENABLE
STK_CSR_TICKINT
STK_CVR_CURRENT
STK_RVR_RELOAD
SYS_TICK_BASE
TIM1
TIM2
TIM3
TIM4
TIM5
TIM6
TIM7
TIM8
TIM9
TIM10
TIM11
TIM12
TIM13
TIM14
TIM15
TIM16
TIM17
TIM10_BASE
TIM11_BASE
TIM12_BASE
TIM13_BASE
TIM14_BASE
TIM15_BASE
TIM16_BASE
TIM17_BASE
TIM1_BASE
TIM2_BASE
TIM3_BASE
TIM4_BASE
TIM5_BASE
TIM6_BASE
TIM7_BASE
TIM8_BASE
TIM9_BASE
TIM_BDTR_AOE
TIM_BDTR_BKE
TIM_BDTR_BKP
TIM_BDTR_DBA_MASK
TIM_BDTR_DBL_MASK
TIM_BDTR_DTG_MASK
TIM_BDTR_LOCK_LEVEL_1
TIM_BDTR_LOCK_LEVEL_2
TIM_BDTR_LOCK_LEVEL_3
TIM_BDTR_LOCK_MASK
TIM_BDTR_LOCK_OFF
TIM_BDTR_MOE
TIM_BDTR_OSSI
TIM_BDTR_OSSR
TIM_CCER_CC1E
TIM_CCER_CC1NE
TIM_CCER_CC1NP
TIM_CCER_CC1P
TIM_CCER_CC2E
TIM_CCER_CC2NE
TIM_CCER_CC2NP
TIM_CCER_CC2P
TIM_CCER_CC3E
TIM_CCER_CC3NE
TIM_CCER_CC3NP
TIM_CCER_CC3P
TIM_CCER_CC4E
TIM_CCER_CC4NP
TIM_CCER_CC4P
TIM_CCMR1_CC1S_IN_TI1
TIM_CCMR1_CC1S_IN_TI2
TIM_CCMR1_CC1S_IN_TRC
TIM_CCMR1_CC1S_MASK
TIM_CCMR1_CC1S_OUT
TIM_CCMR1_CC2S_IN_TI1
TIM_CCMR1_CC2S_IN_TI2
TIM_CCMR1_CC2S_IN_TRC
TIM_CCMR1_CC2S_MASK
TIM_CCMR1_CC2S_OUT
TIM_CCMR1_IC1F_CK_INT_N_2
TIM_CCMR1_IC1F_CK_INT_N_4
TIM_CCMR1_IC1F_CK_INT_N_8
TIM_CCMR1_IC1F_DTF_DIV_16_N_5
TIM_CCMR1_IC1F_DTF_DIV_16_N_6
TIM_CCMR1_IC1F_DTF_DIV_16_N_8
TIM_CCMR1_IC1F_DTF_DIV_2_N_6
TIM_CCMR1_IC1F_DTF_DIV_2_N_8
TIM_CCMR1_IC1F_DTF_DIV_32_N_5
TIM_CCMR1_IC1F_DTF_DIV_32_N_6
TIM_CCMR1_IC1F_DTF_DIV_32_N_8
TIM_CCMR1_IC1F_DTF_DIV_4_N_6
TIM_CCMR1_IC1F_DTF_DIV_4_N_8
TIM_CCMR1_IC1F_DTF_DIV_8_N_6
TIM_CCMR1_IC1F_DTF_DIV_8_N_8
TIM_CCMR1_IC1F_MASK
TIM_CCMR1_IC1F_OFF
TIM_CCMR1_IC1PSC_2
TIM_CCMR1_IC1PSC_4
TIM_CCMR1_IC1PSC_8
TIM_CCMR1_IC1PSC_MASK
TIM_CCMR1_IC1PSC_OFF
TIM_CCMR1_IC2F_CK_INT_N_2
TIM_CCMR1_IC2F_CK_INT_N_4
TIM_CCMR1_IC2F_CK_INT_N_8
TIM_CCMR1_IC2F_DTF_DIV_16_N_5
TIM_CCMR1_IC2F_DTF_DIV_16_N_6
TIM_CCMR1_IC2F_DTF_DIV_16_N_8
TIM_CCMR1_IC2F_DTF_DIV_2_N_6
TIM_CCMR1_IC2F_DTF_DIV_2_N_8
TIM_CCMR1_IC2F_DTF_DIV_32_N_5
TIM_CCMR1_IC2F_DTF_DIV_32_N_6
TIM_CCMR1_IC2F_DTF_DIV_32_N_8
TIM_CCMR1_IC2F_DTF_DIV_4_N_6
TIM_CCMR1_IC2F_DTF_DIV_4_N_8
TIM_CCMR1_IC2F_DTF_DIV_8_N_6
TIM_CCMR1_IC2F_DTF_DIV_8_N_8
TIM_CCMR1_IC2F_MASK
TIM_CCMR1_IC2F_OFF
TIM_CCMR1_IC2PSC_2
TIM_CCMR1_IC2PSC_4
TIM_CCMR1_IC2PSC_8
TIM_CCMR1_IC2PSC_MASK
TIM_CCMR1_IC2PSC_OFF
TIM_CCMR1_OC1CE
TIM_CCMR1_OC1FE
TIM_CCMR1_OC1M_ACTIVE
TIM_CCMR1_OC1M_FORCE_HIGH
TIM_CCMR1_OC1M_FORCE_LOW
TIM_CCMR1_OC1M_FROZEN
TIM_CCMR1_OC1M_INACTIVE
TIM_CCMR1_OC1M_MASK
TIM_CCMR1_OC1M_PWM1
TIM_CCMR1_OC1M_PWM2
TIM_CCMR1_OC1M_TOGGLE
TIM_CCMR1_OC1PE
TIM_CCMR1_OC2CE
TIM_CCMR1_OC2FE
TIM_CCMR1_OC2M_ACTIVE
TIM_CCMR1_OC2M_FORCE_HIGH
TIM_CCMR1_OC2M_FORCE_LOW
TIM_CCMR1_OC2M_FROZEN
TIM_CCMR1_OC2M_INACTIVE
TIM_CCMR1_OC2M_MASK
TIM_CCMR1_OC2M_PWM1
TIM_CCMR1_OC2M_PWM2
TIM_CCMR1_OC2M_TOGGLE
TIM_CCMR1_OC2PE
TIM_CCMR2_CC3S_IN_TI3
TIM_CCMR2_CC3S_IN_TI4
TIM_CCMR2_CC3S_IN_TRC
TIM_CCMR2_CC3S_MASK
TIM_CCMR2_CC3S_OUT
TIM_CCMR2_CC4S_IN_TI3
TIM_CCMR2_CC4S_IN_TI4
TIM_CCMR2_CC4S_IN_TRC
TIM_CCMR2_CC4S_MASK
TIM_CCMR2_CC4S_OUT
TIM_CCMR2_IC3F_CK_INT_N_2
TIM_CCMR2_IC3F_CK_INT_N_4
TIM_CCMR2_IC3F_CK_INT_N_8
TIM_CCMR2_IC3F_DTF_DIV_16_N_5
TIM_CCMR2_IC3F_DTF_DIV_16_N_6
TIM_CCMR2_IC3F_DTF_DIV_16_N_8
TIM_CCMR2_IC3F_DTF_DIV_2_N_6
TIM_CCMR2_IC3F_DTF_DIV_2_N_8
TIM_CCMR2_IC3F_DTF_DIV_32_N_5
TIM_CCMR2_IC3F_DTF_DIV_32_N_6
TIM_CCMR2_IC3F_DTF_DIV_32_N_8
TIM_CCMR2_IC3F_DTF_DIV_4_N_6
TIM_CCMR2_IC3F_DTF_DIV_4_N_8
TIM_CCMR2_IC3F_DTF_DIV_8_N_6
TIM_CCMR2_IC3F_DTF_DIV_8_N_8
TIM_CCMR2_IC3F_MASK
TIM_CCMR2_IC3F_OFF
TIM_CCMR2_IC3PSC_2
TIM_CCMR2_IC3PSC_4
TIM_CCMR2_IC3PSC_8
TIM_CCMR2_IC3PSC_MASK
TIM_CCMR2_IC3PSC_OFF
TIM_CCMR2_IC4F_CK_INT_N_2
TIM_CCMR2_IC4F_CK_INT_N_4
TIM_CCMR2_IC4F_CK_INT_N_8
TIM_CCMR2_IC4F_DTF_DIV_16_N_5
TIM_CCMR2_IC4F_DTF_DIV_16_N_6
TIM_CCMR2_IC4F_DTF_DIV_16_N_8
TIM_CCMR2_IC4F_DTF_DIV_2_N_6
TIM_CCMR2_IC4F_DTF_DIV_2_N_8
TIM_CCMR2_IC4F_DTF_DIV_32_N_5
TIM_CCMR2_IC4F_DTF_DIV_32_N_6
TIM_CCMR2_IC4F_DTF_DIV_32_N_8
TIM_CCMR2_IC4F_DTF_DIV_4_N_6
TIM_CCMR2_IC4F_DTF_DIV_4_N_8
TIM_CCMR2_IC4F_DTF_DIV_8_N_6
TIM_CCMR2_IC4F_DTF_DIV_8_N_8
TIM_CCMR2_IC4F_MASK
TIM_CCMR2_IC4F_OFF
TIM_CCMR2_IC4PSC_2
TIM_CCMR2_IC4PSC_4
TIM_CCMR2_IC4PSC_8
TIM_CCMR2_IC4PSC_MASK
TIM_CCMR2_IC4PSC_OFF
TIM_CCMR2_OC3CE
TIM_CCMR2_OC3FE
TIM_CCMR2_OC3M_ACTIVE
TIM_CCMR2_OC3M_FORCE_HIGH
TIM_CCMR2_OC3M_FORCE_LOW
TIM_CCMR2_OC3M_FROZEN
TIM_CCMR2_OC3M_INACTIVE
TIM_CCMR2_OC3M_MASK
TIM_CCMR2_OC3M_PWM1
TIM_CCMR2_OC3M_PWM2
TIM_CCMR2_OC3M_TOGGLE
TIM_CCMR2_OC3PE
TIM_CCMR2_OC4CE
TIM_CCMR2_OC4FE
TIM_CCMR2_OC4M_ACTIVE
TIM_CCMR2_OC4M_FORCE_HIGH
TIM_CCMR2_OC4M_FORCE_LOW
TIM_CCMR2_OC4M_FROZEN
TIM_CCMR2_OC4M_INACTIVE
TIM_CCMR2_OC4M_MASK
TIM_CCMR2_OC4M_PWM1
TIM_CCMR2_OC4M_PWM2
TIM_CCMR2_OC4M_TOGGLE
TIM_CCMR2_OC4PE
TIM_CR1_ARPE
TIM_CR1_CEN
TIM_CR1_CKD_CK_INT
TIM_CR1_CKD_CK_INT_MASK
TIM_CR1_CKD_CK_INT_MUL_2
TIM_CR1_CKD_CK_INT_MUL_4
TIM_CR1_CMS_CENTER_1
TIM_CR1_CMS_CENTER_2
TIM_CR1_CMS_CENTER_3
TIM_CR1_CMS_EDGE
TIM_CR1_CMS_MASK
TIM_CR1_DIR_DOWN
TIM_CR1_DIR_UP
TIM_CR1_OPM
TIM_CR1_UDIS
TIM_CR1_URS
TIM_CR2_CCDS
TIM_CR2_CCPC
TIM_CR2_CCUS
TIM_CR2_MMS_COMPARE_OC1REF
TIM_CR2_MMS_COMPARE_OC2REF
TIM_CR2_MMS_COMPARE_OC3REF
TIM_CR2_MMS_COMPARE_OC4REF
TIM_CR2_MMS_COMPARE_PULSE
TIM_CR2_MMS_ENABLE
TIM_CR2_MMS_MASK
TIM_CR2_MMS_RESET
TIM_CR2_MMS_UPDATE
TIM_CR2_OIS1
TIM_CR2_OIS2
TIM_CR2_OIS3
TIM_CR2_OIS4
TIM_CR2_OIS1N
TIM_CR2_OIS2N
TIM_CR2_OIS3N
TIM_CR2_OIS_MASK
TIM_CR2_TI1S
TIM_DIER_BIE
TIM_DIER_CC1DE
TIM_DIER_CC1IE
TIM_DIER_CC2DE
TIM_DIER_CC2IE
TIM_DIER_CC3DE
TIM_DIER_CC3IE
TIM_DIER_CC4DE
TIM_DIER_CC4IE
TIM_DIER_COMDE
TIM_DIER_COMIE
TIM_DIER_TDE
TIM_DIER_TIE
TIM_DIER_UDE
TIM_DIER_UIE
TIM_EGR_BG
TIM_EGR_CC1G
TIM_EGR_CC2G
TIM_EGR_CC3G
TIM_EGR_CC4G
TIM_EGR_COMG
TIM_EGR_TG
TIM_EGR_UG
TIM_SMCR_ECE
TIM_SMCR_ETF_CK_INT_N_2
TIM_SMCR_ETF_CK_INT_N_4
TIM_SMCR_ETF_CK_INT_N_8
TIM_SMCR_ETF_DTS_DIV_16_N_5
TIM_SMCR_ETF_DTS_DIV_16_N_6
TIM_SMCR_ETF_DTS_DIV_16_N_8
TIM_SMCR_ETF_DTS_DIV_2_N_6
TIM_SMCR_ETF_DTS_DIV_2_N_8
TIM_SMCR_ETF_DTS_DIV_32_N_5
TIM_SMCR_ETF_DTS_DIV_32_N_6
TIM_SMCR_ETF_DTS_DIV_32_N_8
TIM_SMCR_ETF_DTS_DIV_4_N_6
TIM_SMCR_ETF_DTS_DIV_4_N_8
TIM_SMCR_ETF_DTS_DIV_8_N_6
TIM_SMCR_ETF_DTS_DIV_8_N_8
TIM_SMCR_ETF_MASK
TIM_SMCR_ETF_OFF
TIM_SMCR_ETP
TIM_SMCR_ETPS_ETRP_DIV_2
TIM_SMCR_ETPS_ETRP_DIV_4
TIM_SMCR_ETPS_ETRP_DIV_8
TIM_SMCR_ETPS_OFF
TIM_SMCR_MSM
TIM_SMCR_SMS_ECM1
TIM_SMCR_SMS_EM1
TIM_SMCR_SMS_EM2
TIM_SMCR_SMS_EM3
TIM_SMCR_SMS_GM
TIM_SMCR_SMS_MASK
TIM_SMCR_SMS_OFF
TIM_SMCR_SMS_RM
TIM_SMCR_SMS_TM
TIM_SMCR_TS_ETRF
TIM_SMCR_TS_ITR0
TIM_SMCR_TS_ITR1
TIM_SMCR_TS_ITR2
TIM_SMCR_TS_ITR3
TIM_SMCR_TS_MASK
TIM_SMCR_TS_TI1FP1
TIM_SMCR_TS_TI1F_ED
TIM_SMCR_TS_TI2FP2
TIM_SR_BIF
TIM_SR_CC1IF
TIM_SR_CC1OF
TIM_SR_CC2IF
TIM_SR_CC2OF
TIM_SR_CC3IF
TIM_SR_CC3OF
TIM_SR_CC4IF
TIM_SR_CC4OF
TIM_SR_COMIF
TIM_SR_TIF
TIM_SR_UIF
UART4
UART5
UART4_BASE
UART5_BASE
UINT16_MAX
UINT32_MAX
UINT8_MAX
UINTPTR_MAX
UINT_FAST16_MAX
UINT_FAST32_MAX
UINT_FAST8_MAX
UINT_LEAST16_MAX
UINT_LEAST32_MAX
UINT_LEAST8_MAX
USART1
USART2
USART3
USART1_BASE
USART2_BASE
USART3_BASE
USART_BRR_DIV_FRACTION_MASK
USART_BRR_DIV_MANTISSA_MASK
USART_CR1_IDLEIE
USART_CR1_M
USART_CR1_PCE
USART_CR1_PEIE
USART_CR1_PS
USART_CR1_RE
USART_CR1_RWU
USART_CR1_RXNEIE
USART_CR1_SBK
USART_CR1_TCIE
USART_CR1_TE
USART_CR1_TXEIE
USART_CR1_UE
USART_CR1_WAKE
USART_CR2_ADD_MASK
USART_CR2_CLKEN
USART_CR2_CPHA
USART_CR2_CPOL
USART_CR2_LBCL
USART_CR2_LBDIE
USART_CR2_LBDL
USART_CR2_LINEN
USART_CR2_STOPBITS_1
USART_CR2_STOPBITS_2
USART_CR2_STOPBITS_0_5
USART_CR2_STOPBITS_1_5
USART_CR2_STOPBITS_MASK
USART_CR2_STOPBITS_SHIFT
USART_CR3_CTSE
USART_CR3_CTSIE
USART_CR3_DMAR
USART_CR3_DMAT
USART_CR3_EIE
USART_CR3_HDSEL
USART_CR3_IREN
USART_CR3_IRLP
USART_CR3_NACK
USART_CR3_RTSE
USART_CR3_SCEN
USART_DR_MASK
USART_FLOWCONTROL_NONE
USART_GTPR_GT_MASK
USART_GTPR_PSC_MASK
USART_PARITY_NONE
USART_SR_CTS
USART_SR_FE
USART_SR_IDLE
USART_SR_LBD
USART_SR_NE
USART_SR_ORE
USART_SR_PE
USART_SR_RXNE
USART_SR_TC
USART_SR_TXE
USB_AUDIO_DT_CS_CONFIGURATION
USB_AUDIO_DT_CS_DEVICE
USB_AUDIO_DT_CS_ENDPOINT
USB_AUDIO_DT_CS_INTERFACE
USB_AUDIO_DT_CS_STRING
USB_AUDIO_DT_CS_UNDEFINED
USB_AUDIO_SUBCLASS_AUDIOSTREAMING
USB_AUDIO_SUBCLASS_CONTROL
USB_AUDIO_SUBCLASS_MIDISTREAMING
USB_AUDIO_SUBCLASS_UNDEFINED
USB_AUDIO_TYPE_AC_DESCRIPTOR_UNDEFINED
USB_AUDIO_TYPE_EXTENSION_UNIT
USB_AUDIO_TYPE_FEATURE_UNIT
USB_AUDIO_TYPE_HEADER
USB_AUDIO_TYPE_INPUT_TERMINAL
USB_AUDIO_TYPE_MIXER_UNIT
USB_AUDIO_TYPE_OUTPUT_TERMINAL
USB_AUDIO_TYPE_PROCESSING_UNIT
USB_AUDIO_TYPE_SELECTOR_UNIT
USB_BTABLE_BTABLE
USB_CAN_SRAM_BASE
USB_CDC_NOTIFY_SERIAL_STATE
USB_CDC_PROTOCOL_AT
USB_CDC_PROTOCOL_NONE
USB_CDC_REQ_SET_CONTROL_LINE_STATE
USB_CDC_REQ_SET_LINE_CODING
USB_CDC_SUBCLASS_ACM
USB_CDC_SUBCLASS_DLCM
USB_CDC_TYPE_ACM
USB_CDC_TYPE_CALL_MANAGEMENT
USB_CDC_TYPE_HEADER
USB_CDC_TYPE_UNION
USB_CLASS_AUDIO
USB_CLASS_CDC
USB_CLASS_DATA
USB_CLASS_HID
USB_CLASS_MSC
USB_CLASS_VENDOR
USB_CNTR_CTRM
USB_CNTR_ERRM
USB_CNTR_ESOFM
USB_CNTR_FRES
USB_CNTR_FSUSP
USB_CNTR_LP_MODE
USB_CNTR_PMAOVRM
USB_CNTR_PWDN
USB_CNTR_RESETM
USB_CNTR_RESUME
USB_CNTR_SOFM
USB_CNTR_SUSPM
USB_CNTR_WKUPM
USB_CONFIG_ATTR_DEFAULT
USB_CONFIG_ATTR_REMOTE_WAKEUP
USB_CONFIG_ATTR_SELF_POWERED
USB_DADDR_ADDR
USB_DADDR_EF
USB_DEV_FS_BASE
USB_DEV_STATUS_REMOTE_WAKEUP
USB_DEV_STATUS_SELF_POWERED
USB_DFU_CAN_DOWNLOAD
USB_DFU_CAN_UPLOAD
USB_DFU_MANIFEST_TOLERANT
USB_DFU_WILL_DETACH
USB_DT_CONFIGURATION
USB_DT_CONFIGURATION_SIZE
USB_DT_DEBUG
USB_DT_DEVICE
USB_DT_DEVICE_QUALIFIER
USB_DT_ENDPOINT
USB_DT_ENDPOINT_SIZE
USB_DT_HID
USB_DT_INTERFACE
USB_DT_INTERFACE_ASSOCIATION
USB_DT_INTERFACE_POWER
USB_DT_INTERFACE_SIZE
USB_DT_OTG
USB_DT_OTHER_SPEED_CONFIGURATION
USB_DT_REPORT
USB_DT_STRING
USB_ENDPOINT_ATTR_ADAPTIVE
USB_ENDPOINT_ATTR_ASYNC
USB_ENDPOINT_ATTR_BULK
USB_ENDPOINT_ATTR_CONTROL
USB_ENDPOINT_ATTR_DATA
USB_ENDPOINT_ATTR_FEEDBACK
USB_ENDPOINT_ATTR_IMPLICIT_FEEDBACK_DATA
USB_ENDPOINT_ATTR_INTERRUPT
USB_ENDPOINT_ATTR_ISOCHRONOUS
USB_ENDPOINT_ATTR_NOSYNC
USB_ENDPOINT_ATTR_SYNC
USB_ENDPOINT_ATTR_SYNCTYPE
USB_ENDPOINT_ATTR_TYPE
USB_ENDPOINT_ATTR_USAGETYPE
USB_EP0
USB_EP1
USB_EP2
USB_EP3
USB_EP4
USB_EP5
USB_EP6
USB_EP7
USB_EP_ADDR
USB_EP_KIND
USB_EP_NTOGGLE_MSK
USB_EP_RX_CTR
USB_EP_RX_DTOG
USB_EP_RX_STAT
USB_EP_RX_STAT_DISABLED
USB_EP_RX_STAT_NAK
USB_EP_RX_STAT_STALL
USB_EP_RX_STAT_TOG_MSK
USB_EP_RX_STAT_VALID
USB_EP_SETUP
USB_EP_TX_CTR
USB_EP_TX_DTOG
USB_EP_TX_STAT
USB_EP_TX_STAT_DISABLED
USB_EP_TX_STAT_NAK
USB_EP_TX_STAT_STALL
USB_EP_TX_STAT_TOG_MSK
USB_EP_TX_STAT_VALID
USB_EP_TYPE
USB_EP_TYPE_BULK
USB_EP_TYPE_CONTROL
USB_EP_TYPE_INTERRUPT
USB_EP_TYPE_ISO
USB_FEAT_DEVICE_REMOTE_WAKEUP
USB_FEAT_ENDPOINT_HALT
USB_FEAT_TEST_MODE
USB_FNR_FN
USB_FNR_LCK
USB_FNR_LSOF
USB_FNR_LSOF_SHIFT
USB_FNR_RXDM
USB_FNR_RXDP
USB_ISTR_CTR
USB_ISTR_DIR
USB_ISTR_EP_ID
USB_ISTR_ERR
USB_ISTR_ESOF
USB_ISTR_PMAOVR
USB_ISTR_RESET
USB_ISTR_SOF
USB_ISTR_SUSP
USB_ISTR_WKUP
USB_MIDI_ASSOCIATION_CONTROL
USB_MIDI_EP_CONTROL_UNDEFINED
USB_MIDI_JACK_TYPE_EMBEDDED
USB_MIDI_JACK_TYPE_EXTERNAL
USB_MIDI_JACK_TYPE_UNDEFINED
USB_MIDI_SUBTYPE_DESCRIPTOR_UNDEFINED
USB_MIDI_SUBTYPE_MIDI_ELEMENT
USB_MIDI_SUBTYPE_MIDI_IN_JACK
USB_MIDI_SUBTYPE_MIDI_OUT_JACK
USB_MIDI_SUBTYPE_MS_DESCRIPTOR_UNDEFINED
USB_MIDI_SUBTYPE_MS_GENERAL
USB_MIDI_SUBTYPE_MS_HEADER
USB_MSC_PROTOCOL_BBB
USB_MSC_PROTOCOL_CBI
USB_MSC_PROTOCOL_CBI_ALT
USB_MSC_REQ_BULK_ONLY_RESET
USB_MSC_REQ_CODES_ADSC
USB_MSC_REQ_CODES_BOMSR
USB_MSC_REQ_CODES_GET
USB_MSC_REQ_CODES_GML
USB_MSC_REQ_CODES_PUT
USB_MSC_REQ_GET_MAX_LUN
USB_MSC_SUBCLASS_ATAPI
USB_MSC_SUBCLASS_IEEE1667
USB_MSC_SUBCLASS_LOCKABLE
USB_MSC_SUBCLASS_RBC
USB_MSC_SUBCLASS_SCSI
USB_MSC_SUBCLASS_UFI
USB_OTG_FS_BASE
USB_PMA_BASE
USB_REQ_CLEAR_FEATURE
USB_REQ_GET_CONFIGURATION
USB_REQ_GET_DESCRIPTOR
USB_REQ_GET_INTERFACE
USB_REQ_GET_STATUS
USB_REQ_SET_ADDRESS
USB_REQ_SET_CONFIGURATION
USB_REQ_SET_DESCRIPTOR
USB_REQ_SET_FEATURE
USB_REQ_SET_INTERFACE
USB_REQ_SET_SYNCH_FRAME
USB_REQ_TYPE_CLASS
USB_REQ_TYPE_DEVICE
USB_REQ_TYPE_DIRECTION
USB_REQ_TYPE_ENDPOINT
USB_REQ_TYPE_IN
USB_REQ_TYPE_INTERFACE
USB_REQ_TYPE_OTHER
USB_REQ_TYPE_RECIPIENT
USB_REQ_TYPE_STANDARD
USB_REQ_TYPE_TYPE
USB_REQ_TYPE_VENDOR
WINT_MAX
WINT_MIN
WWDG_BASE
_ATFILE_SOURCE
_BITS_WCHAR_H
_DEFAULT_SOURCE
_FEATURES_H
_POSIX_C_SOURCE
_POSIX_SOURCE
_STDC_PREDEF_H
_STDINT_H
_SYS_CDEFS_H
__GLIBC_MINOR__
__GLIBC__
__GNU_LIBRARY__
__STDC_IEC_559_COMPLEX__
__STDC_IEC_559__
__STDC_ISO_10646__
__STDC_NO_THREADS__
__SYSCALL_WORDSIZE
__USE_ATFILE
__USE_FORTIFY_LEVEL
__USE_ISOC11
__USE_ISOC95
__USE_ISOC99
__USE_MISC
__USE_POSIX
__USE_POSIX2
__USE_POSIX199309
__USE_POSIX199506
__USE_POSIX_IMPLICITLY
__USE_XOPEN2K
__USE_XOPEN2K8
__WORDSIZE
__WORDSIZE_TIME64_COMPAT32
__bool_true_false_are_defined
data_align_LEFT12
data_align_RIGHT8
data_align_RIGHT12
data_channel_CHANNEL_1
data_channel_CHANNEL_2
data_channel_CHANNEL_D
dfu_req_DFU_ABORT
dfu_req_DFU_CLRSTATUS
dfu_req_DFU_DETACH
dfu_req_DFU_DNLOAD
dfu_req_DFU_GETSTATE
dfu_req_DFU_GETSTATUS
dfu_req_DFU_UPLOAD
dfu_state_STATE_APP_DETACH
dfu_state_STATE_APP_IDLE
dfu_state_STATE_DFU_DNBUSY
dfu_state_STATE_DFU_DNLOAD_IDLE
dfu_state_STATE_DFU_DNLOAD_SYNC
dfu_state_STATE_DFU_ERROR
dfu_state_STATE_DFU_IDLE
dfu_state_STATE_DFU_MANIFEST
dfu_state_STATE_DFU_MANIFEST_SYNC
dfu_state_STATE_DFU_MANIFEST_WAIT_RESET
dfu_state_STATE_DFU_UPLOAD_IDLE
dfu_status_DFU_STATUS_ERR_ADDRESS
dfu_status_DFU_STATUS_ERR_CHECK_ERASED
dfu_status_DFU_STATUS_ERR_ERASE
dfu_status_DFU_STATUS_ERR_FILE
dfu_status_DFU_STATUS_ERR_FIRMWARE
dfu_status_DFU_STATUS_ERR_NOTDONE
dfu_status_DFU_STATUS_ERR_POR
dfu_status_DFU_STATUS_ERR_PROG
dfu_status_DFU_STATUS_ERR_STALLEDPKT
dfu_status_DFU_STATUS_ERR_TARGET
dfu_status_DFU_STATUS_ERR_UNKNOWN
dfu_status_DFU_STATUS_ERR_USBR
dfu_status_DFU_STATUS_ERR_VENDOR
dfu_status_DFU_STATUS_ERR_VERIFY
dfu_status_DFU_STATUS_ERR_WRITE
dfu_status_DFU_STATUS_OK
exti_trigger_type_EXTI_TRIGGER_BOTH
exti_trigger_type_EXTI_TRIGGER_FALLING
exti_trigger_type_EXTI_TRIGGER_RISING
false_
i2c_speeds_i2c_speed_fm_400k
i2c_speeds_i2c_speed_fmp_1m
i2c_speeds_i2c_speed_sm_100k
i2c_speeds_i2c_speed_unknown
rcc_osc_RCC_HSE
rcc_osc_RCC_HSI
rcc_osc_RCC_LSE
rcc_osc_RCC_LSI
rcc_osc_RCC_PLL
rcc_osc_RCC_PLL2
rcc_osc_RCC_PLL3
rcc_periph_clken_RCC_ADC1
rcc_periph_clken_RCC_ADC2
rcc_periph_clken_RCC_ADC3
rcc_periph_clken_RCC_AFIO
rcc_periph_clken_RCC_BKP
rcc_periph_clken_RCC_CAN
rcc_periph_clken_RCC_CAN1
rcc_periph_clken_RCC_CAN2
rcc_periph_clken_RCC_CEC
rcc_periph_clken_RCC_CRC
rcc_periph_clken_RCC_DAC
rcc_periph_clken_RCC_DMA1
rcc_periph_clken_RCC_DMA2
rcc_periph_clken_RCC_ETHMAC
rcc_periph_clken_RCC_ETHMACRX
rcc_periph_clken_RCC_ETHMACTX
rcc_periph_clken_RCC_FLTF
rcc_periph_clken_RCC_FSMC
rcc_periph_clken_RCC_GPIOA
rcc_periph_clken_RCC_GPIOB
rcc_periph_clken_RCC_GPIOC
rcc_periph_clken_RCC_GPIOD
rcc_periph_clken_RCC_GPIOE
rcc_periph_clken_RCC_GPIOF
rcc_periph_clken_RCC_GPIOG
rcc_periph_clken_RCC_I2C1
rcc_periph_clken_RCC_I2C2
rcc_periph_clken_RCC_OTGFS
rcc_periph_clken_RCC_PWR
rcc_periph_clken_RCC_SDIO
rcc_periph_clken_RCC_SPI1
rcc_periph_clken_RCC_SPI2
rcc_periph_clken_RCC_SPI3
rcc_periph_clken_RCC_SRAM
rcc_periph_clken_RCC_TIM1
rcc_periph_clken_RCC_TIM2
rcc_periph_clken_RCC_TIM3
rcc_periph_clken_RCC_TIM4
rcc_periph_clken_RCC_TIM5
rcc_periph_clken_RCC_TIM6
rcc_periph_clken_RCC_TIM7
rcc_periph_clken_RCC_TIM8
rcc_periph_clken_RCC_TIM9
rcc_periph_clken_RCC_TIM10
rcc_periph_clken_RCC_TIM11
rcc_periph_clken_RCC_TIM12
rcc_periph_clken_RCC_TIM13
rcc_periph_clken_RCC_TIM14
rcc_periph_clken_RCC_TIM15
rcc_periph_clken_RCC_TIM16
rcc_periph_clken_RCC_TIM17
rcc_periph_clken_RCC_UART4
rcc_periph_clken_RCC_UART5
rcc_periph_clken_RCC_USART1
rcc_periph_clken_RCC_USART2
rcc_periph_clken_RCC_USART3
rcc_periph_clken_RCC_USB
rcc_periph_clken_RCC_WWDG
rcc_periph_rst_RST_ADC1
rcc_periph_rst_RST_ADC2
rcc_periph_rst_RST_ADC3
rcc_periph_rst_RST_AFIO
rcc_periph_rst_RST_BKP
rcc_periph_rst_RST_CAN
rcc_periph_rst_RST_CAN1
rcc_periph_rst_RST_CAN2
rcc_periph_rst_RST_CEC
rcc_periph_rst_RST_DAC
rcc_periph_rst_RST_ETHMAC
rcc_periph_rst_RST_GPIOA
rcc_periph_rst_RST_GPIOB
rcc_periph_rst_RST_GPIOC
rcc_periph_rst_RST_GPIOD
rcc_periph_rst_RST_GPIOE
rcc_periph_rst_RST_GPIOF
rcc_periph_rst_RST_GPIOG
rcc_periph_rst_RST_I2C1
rcc_periph_rst_RST_I2C2
rcc_periph_rst_RST_OTGFS
rcc_periph_rst_RST_PWR
rcc_periph_rst_RST_SPI1
rcc_periph_rst_RST_SPI2
rcc_periph_rst_RST_SPI3
rcc_periph_rst_RST_TIM1
rcc_periph_rst_RST_TIM2
rcc_periph_rst_RST_TIM3
rcc_periph_rst_RST_TIM4
rcc_periph_rst_RST_TIM5
rcc_periph_rst_RST_TIM6
rcc_periph_rst_RST_TIM7
rcc_periph_rst_RST_TIM8
rcc_periph_rst_RST_TIM9
rcc_periph_rst_RST_TIM10
rcc_periph_rst_RST_TIM11
rcc_periph_rst_RST_TIM12
rcc_periph_rst_RST_TIM13
rcc_periph_rst_RST_TIM14
rcc_periph_rst_RST_TIM15
rcc_periph_rst_RST_TIM16
rcc_periph_rst_RST_TIM17
rcc_periph_rst_RST_UART4
rcc_periph_rst_RST_UART5
rcc_periph_rst_RST_USART1
rcc_periph_rst_RST_USART2
rcc_periph_rst_RST_USART3
rcc_periph_rst_RST_USB