Crate k32l3a60_cm0plus

Expand description

Peripheral access API for K32L3A60_CM0PLUS microcontrollers (generated using svd2rust v0.29.0 ( ))

You can find an overview of the generated API here.

API features to be included in the next svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open.

Re-exports§

pub use self::sema420 as sema421;
pub use self::llwu0 as llwu1;
pub use self::wdog0 as wdog1;
pub use self::lpit0 as lpit1;
pub use self::lptmr0 as lptmr1;
pub use self::lptmr0 as lptmr2;
pub use self::tpm0 as tpm1;
pub use self::tpm0 as tpm2;
pub use self::tpm0 as tpm3;
pub use self::lpi2c0 as lpi2c1;
pub use self::lpi2c0 as lpi2c2;
pub use self::lpi2c0 as lpi2c3;
pub use self::lpspi0 as lpspi1;
pub use self::lpspi0 as lpspi2;
pub use self::lpspi0 as lpspi3;
pub use self::lpuart0 as lpuart1;
pub use self::lpuart0 as lpuart2;
pub use self::lpuart0 as lpuart3;
pub use self::lpcmp0 as lpcmp1;
pub use self::gpioa as gpioe;
pub use self::gpioa as gpiob;
pub use self::gpioa as gpioc;
pub use self::gpioa as gpiod;

Modules§

cau3: CAU3
core_debug: Core Debug Registers
crc: CRC
dma1: DMA
dmamux1: DMA_CH_MUX
emvsim0: EMVSIM
ewm: EWM
fb: FB
fgpioe: GPIO
flexio0: FLEXIO
ftfe: Flash
generic: Common register and bit access and modify traits
gpioa: GPIO
i2s0: I2S
intmux1: INTMUX
llwu0: LLWU
lpadc0: LPADC
lpcmp0: LPCMP
lpdac0: LPDAC
lpi2c0: LPI2C
lpit0: LPIT
lpspi0: LPSPI
lptmr0: LPTMR
lpuart0: LPUART
mcm1: MCM
mmdvsq1: MMDVSQ
mscm: MSCM
mtb: MTB
mtbdwt: DWT
mub: MUB
pcc0: PCC
pcc1: PCC
porta: PORT
portb: PORT
portc: PORT
portd: PORT
porte: PORT
rom: ROM
rtc: RTC
scg: SCG
sema420: sema42_ips
sim: SIM
smc0: crr_cmc0
smc1: crr_cmc1
spm: SPM
sys_tick: System timer
system_control: System Control Block
tpm0: TPM
trgmux0: TRGMUX
trgmux1: TRGMUX
trng: TRNG
tstmrb: TSTMRB
usb0: USB
usbvreg: USBVREG
usdhc0: uSDHC
vref: VREF
wdog0: WDOG
xrdc: XRDC

Structs§

CAU3: CAU3
CBP: Cache and branch predictor maintenance operations
CORE_DEBUG: Core Debug Registers
CPUID: CPUID
CRC: CRC
CorePeripherals: Core peripherals
DCB: Debug Control Block
DMA1: DMA
DMAMUX1: DMA_CH_MUX
DWT: Data Watchpoint and Trace unit
EMVSIM0: EMVSIM
EWM: EWM
FB: FB
FGPIOE: GPIO
FLEXIO0: FLEXIO
FPB: Flash Patch and Breakpoint unit
FTFE: Flash
GPIOA: GPIO
GPIOB: GPIO
GPIOC: GPIO
GPIOD: GPIO
GPIOE: GPIO
I2S0: I2S
INTMUX1: INTMUX
ITM: Instrumentation Trace Macrocell
LLWU0: LLWU
LLWU1: LLWU
LPADC0: LPADC
LPCMP0: LPCMP
LPCMP1: LPCMP
LPDAC0: LPDAC
LPI2C0: LPI2C
LPI2C1: LPI2C
LPI2C2: LPI2C
LPI2C3: LPI2C
LPIT0: LPIT
LPIT1: LPIT
LPSPI0: LPSPI
LPSPI1: LPSPI
LPSPI2: LPSPI
LPSPI3: LPSPI
LPTMR0: LPTMR
LPTMR1: LPTMR
LPTMR2: LPTMR
LPUART0: LPUART
LPUART1: LPUART
LPUART2: LPUART
LPUART3: LPUART
MCM1: MCM
MMDVSQ1: MMDVSQ
MPU: Memory Protection Unit
MSCM: MSCM
MTB: MTB
MTBDWT: DWT
MUB: MUB
NVIC: Nested Vector Interrupt Controller
PCC0: PCC
PCC1: PCC
PORTA: PORT
PORTB: PORT
PORTC: PORT
PORTD: PORT
PORTE: PORT
Peripherals: All the peripherals.
ROM: ROM
RTC: RTC
SCB: System Control Block
SCG: SCG
SEMA420: sema42_ips
SEMA421: sema42_ips
SIM: SIM
SMC0: crr_cmc0
SMC1: crr_cmc1
SPM: SPM
SYST: SysTick: System Timer
SYSTEM_CONTROL: System Control Block
SYS_TICK: System timer
TPIU: Trace Port Interface Unit
TPM0: TPM
TPM1: TPM
TPM2: TPM
TPM3: TPM
TRGMUX0: TRGMUX
TRGMUX1: TRGMUX
TRNG: TRNG
TSTMRB: TSTMRB
USB0: USB
USBVREG: USBVREG
USDHC0: uSDHC
VREF: VREF
WDOG0: WDOG
WDOG1: WDOG
XRDC: XRDC

Enums§

Interrupt: Enumeration of all the interrupts.

Constants§