[−][src]Module k210_pac::kpu
Neural Network Accelerator
Modules
| eight_bit_mode | Eight bit mode |
| fifo_ctrl | FIFO control |
| fifo_data_out | FIFO data output |
| fifo_threshold | FIFO threshold |
| interrupt_clear | Interrupt clear: write 1 to a bit to clear interrupt |
| interrupt_mask | Interrupt mask: 0 enables the interrupt, 1 masks the interrupt |
| interrupt_raw | Interrupt raw |
| interrupt_status | Interrupt status |
| layer_argument_fifo | Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register |
Structs
| RegisterBlock | Register block |
Type Definitions
| EIGHT_BIT_MODE | Eight bit mode |
| FIFO_CTRL | FIFO control |
| FIFO_DATA_OUT | FIFO data output |
| FIFO_THRESHOLD | FIFO threshold |
| INTERRUPT_CLEAR | Interrupt clear: write 1 to a bit to clear interrupt |
| INTERRUPT_MASK | Interrupt mask: 0 enables the interrupt, 1 masks the interrupt |
| INTERRUPT_RAW | Interrupt raw |
| INTERRUPT_STATUS | Interrupt status |
| LAYER_ARGUMENT_FIFO | Layer arguments FIFO: each layer is defined by writing 12 successive argument values to this register |