[−][src]Module k210_pac::uart1
Universal Asynchronous Receiver-Transmitter 1
Modules
cpr | Component Parameter Register |
ctr | Component Type Register |
de_en | DE Enable Register |
det | DE Assertion Time Register |
dlf | Divisor Latch (Fractional) Register |
dlh_ier | Divisor Latch (High) / Interrupt Enable Register |
dmasa | DMA Software Acknowledge Register |
far | FIFO Access Register |
fcr_iir | FIFO Control Register / Interrupt Identification Register |
htx | Halt TX Regster |
lcr | Line Control Register |
lcr_ext | Line Control Register (Extended) |
lpdlh | Low Power Divisor Latch (High) Register |
lpdll | Low Power Divisor Latch (Low) Register |
lsr | Line Status Register |
mcr | Modem Control Register |
msr | Modem Status Register |
rar | Receive-Mode Address Register |
rbr_dll_thr | Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W) |
re_en | RE Enable Register |
rfl | Receive FIFO Level |
rfw | Receive FIFO Write Register |
sbcr | Shadow Break Control Register |
scr | Scratchpad Register |
sdmam | Shadow DMA Mode |
sfe | Shadow FIFO Enable |
srbr_sthr | Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W) |
srr | Software Reset Register |
srt | Shadow RCVR Trigger Register |
srts | Shadow Request to Send Register |
stet | Shadow TX Empty Trigger Register |
tar | Transmit-Mode Address Register |
tat | Turn-Around Time Register |
tcr | Transfer Control Register |
tfl | Transmit FIFO Level |
tfr | Transmit FIFO Read Register |
ucv | UART Component Version |
usr | UART Status Register |
Structs
RegisterBlock | Register block |
Type Definitions
CPR | Component Parameter Register |
CTR | Component Type Register |
DET | DE Assertion Time Register |
DE_EN | DE Enable Register |
DLF | Divisor Latch (Fractional) Register |
DLH_IER | Divisor Latch (High) / Interrupt Enable Register |
DMASA | DMA Software Acknowledge Register |
FAR | FIFO Access Register |
FCR_IIR | FIFO Control Register / Interrupt Identification Register |
HTX | Halt TX Regster |
LCR | Line Control Register |
LCR_EXT | Line Control Register (Extended) |
LPDLH | Low Power Divisor Latch (High) Register |
LPDLL | Low Power Divisor Latch (Low) Register |
LSR | Line Status Register |
MCR | Modem Control Register |
MSR | Modem Status Register |
RAR | Receive-Mode Address Register |
RBR_DLL_THR | Receive Buffer Register / Divisor Latch (Low) / Transmit Holding Register (depending on context and R/W) |
RE_EN | RE Enable Register |
RFL | Receive FIFO Level |
RFW | Receive FIFO Write Register |
SBCR | Shadow Break Control Register |
SCR | Scratchpad Register |
SDMAM | Shadow DMA Mode |
SFE | Shadow FIFO Enable |
SRBR_STHR | Shadow Receive Buffer Register / Shadow Transmit Holding Register (depending on R/W) |
SRR | Software Reset Register |
SRT | Shadow RCVR Trigger Register |
SRTS | Shadow Request to Send Register |
STET | Shadow TX Empty Trigger Register |
TAR | Transmit-Mode Address Register |
TAT | Turn-Around Time Register |
TCR | Transfer Control Register |
TFL | Transmit FIFO Level |
TFR | Transmit FIFO Read Register |
UCV | UART Component Version |
USR | UART Status Register |