[−][src]Struct imxrt1062_system_control::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub actlr: ACTLR,
    pub cpuid: CPUID,
    pub icsr: ICSR,
    pub vtor: VTOR,
    pub aircr: AIRCR,
    pub scr: SCR,
    pub ccr: CCR,
    pub shpr1: SHPR1,
    pub shpr2: SHPR2,
    pub shpr3: SHPR3,
    pub shcsr: SHCSR,
    pub cfsr: CFSR,
    pub hfsr: HFSR,
    pub dfsr: DFSR,
    pub mmfar: MMFAR,
    pub bfar: BFAR,
    pub id_pfr0: ID_PFR0,
    pub id_pfr1: ID_PFR1,
    pub id_dfr0: ID_DFR0,
    pub id_afr0: ID_AFR0,
    pub id_mmfr0: ID_MMFR0,
    pub id_mmfr1: ID_MMFR1,
    pub id_mmfr2: ID_MMFR2,
    pub id_mmfr3: ID_MMFR3,
    pub id_isar0: ID_ISAR0,
    pub id_isar1: ID_ISAR1,
    pub id_isar2: ID_ISAR2,
    pub id_isar3: ID_ISAR3,
    pub id_isar4: ID_ISAR4,
    pub clidr: CLIDR,
    pub ctr: CTR,
    pub ccsidr: CCSIDR,
    pub csselr: CSSELR,
    pub cpacr: CPACR,
    pub stir: STIR,
    pub iciallu: ICIALLU,
    pub icimvau: ICIMVAU,
    pub dcimvac: DCIMVAC,
    pub dcisw: DCISW,
    pub dccmvau: DCCMVAU,
    pub dccmvac: DCCMVAC,
    pub dccsw: DCCSW,
    pub dccimvac: DCCIMVAC,
    pub dccisw: DCCISW,
    pub cm7_itcmcr: CM7_ITCMCR,
    pub cm7_dtcmcr: CM7_DTCMCR,
    pub cm7_ahbpcr: CM7_AHBPCR,
    pub cm7_cacr: CM7_CACR,
    pub cm7_ahbscr: CM7_AHBSCR,
    pub cm7_abfsr: CM7_ABFSR,
    // some fields omitted
}

Register block

Fields

actlr: ACTLR

0x08 - Auxiliary Control Register,

cpuid: CPUID

0xd00 - CPUID Base Register

icsr: ICSR

0xd04 - Interrupt Control and State Register

vtor: VTOR

0xd08 - Vector Table Offset Register

aircr: AIRCR

0xd0c - Application Interrupt and Reset Control Register

scr: SCR

0xd10 - System Control Register

ccr: CCR

0xd14 - Configuration and Control Register

shpr1: SHPR1

0xd18 - System Handler Priority Register 1

shpr2: SHPR2

0xd1c - System Handler Priority Register 2

shpr3: SHPR3

0xd20 - System Handler Priority Register 3

shcsr: SHCSR

0xd24 - System Handler Control and State Register

cfsr: CFSR

0xd28 - Configurable Fault Status Register

hfsr: HFSR

0xd2c - HardFault Status register

dfsr: DFSR

0xd30 - Debug Fault Status Register

mmfar: MMFAR

0xd34 - MemManage Fault Address Register

bfar: BFAR

0xd38 - BusFault Address Register

id_pfr0: ID_PFR0

0xd40 - Processor Feature Register 0

id_pfr1: ID_PFR1

0xd44 - Processor Feature Register 1

id_dfr0: ID_DFR0

0xd48 - Debug Feature Register

id_afr0: ID_AFR0

0xd4c - Auxiliary Feature Register

id_mmfr0: ID_MMFR0

0xd50 - Memory Model Feature Register 0

id_mmfr1: ID_MMFR1

0xd54 - Memory Model Feature Register 1

id_mmfr2: ID_MMFR2

0xd58 - Memory Model Feature Register 2

id_mmfr3: ID_MMFR3

0xd5c - Memory Model Feature Register 3

id_isar0: ID_ISAR0

0xd60 - Instruction Set Attributes Register 0

id_isar1: ID_ISAR1

0xd64 - Instruction Set Attributes Register 1

id_isar2: ID_ISAR2

0xd68 - Instruction Set Attributes Register 2

id_isar3: ID_ISAR3

0xd6c - Instruction Set Attributes Register 3

id_isar4: ID_ISAR4

0xd70 - Instruction Set Attributes Register 4

clidr: CLIDR

0xd78 - Cache Level ID register

ctr: CTR

0xd7c - Cache Type register

ccsidr: CCSIDR

0xd80 - Cache Size ID Register

csselr: CSSELR

0xd84 - Cache Size Selection Register

cpacr: CPACR

0xd88 - Coprocessor Access Control Register

stir: STIR

0xf00 - Instruction cache invalidate all to Point of Unification (PoU)

iciallu: ICIALLU

0xf50 - Instruction cache invalidate all to Point of Unification (PoU)

icimvau: ICIMVAU

0xf58 - Instruction cache invalidate by address to PoU

dcimvac: DCIMVAC

0xf5c - Data cache invalidate by address to Point of Coherency (PoC)

dcisw: DCISW

0xf60 - Data cache invalidate by set/way

dccmvau: DCCMVAU

0xf64 - Data cache by address to PoU

dccmvac: DCCMVAC

0xf68 - Data cache clean by address to PoC

dccsw: DCCSW

0xf6c - Data cache clean by set/way

dccimvac: DCCIMVAC

0xf70 - Data cache clean and invalidate by address to PoC

dccisw: DCCISW

0xf74 - Data cache clean and invalidate by set/way

cm7_itcmcr: CM7_ITCMCR

0xf90 - Instruction Tightly-Coupled Memory Control Register

cm7_dtcmcr: CM7_DTCMCR

0xf94 - Data Tightly-Coupled Memory Control Register

cm7_ahbpcr: CM7_AHBPCR

0xf98 - AHBP Control Register

cm7_cacr: CM7_CACR

0xf9c - L1 Cache Control Register

cm7_ahbscr: CM7_AHBSCR

0xfa0 - AHB Slave Control Register

cm7_abfsr: CM7_ABFSR

0xfa8 - Auxiliary Bus Fault Status Register

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