[][src]Struct imxrt1062_snvs::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

Writes raw bits to the register

impl W<u32, Reg<u32, _HPLR>>[src]

pub fn zmk_wsl(&mut self) -> ZMK_WSL_W[src]

Bit 0 - Zeroizable Master Key Write Soft Lock When set, prevents any writes (software and hardware) to the ZMK registers and the ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR

pub fn zmk_rsl(&mut self) -> ZMK_RSL_W[src]

Bit 1 - Zeroizable Master Key Read Soft Lock When set, prevents any software reads to the ZMK Registers and ZMK_ECC_VALUE field of the LPMKCR

pub fn srtc_sl(&mut self) -> SRTC_SL_W[src]

Bit 2 - Secure Real Time Counter Soft Lock When set, prevents any writes to the SRTC Registers, SRTC_ENV, and SRTC_INV_EN bits

pub fn lpcalb_sl(&mut self) -> LPCALB_SL_W[src]

Bit 3 - LP Calibration Soft Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)

pub fn mc_sl(&mut self) -> MC_SL_W[src]

Bit 4 - Monotonic Counter Soft Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit

pub fn gpr_sl(&mut self) -> GPR_SL_W[src]

Bit 5 - General Purpose Register Soft Lock When set, prevents any writes to the GPR

pub fn lpsvcr_sl(&mut self) -> LPSVCR_SL_W[src]

Bit 6 - LP Security Violation Control Register Soft Lock When set, prevents any writes to the LPSVCR

pub fn lptdcr_sl(&mut self) -> LPTDCR_SL_W[src]

Bit 8 - LP Tamper Detectors Configuration Register Soft Lock When set, prevents any writes to the LPTDCR

pub fn mks_sl(&mut self) -> MKS_SL_W[src]

Bit 9 - Master Key Select Soft Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LPMKCR

pub fn hpsvcr_l(&mut self) -> HPSVCR_L_W[src]

Bit 16 - HP Security Violation Control Register Lock When set, prevents any writes to the HPSVCR

pub fn hpsicr_l(&mut self) -> HPSICR_L_W[src]

Bit 17 - HP Security Interrupt Control Register Lock When set, prevents any writes to the HPSICR

pub fn hac_l(&mut self) -> HAC_L_W[src]

Bit 18 - High Assurance Counter Lock When set, prevents any writes to HPHACIVR, HPHACR, and HAC_EN bit of HPCOMR

impl W<u32, Reg<u32, _HPCOMR>>[src]

pub fn ssm_st(&mut self) -> SSM_ST_W[src]

Bit 0 - SSM State Transition Transition state of the system security monitor

pub fn ssm_st_dis(&mut self) -> SSM_ST_DIS_W[src]

Bit 1 - SSM Secure to Trusted State Transition Disable When set, disables the SSM transition from secure to trusted state

pub fn ssm_sfns_dis(&mut self) -> SSM_SFNS_DIS_W[src]

Bit 2 - SSM Soft Fail to Non-Secure State Transition Disable When set, it disables the SSM transition from soft fail to non-secure state

pub fn lp_swr(&mut self) -> LP_SWR_W[src]

Bit 4 - LP Software Reset When set to 1, most registers in the SNVS_LP section are reset, but the following registers are not reset by an LP software reset: Secure Real Time Counter Time Alarm Register This bit cannot be set when the LP_SWR_DIS bit is set

pub fn lp_swr_dis(&mut self) -> LP_SWR_DIS_W[src]

Bit 5 - LP Software Reset Disable When set, disables the LP software reset

pub fn sw_sv(&mut self) -> SW_SV_W[src]

Bit 8 - Software Security Violation When set, the system security monitor treats this bit as a non-fatal security violation

pub fn sw_fsv(&mut self) -> SW_FSV_W[src]

Bit 9 - Software Fatal Security Violation When set, the system security monitor treats this bit as a fatal security violation

pub fn sw_lpsv(&mut self) -> SW_LPSV_W[src]

Bit 10 - LP Software Security Violation When set, SNVS_LP treats this bit as a security violation

pub fn prog_zmk(&mut self) -> PROG_ZMK_W[src]

Bit 12 - Program Zeroizable Master Key This bit activates ZMK hardware programming mechanism

pub fn mks_en(&mut self) -> MKS_EN_W[src]

Bit 13 - Master Key Select Enable When not set, the one time programmable (OTP) master key is selected by default

pub fn hac_en(&mut self) -> HAC_EN_W[src]

Bit 16 - High Assurance Counter Enable This bit controls the SSM transition from the soft fail to the hard fail state

pub fn hac_load(&mut self) -> HAC_LOAD_W[src]

Bit 17 - High Assurance Counter Load When set, it loads the High Assurance Counter Register with the value of the High Assurance Counter Load Register

pub fn hac_clear(&mut self) -> HAC_CLEAR_W[src]

Bit 18 - High Assurance Counter Clear When set, it clears the High Assurance Counter Register

pub fn hac_stop(&mut self) -> HAC_STOP_W[src]

Bit 19 - High Assurance Counter Stop This bit can be set only when SSM is in soft fail state

pub fn npswa_en(&mut self) -> NPSWA_EN_W[src]

Bit 31 - Non-Privileged Software Access Enable When set, allows non-privileged software to access all SNVS registers, including those that are privileged software read/write access only

impl W<u32, Reg<u32, _HPCR>>[src]

pub fn rtc_en(&mut self) -> RTC_EN_W[src]

Bit 0 - HP Real Time Counter Enable

pub fn hpta_en(&mut self) -> HPTA_EN_W[src]

Bit 1 - HP Time Alarm Enable When set, the time alarm interrupt is generated if the value in the HP Time Alarm Registers is equal to the value of the HP Real Time Counter

pub fn dis_pi(&mut self) -> DIS_PI_W[src]

Bit 2 - Disable periodic interrupt in the functional interrupt

pub fn pi_en(&mut self) -> PI_EN_W[src]

Bit 3 - HP Periodic Interrupt Enable The periodic interrupt can be generated only if the HP Real Time Counter is enabled

pub fn pi_freq(&mut self) -> PI_FREQ_W[src]

Bits 4:7 - Periodic Interrupt Frequency Defines frequency of the periodic interrupt

pub fn hpcalb_en(&mut self) -> HPCALB_EN_W[src]

Bit 8 - HP Real Time Counter Calibration Enabled Indicates that the time calibration mechanism is enabled.

pub fn hpcalb_val(&mut self) -> HPCALB_VAL_W[src]

Bits 10:14 - HP Calibration Value Defines signed calibration value for the HP Real Time Counter

pub fn hp_ts(&mut self) -> HP_TS_W[src]

Bit 16 - HP Time Synchronize

pub fn btn_config(&mut self) -> BTN_CONFIG_W[src]

Bits 24:26 - Button Configuration

pub fn btn_mask(&mut self) -> BTN_MASK_W[src]

Bit 27 - Button interrupt mask

impl W<u32, Reg<u32, _HPSICR>>[src]

pub fn sv0_en(&mut self) -> SV0_EN_W[src]

Bit 0 - Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation

pub fn sv1_en(&mut self) -> SV1_EN_W[src]

Bit 1 - Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation

pub fn sv2_en(&mut self) -> SV2_EN_W[src]

Bit 2 - Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation

pub fn sv3_en(&mut self) -> SV3_EN_W[src]

Bit 3 - Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation

pub fn sv4_en(&mut self) -> SV4_EN_W[src]

Bit 4 - Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation

pub fn sv5_en(&mut self) -> SV5_EN_W[src]

Bit 5 - Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation

pub fn lpsvi_en(&mut self) -> LPSVI_EN_W[src]

Bit 31 - LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section

impl W<u32, Reg<u32, _HPSVCR>>[src]

pub fn sv0_cfg(&mut self) -> SV0_CFG_W[src]

Bit 0 - Security Violation 0 Security Violation Configuration This field configures the Security Violation 0 Security Violation Input

pub fn sv1_cfg(&mut self) -> SV1_CFG_W[src]

Bit 1 - Security Violation 1 Security Violation Configuration This field configures the Security Violation 1 Security Violation Input

pub fn sv2_cfg(&mut self) -> SV2_CFG_W[src]

Bit 2 - Security Violation 2 Security Violation Configuration This field configures the Security Violation 2 Security Violation Input

pub fn sv3_cfg(&mut self) -> SV3_CFG_W[src]

Bit 3 - Security Violation 3 Security Violation Configuration This field configures the Security Violation 3 Security Violation Input

pub fn sv4_cfg(&mut self) -> SV4_CFG_W[src]

Bit 4 - Security Violation 4 Security Violation Configuration This field configures the Security Violation 4 Security Violation Input

pub fn sv5_cfg(&mut self) -> SV5_CFG_W[src]

Bits 5:6 - Security Violation 5 Security Violation Configuration This field configures the Security Violation 5 Security Violation Input

pub fn lpsv_cfg(&mut self) -> LPSV_CFG_W[src]

Bits 30:31 - LP Security Violation Configuration This field configures the LP security violation source.

impl W<u32, Reg<u32, _HPSR>>[src]

pub fn hpta(&mut self) -> HPTA_W[src]

Bit 0 - HP Time Alarm Indicates that the HP Time Alarm has occurred since this bit was last cleared.

pub fn pi(&mut self) -> PI_W[src]

Bit 1 - Periodic Interrupt Indicates that periodic interrupt has occurred since this bit was last cleared.

pub fn bi(&mut self) -> BI_W[src]

Bit 7 - Button Interrupt Signal ipi_snvs_btn_int_b was asserted.

impl W<u32, Reg<u32, _HPSVSR>>[src]

pub fn sv0(&mut self) -> SV0_W[src]

Bit 0 - Security Violation 0 security violation was detected.

pub fn sv1(&mut self) -> SV1_W[src]

Bit 1 - Security Violation 1 security violation was detected.

pub fn sv2(&mut self) -> SV2_W[src]

Bit 2 - Security Violation 2 security violation was detected.

pub fn sv3(&mut self) -> SV3_W[src]

Bit 3 - Security Violation 3 security violation was detected.

pub fn sv4(&mut self) -> SV4_W[src]

Bit 4 - Security Violation 4 security violation was detected.

pub fn sv5(&mut self) -> SV5_W[src]

Bit 5 - Security Violation 5 security violation was detected.

pub fn zmk_ecc_fail(&mut self) -> ZMK_ECC_FAIL_W[src]

Bit 27 - Zeroizable Master Key Error Correcting Code Check Failure When set, this bit triggers a bad key violation to the SSM and a security violation to the SNVS_LP section, which clears security sensitive data

impl W<u32, Reg<u32, _HPHACIVR>>[src]

pub fn hac_counter_iv(&mut self) -> HAC_COUNTER_IV_W[src]

Bits 0:31 - High Assurance Counter Initial Value This register is used to set the starting count value to the high assurance counter

impl W<u32, Reg<u32, _HPRTCMR>>[src]

pub fn rtc(&mut self) -> RTC_W[src]

Bits 0:14 - HP Real Time Counter The most-significant 15 bits of the RTC

impl W<u32, Reg<u32, _HPRTCLR>>[src]

pub fn rtc(&mut self) -> RTC_W[src]

Bits 0:31 - HP Real Time Counter least-significant 32 bits

impl W<u32, Reg<u32, _HPTAMR>>[src]

pub fn hpta_ms(&mut self) -> HPTA_MS_W[src]

Bits 0:14 - HP Time Alarm, most-significant 15 bits

impl W<u32, Reg<u32, _HPTALR>>[src]

pub fn hpta_ls(&mut self) -> HPTA_LS_W[src]

Bits 0:31 - HP Time Alarm, 32 least-significant bits

impl W<u32, Reg<u32, _LPLR>>[src]

pub fn zmk_whl(&mut self) -> ZMK_WHL_W[src]

Bit 0 - Zeroizable Master Key Write Hard Lock When set, prevents any writes (software and hardware) to the ZMK registers and ZMK_HWP, ZMK_VAL, and ZMK_ECC_EN fields of the LPMKCR

pub fn zmk_rhl(&mut self) -> ZMK_RHL_W[src]

Bit 1 - Zeroizable Master Key Read Hard Lock When set, prevents any software reads to the ZMK registers and ZMK_ECC_VALUE field of the LPMKCR

pub fn srtc_hl(&mut self) -> SRTC_HL_W[src]

Bit 2 - Secure Real Time Counter Hard Lock When set, prevents any writes to the SRTC registers, SRTC_ENV, and SRTC_INV_EN bits

pub fn lpcalb_hl(&mut self) -> LPCALB_HL_W[src]

Bit 3 - LP Calibration Hard Lock When set, prevents any writes to the LP Calibration Value (LPCALB_VAL) and LP Calibration Enable (LPCALB_EN)

pub fn mc_hl(&mut self) -> MC_HL_W[src]

Bit 4 - Monotonic Counter Hard Lock When set, prevents any writes (increments) to the MC Registers and MC_ENV bit

pub fn gpr_hl(&mut self) -> GPR_HL_W[src]

Bit 5 - General Purpose Register Hard Lock When set, prevents any writes to the GPR

pub fn lpsvcr_hl(&mut self) -> LPSVCR_HL_W[src]

Bit 6 - LP Security Violation Control Register Hard Lock When set, prevents any writes to the LPSVCR

pub fn lptdcr_hl(&mut self) -> LPTDCR_HL_W[src]

Bit 8 - LP Tamper Detectors Configuration Register Hard Lock When set, prevents any writes to the LPTDCR

pub fn mks_hl(&mut self) -> MKS_HL_W[src]

Bit 9 - Master Key Select Hard Lock When set, prevents any writes to the MASTER_KEY_SEL field of the LP Master Key Control Register

impl W<u32, Reg<u32, _LPCR>>[src]

pub fn srtc_env(&mut self) -> SRTC_ENV_W[src]

Bit 0 - Secure Real Time Counter Enabled and Valid When set, the SRTC becomes operational

pub fn lpta_en(&mut self) -> LPTA_EN_W[src]

Bit 1 - LP Time Alarm Enable When set, the SNVS functional interrupt is asserted if the LP Time Alarm Register is equal to the 32 MSBs of the secure real time counter

pub fn mc_env(&mut self) -> MC_ENV_W[src]

Bit 2 - Monotonic Counter Enabled and Valid When set, the MC can be incremented (by write transaction to the LPSMCMR or LPSMCLR)

pub fn lpwui_en(&mut self) -> LPWUI_EN_W[src]

Bit 3 - LP Wake-Up Interrupt Enable This interrupt line should be connected to the external pin and is intended to inform the external chip about an SNVS_LP event (tamper event, MC rollover, SRTC rollover, or time alarm )

pub fn srtc_inv_en(&mut self) -> SRTC_INV_EN_W[src]

Bit 4 - If this bit is 1, in the case of a security violation the SRTC stops counting and the SRTC is invalidated (SRTC_ENV bit is cleared)

pub fn dp_en(&mut self) -> DP_EN_W[src]

Bit 5 - Dumb PMIC Enabled When set, software can control the system power

pub fn top(&mut self) -> TOP_W[src]

Bit 6 - Turn off System Power Asserting this bit causes a signal to be sent to the Power Management IC to turn off the system power

pub fn pwr_glitch_en(&mut self) -> PWR_GLITCH_EN_W[src]

Bit 7 - Power Glitch Enable By default the detection of a power glitch does not cause the pmic_en_b signal to be asserted

pub fn lpcalb_en(&mut self) -> LPCALB_EN_W[src]

Bit 8 - LP Calibration Enable When set, enables the SRTC calibration mechanism

pub fn lpcalb_val(&mut self) -> LPCALB_VAL_W[src]

Bits 10:14 - LP Calibration Value Defines signed calibration value for SRTC

pub fn btn_press_time(&mut self) -> BTN_PRESS_TIME_W[src]

Bits 16:17 - This field configures the button press time out values for the PMIC Logic

pub fn debounce(&mut self) -> DEBOUNCE_W[src]

Bits 18:19 - This field configures the amount of debounce time for the BTN input signal

pub fn on_time(&mut self) -> ON_TIME_W[src]

Bits 20:21 - The ON_TIME field is used to configure the period of time after BTN is asserted before pmic_en_b is asserted to turn on the SoC power

pub fn pk_en(&mut self) -> PK_EN_W[src]

Bit 22 - PMIC On Request Enable The value written to PK_EN will be asserted on output signal snvs_lp_pk_en

pub fn pk_override(&mut self) -> PK_OVERRIDE_W[src]

Bit 23 - PMIC On Request Override The value written to PK_OVERRIDE will be asserted on output signal snvs_lp_pk_override

pub fn gpr_z_dis(&mut self) -> GPR_Z_DIS_W[src]

Bit 24 - General Purpose Registers Zeroization Disable

impl W<u32, Reg<u32, _LPMKCR>>[src]

pub fn master_key_sel(&mut self) -> MASTER_KEY_SEL_W[src]

Bits 0:1 - Master Key Select These bits select the SNVS Master Key output when Master Key Select bits are enabled by MKS_EN bit in the HPCOMR

pub fn zmk_hwp(&mut self) -> ZMK_HWP_W[src]

Bit 2 - Zeroizable Master Key hardware Programming mode When set, only the hardware key programming mechanism can set the ZMK and software cannot read it

pub fn zmk_val(&mut self) -> ZMK_VAL_W[src]

Bit 3 - Zeroizable Master Key Valid When set, the ZMK value can be selected by the master key control block for use by cryptographic modules

pub fn zmk_ecc_en(&mut self) -> ZMK_ECC_EN_W[src]

Bit 4 - Zeroizable Master Key Error Correcting Code Check Enable Writing one to this field automatically calculates and sets the ZMK ECC value in the ZMK_ECC_VALUE field of this register

impl W<u32, Reg<u32, _LPSVCR>>[src]

pub fn sv0_en(&mut self) -> SV0_EN_W[src]

Bit 0 - Security Violation 0 Enable This bit enables Security Violation 0 Input

pub fn sv1_en(&mut self) -> SV1_EN_W[src]

Bit 1 - Security Violation 1 Enable This bit enables Security Violation 1 Input

pub fn sv2_en(&mut self) -> SV2_EN_W[src]

Bit 2 - Security Violation 2 Enable This bit enables Security Violation 2 Input

pub fn sv3_en(&mut self) -> SV3_EN_W[src]

Bit 3 - Security Violation 3 Enable This bit enables Security Violation 3 Input

pub fn sv4_en(&mut self) -> SV4_EN_W[src]

Bit 4 - Security Violation 4 Enable This bit enables Security Violation 4 Input

pub fn sv5_en(&mut self) -> SV5_EN_W[src]

Bit 5 - Security Violation 5 Enable This bit enables Security Violation 5 Input

impl W<u32, Reg<u32, _LPTDCR>>[src]

pub fn srtcr_en(&mut self) -> SRTCR_EN_W[src]

Bit 1 - SRTC Rollover Enable When set, an SRTC rollover event generates an LP security violation.

pub fn mcr_en(&mut self) -> MCR_EN_W[src]

Bit 2 - MC Rollover Enable When set, an MC Rollover event generates an LP security violation.

pub fn et1_en(&mut self) -> ET1_EN_W[src]

Bit 9 - External Tampering 1 Enable When set, external tampering 1 detection generates an LP security violation

pub fn et1p(&mut self) -> ET1P_W[src]

Bit 11 - External Tampering 1 Polarity This bit is used to determine the polarity of external tamper 1.

pub fn pfd_observ(&mut self) -> PFD_OBSERV_W[src]

Bit 14 - System Power Fail Detector (PFD) Observability Flop The asynchronous reset input of this flop is connected directly to the inverted output of the PFD analog circuitry (external to the SNVS block)

pub fn por_observ(&mut self) -> POR_OBSERV_W[src]

Bit 15 - Power On Reset (POR) Observability Flop The asynchronous reset input of this flop is connected directly to the output of the POR analog circuitry (external to the SNVS

pub fn oscb(&mut self) -> OSCB_W[src]

Bit 28 - Oscillator Bypass When OSCB=1 the osc_bypass signal is asserted

impl W<u32, Reg<u32, _LPSR>>[src]

pub fn lpta(&mut self) -> LPTA_W[src]

Bit 0 - LP Time Alarm

pub fn srtcr(&mut self) -> SRTCR_W[src]

Bit 1 - Secure Real Time Counter Rollover

pub fn mcr(&mut self) -> MCR_W[src]

Bit 2 - Monotonic Counter Rollover

pub fn pgd(&mut self) -> PGD_W[src]

Bit 3 - Power Supply Glitch Detected 0 No power supply glitch. 1 Power supply glitch is detected.

pub fn et1d(&mut self) -> ET1D_W[src]

Bit 9 - External Tampering 1 Detected

pub fn esvd(&mut self) -> ESVD_W[src]

Bit 16 - External Security Violation Detected Indicates that a security violation is detected on one of the HP security violation ports

pub fn eo(&mut self) -> EO_W[src]

Bit 17 - Emergency Off This bit is set when a power off is requested.

pub fn spo(&mut self) -> SPO_W[src]

Bit 18 - Set Power Off The SPO bit is set when the power button is pressed longer than the configured debounce time

pub fn sed(&mut self) -> SED_W[src]

Bit 20 - Scan Exit Detected

impl W<u32, Reg<u32, _LPSRTCMR>>[src]

pub fn srtc(&mut self) -> SRTC_W[src]

Bits 0:14 - LP Secure Real Time Counter The most-significant 15 bits of the SRTC

impl W<u32, Reg<u32, _LPSRTCLR>>[src]

pub fn srtc(&mut self) -> SRTC_W[src]

Bits 0:31 - LP Secure Real Time Counter least-significant 32 bits This register can be programmed only when SRTC is not active and not locked, meaning the SRTC_ENV, SRTC_SL, and SRTC_HL bits are not set

impl W<u32, Reg<u32, _LPTAR>>[src]

pub fn lpta(&mut self) -> LPTA_W[src]

Bits 0:31 - LP Time Alarm This register can be programmed only when the LP time alarm is disabled (LPTA_EN bit is not set)

impl W<u32, Reg<u32, _LPPGDR>>[src]

pub fn pgd(&mut self) -> PGD_W[src]

Bits 0:31 - Power Glitch Detector Value

impl W<u32, Reg<u32, _LPGPR0_LEGACY_ALIAS>>[src]

pub fn gpr(&mut self) -> GPR_W[src]

Bits 0:31 - General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.

impl W<u32, Reg<u32, _LPZMKR>>[src]

pub fn zmk(&mut self) -> ZMK_W[src]

Bits 0:31 - Zeroizable Master Key Each of these registers contains 32 bits of the 256-bit ZMK value

impl W<u32, Reg<u32, _LPGPR_ALIAS>>[src]

pub fn gpr(&mut self) -> GPR_W[src]

Bits 0:31 - General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.

impl W<u32, Reg<u32, _LPGPR>>[src]

pub fn gpr(&mut self) -> GPR_W[src]

Bits 0:31 - General Purpose Register When GPR_SL or GPR_HL bit is set, the register cannot be programmed.

Auto Trait Implementations

impl<U, REG> Send for W<U, REG> where
    REG: Send,
    U: Send

impl<U, REG> Sync for W<U, REG> where
    REG: Sync,
    U: Sync

impl<U, REG> Unpin for W<U, REG> where
    REG: Unpin,
    U: Unpin

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.