[−] List of all items
Structs
- R
- Reg
- RegisterBlock
- W
- as_buf::ADDR_W
- as_clrkeyhigh::PIXEL_W
- as_clrkeylow::PIXEL_W
- as_ctrl::ALPHA_CTRL_W
- as_ctrl::ALPHA_INVERT_W
- as_ctrl::ALPHA_W
- as_ctrl::ENABLE_COLORKEY_W
- as_ctrl::FORMAT_W
- as_ctrl::ROP_W
- as_pitch::PITCH_W
- csc1_coef0::BYPASS_W
- csc1_coef0::C0_W
- csc1_coef0::UV_OFFSET_W
- csc1_coef0::YCBCR_MODE_W
- csc1_coef0::Y_OFFSET_W
- csc1_coef1::C1_W
- csc1_coef1::C4_W
- csc1_coef2::C2_W
- csc1_coef2::C3_W
- ctrl::BLOCK_SIZE_W
- ctrl::CLKGATE_W
- ctrl::ENABLE_LCD_HANDSHAKE_W
- ctrl::ENABLE_W
- ctrl::EN_REPEAT_W
- ctrl::HFLIP_W
- ctrl::IRQ_ENABLE_W
- ctrl::NEXT_IRQ_ENABLE_W
- ctrl::ROTATE_W
- ctrl::ROT_POS_W
- ctrl::SFTRST_W
- ctrl::VFLIP_W
- ctrl_clr::BLOCK_SIZE_W
- ctrl_clr::CLKGATE_W
- ctrl_clr::ENABLE_LCD_HANDSHAKE_W
- ctrl_clr::ENABLE_W
- ctrl_clr::EN_REPEAT_W
- ctrl_clr::HFLIP_W
- ctrl_clr::IRQ_ENABLE_W
- ctrl_clr::NEXT_IRQ_ENABLE_W
- ctrl_clr::ROTATE_W
- ctrl_clr::ROT_POS_W
- ctrl_clr::SFTRST_W
- ctrl_clr::VFLIP_W
- ctrl_set::BLOCK_SIZE_W
- ctrl_set::CLKGATE_W
- ctrl_set::ENABLE_LCD_HANDSHAKE_W
- ctrl_set::ENABLE_W
- ctrl_set::EN_REPEAT_W
- ctrl_set::HFLIP_W
- ctrl_set::IRQ_ENABLE_W
- ctrl_set::NEXT_IRQ_ENABLE_W
- ctrl_set::ROTATE_W
- ctrl_set::ROT_POS_W
- ctrl_set::SFTRST_W
- ctrl_set::VFLIP_W
- ctrl_tog::BLOCK_SIZE_W
- ctrl_tog::CLKGATE_W
- ctrl_tog::ENABLE_LCD_HANDSHAKE_W
- ctrl_tog::ENABLE_W
- ctrl_tog::EN_REPEAT_W
- ctrl_tog::HFLIP_W
- ctrl_tog::IRQ_ENABLE_W
- ctrl_tog::NEXT_IRQ_ENABLE_W
- ctrl_tog::ROTATE_W
- ctrl_tog::ROT_POS_W
- ctrl_tog::SFTRST_W
- ctrl_tog::VFLIP_W
- next::POINTER_W
- out_as_lrc::X_W
- out_as_lrc::Y_W
- out_as_ulc::X_W
- out_as_ulc::Y_W
- out_buf2::ADDR_W
- out_buf::ADDR_W
- out_ctrl::ALPHA_OUTPUT_W
- out_ctrl::ALPHA_W
- out_ctrl::FORMAT_W
- out_ctrl::INTERLACED_OUTPUT_W
- out_ctrl_clr::ALPHA_OUTPUT_W
- out_ctrl_clr::ALPHA_W
- out_ctrl_clr::FORMAT_W
- out_ctrl_clr::INTERLACED_OUTPUT_W
- out_ctrl_set::ALPHA_OUTPUT_W
- out_ctrl_set::ALPHA_W
- out_ctrl_set::FORMAT_W
- out_ctrl_set::INTERLACED_OUTPUT_W
- out_ctrl_tog::ALPHA_OUTPUT_W
- out_ctrl_tog::ALPHA_W
- out_ctrl_tog::FORMAT_W
- out_ctrl_tog::INTERLACED_OUTPUT_W
- out_lrc::X_W
- out_lrc::Y_W
- out_pitch::PITCH_W
- out_ps_lrc::X_W
- out_ps_lrc::Y_W
- out_ps_ulc::X_W
- out_ps_ulc::Y_W
- porter_duff_ctrl::POTER_DUFF_ENABLE_W
- porter_duff_ctrl::S0_ALPHA_MODE_W
- porter_duff_ctrl::S0_COLOR_MODE_W
- porter_duff_ctrl::S0_GLOBAL_ALPHA_MODE_W
- porter_duff_ctrl::S0_GLOBAL_ALPHA_W
- porter_duff_ctrl::S0_S1_FACTOR_MODE_W
- porter_duff_ctrl::S1_ALPHA_MODE_W
- porter_duff_ctrl::S1_COLOR_MODE_W
- porter_duff_ctrl::S1_GLOBAL_ALPHA_MODE_W
- porter_duff_ctrl::S1_GLOBAL_ALPHA_W
- porter_duff_ctrl::S1_S0_FACTOR_MODE_W
- power::CTRL_W
- power::ROT_MEM_LP_STATE_W
- ps_background::COLOR_W
- ps_buf::ADDR_W
- ps_clrkeyhigh::PIXEL_W
- ps_clrkeylow::PIXEL_W
- ps_ctrl::DECX_W
- ps_ctrl::DECY_W
- ps_ctrl::FORMAT_W
- ps_ctrl::WB_SWAP_W
- ps_ctrl_clr::DECX_W
- ps_ctrl_clr::DECY_W
- ps_ctrl_clr::FORMAT_W
- ps_ctrl_clr::WB_SWAP_W
- ps_ctrl_set::DECX_W
- ps_ctrl_set::DECY_W
- ps_ctrl_set::FORMAT_W
- ps_ctrl_set::WB_SWAP_W
- ps_ctrl_tog::DECX_W
- ps_ctrl_tog::DECY_W
- ps_ctrl_tog::FORMAT_W
- ps_ctrl_tog::WB_SWAP_W
- ps_offset::XOFFSET_W
- ps_offset::YOFFSET_W
- ps_pitch::PITCH_W
- ps_scale::XSCALE_W
- ps_scale::YSCALE_W
- ps_ubuf::ADDR_W
- ps_vbuf::ADDR_W
- stat::AXI_READ_ERROR_W
- stat::AXI_WRITE_ERROR_W
- stat::IRQ_W
- stat::LUT_DMA_LOAD_DONE_IRQ_W
- stat::NEXT_IRQ_W
- stat_clr::AXI_READ_ERROR_W
- stat_clr::AXI_WRITE_ERROR_W
- stat_clr::IRQ_W
- stat_clr::LUT_DMA_LOAD_DONE_IRQ_W
- stat_clr::NEXT_IRQ_W
- stat_set::AXI_READ_ERROR_W
- stat_set::AXI_WRITE_ERROR_W
- stat_set::IRQ_W
- stat_set::LUT_DMA_LOAD_DONE_IRQ_W
- stat_set::NEXT_IRQ_W
- stat_tog::AXI_READ_ERROR_W
- stat_tog::AXI_WRITE_ERROR_W
- stat_tog::IRQ_W
- stat_tog::LUT_DMA_LOAD_DONE_IRQ_W
- stat_tog::NEXT_IRQ_W
Enums
- Variant
- as_ctrl::ALPHA_CTRL_A
- as_ctrl::FORMAT_A
- as_ctrl::ROP_A
- ctrl::BLOCK_SIZE_A
- ctrl::ROTATE_A
- ctrl_clr::BLOCK_SIZE_A
- ctrl_clr::ROTATE_A
- ctrl_set::BLOCK_SIZE_A
- ctrl_set::ROTATE_A
- ctrl_tog::BLOCK_SIZE_A
- ctrl_tog::ROTATE_A
- out_ctrl::FORMAT_A
- out_ctrl::INTERLACED_OUTPUT_A
- out_ctrl_clr::FORMAT_A
- out_ctrl_clr::INTERLACED_OUTPUT_A
- out_ctrl_set::FORMAT_A
- out_ctrl_set::INTERLACED_OUTPUT_A
- out_ctrl_tog::FORMAT_A
- out_ctrl_tog::INTERLACED_OUTPUT_A
- power::ROT_MEM_LP_STATE_A
- ps_ctrl::DECX_A
- ps_ctrl::DECY_A
- ps_ctrl::FORMAT_A
- ps_ctrl_clr::DECX_A
- ps_ctrl_clr::DECY_A
- ps_ctrl_clr::FORMAT_A
- ps_ctrl_set::DECX_A
- ps_ctrl_set::DECY_A
- ps_ctrl_set::FORMAT_A
- ps_ctrl_tog::DECX_A
- ps_ctrl_tog::DECY_A
- ps_ctrl_tog::FORMAT_A
Traits
Typedefs
- AS_BUF
- AS_CLRKEYHIGH
- AS_CLRKEYLOW
- AS_CTRL
- AS_PITCH
- CSC1_COEF0
- CSC1_COEF1
- CSC1_COEF2
- CTRL
- CTRL_CLR
- CTRL_SET
- CTRL_TOG
- NEXT
- OUT_AS_LRC
- OUT_AS_ULC
- OUT_BUF
- OUT_BUF2
- OUT_CTRL
- OUT_CTRL_CLR
- OUT_CTRL_SET
- OUT_CTRL_TOG
- OUT_LRC
- OUT_PITCH
- OUT_PS_LRC
- OUT_PS_ULC
- PORTER_DUFF_CTRL
- POWER
- PS_BACKGROUND
- PS_BUF
- PS_CLRKEYHIGH
- PS_CLRKEYLOW
- PS_CTRL
- PS_CTRL_CLR
- PS_CTRL_SET
- PS_CTRL_TOG
- PS_OFFSET
- PS_PITCH
- PS_SCALE
- PS_UBUF
- PS_VBUF
- STAT
- STAT_CLR
- STAT_SET
- STAT_TOG
- as_buf::ADDR_R
- as_buf::R
- as_buf::W
- as_clrkeyhigh::PIXEL_R
- as_clrkeyhigh::R
- as_clrkeyhigh::RSVD1_R
- as_clrkeyhigh::W
- as_clrkeylow::PIXEL_R
- as_clrkeylow::R
- as_clrkeylow::RSVD1_R
- as_clrkeylow::W
- as_ctrl::ALPHA_CTRL_R
- as_ctrl::ALPHA_INVERT_R
- as_ctrl::ALPHA_R
- as_ctrl::ENABLE_COLORKEY_R
- as_ctrl::FORMAT_R
- as_ctrl::R
- as_ctrl::ROP_R
- as_ctrl::RSVD0_R
- as_ctrl::RSVD1_R
- as_ctrl::W
- as_pitch::PITCH_R
- as_pitch::R
- as_pitch::RSVD_R
- as_pitch::W
- csc1_coef0::BYPASS_R
- csc1_coef0::C0_R
- csc1_coef0::R
- csc1_coef0::RSVD1_R
- csc1_coef0::UV_OFFSET_R
- csc1_coef0::W
- csc1_coef0::YCBCR_MODE_R
- csc1_coef0::Y_OFFSET_R
- csc1_coef1::C1_R
- csc1_coef1::C4_R
- csc1_coef1::R
- csc1_coef1::RSVD0_R
- csc1_coef1::RSVD1_R
- csc1_coef1::W
- csc1_coef2::C2_R
- csc1_coef2::C3_R
- csc1_coef2::R
- csc1_coef2::RSVD0_R
- csc1_coef2::RSVD1_R
- csc1_coef2::W
- ctrl::BLOCK_SIZE_R
- ctrl::CLKGATE_R
- ctrl::ENABLE_LCD_HANDSHAKE_R
- ctrl::ENABLE_R
- ctrl::EN_REPEAT_R
- ctrl::HFLIP_R
- ctrl::IRQ_ENABLE_R
- ctrl::NEXT_IRQ_ENABLE_R
- ctrl::R
- ctrl::ROTATE_R
- ctrl::ROT_POS_R
- ctrl::RSVD0_R
- ctrl::RSVD1_R
- ctrl::RSVD3_R
- ctrl::RSVD4_R
- ctrl::SFTRST_R
- ctrl::VFLIP_R
- ctrl::W
- ctrl_clr::BLOCK_SIZE_R
- ctrl_clr::CLKGATE_R
- ctrl_clr::ENABLE_LCD_HANDSHAKE_R
- ctrl_clr::ENABLE_R
- ctrl_clr::EN_REPEAT_R
- ctrl_clr::HFLIP_R
- ctrl_clr::IRQ_ENABLE_R
- ctrl_clr::NEXT_IRQ_ENABLE_R
- ctrl_clr::R
- ctrl_clr::ROTATE_R
- ctrl_clr::ROT_POS_R
- ctrl_clr::RSVD0_R
- ctrl_clr::RSVD1_R
- ctrl_clr::RSVD3_R
- ctrl_clr::RSVD4_R
- ctrl_clr::SFTRST_R
- ctrl_clr::VFLIP_R
- ctrl_clr::W
- ctrl_set::BLOCK_SIZE_R
- ctrl_set::CLKGATE_R
- ctrl_set::ENABLE_LCD_HANDSHAKE_R
- ctrl_set::ENABLE_R
- ctrl_set::EN_REPEAT_R
- ctrl_set::HFLIP_R
- ctrl_set::IRQ_ENABLE_R
- ctrl_set::NEXT_IRQ_ENABLE_R
- ctrl_set::R
- ctrl_set::ROTATE_R
- ctrl_set::ROT_POS_R
- ctrl_set::RSVD0_R
- ctrl_set::RSVD1_R
- ctrl_set::RSVD3_R
- ctrl_set::RSVD4_R
- ctrl_set::SFTRST_R
- ctrl_set::VFLIP_R
- ctrl_set::W
- ctrl_tog::BLOCK_SIZE_R
- ctrl_tog::CLKGATE_R
- ctrl_tog::ENABLE_LCD_HANDSHAKE_R
- ctrl_tog::ENABLE_R
- ctrl_tog::EN_REPEAT_R
- ctrl_tog::HFLIP_R
- ctrl_tog::IRQ_ENABLE_R
- ctrl_tog::NEXT_IRQ_ENABLE_R
- ctrl_tog::R
- ctrl_tog::ROTATE_R
- ctrl_tog::ROT_POS_R
- ctrl_tog::RSVD0_R
- ctrl_tog::RSVD1_R
- ctrl_tog::RSVD3_R
- ctrl_tog::RSVD4_R
- ctrl_tog::SFTRST_R
- ctrl_tog::VFLIP_R
- ctrl_tog::W
- next::ENABLED_R
- next::POINTER_R
- next::R
- next::RSVD_R
- next::W
- out_as_lrc::R
- out_as_lrc::RSVD0_R
- out_as_lrc::RSVD1_R
- out_as_lrc::W
- out_as_lrc::X_R
- out_as_lrc::Y_R
- out_as_ulc::R
- out_as_ulc::RSVD0_R
- out_as_ulc::RSVD1_R
- out_as_ulc::W
- out_as_ulc::X_R
- out_as_ulc::Y_R
- out_buf2::ADDR_R
- out_buf2::R
- out_buf2::W
- out_buf::ADDR_R
- out_buf::R
- out_buf::W
- out_ctrl::ALPHA_OUTPUT_R
- out_ctrl::ALPHA_R
- out_ctrl::FORMAT_R
- out_ctrl::INTERLACED_OUTPUT_R
- out_ctrl::R
- out_ctrl::RSVD0_R
- out_ctrl::RSVD1_R
- out_ctrl::W
- out_ctrl_clr::ALPHA_OUTPUT_R
- out_ctrl_clr::ALPHA_R
- out_ctrl_clr::FORMAT_R
- out_ctrl_clr::INTERLACED_OUTPUT_R
- out_ctrl_clr::R
- out_ctrl_clr::RSVD0_R
- out_ctrl_clr::RSVD1_R
- out_ctrl_clr::W
- out_ctrl_set::ALPHA_OUTPUT_R
- out_ctrl_set::ALPHA_R
- out_ctrl_set::FORMAT_R
- out_ctrl_set::INTERLACED_OUTPUT_R
- out_ctrl_set::R
- out_ctrl_set::RSVD0_R
- out_ctrl_set::RSVD1_R
- out_ctrl_set::W
- out_ctrl_tog::ALPHA_OUTPUT_R
- out_ctrl_tog::ALPHA_R
- out_ctrl_tog::FORMAT_R
- out_ctrl_tog::INTERLACED_OUTPUT_R
- out_ctrl_tog::R
- out_ctrl_tog::RSVD0_R
- out_ctrl_tog::RSVD1_R
- out_ctrl_tog::W
- out_lrc::R
- out_lrc::RSVD0_R
- out_lrc::RSVD1_R
- out_lrc::W
- out_lrc::X_R
- out_lrc::Y_R
- out_pitch::PITCH_R
- out_pitch::R
- out_pitch::RSVD_R
- out_pitch::W
- out_ps_lrc::R
- out_ps_lrc::RSVD0_R
- out_ps_lrc::RSVD1_R
- out_ps_lrc::W
- out_ps_lrc::X_R
- out_ps_lrc::Y_R
- out_ps_ulc::R
- out_ps_ulc::RSVD0_R
- out_ps_ulc::RSVD1_R
- out_ps_ulc::W
- out_ps_ulc::X_R
- out_ps_ulc::Y_R
- porter_duff_ctrl::POTER_DUFF_ENABLE_R
- porter_duff_ctrl::R
- porter_duff_ctrl::S0_ALPHA_MODE_R
- porter_duff_ctrl::S0_COLOR_MODE_R
- porter_duff_ctrl::S0_GLOBAL_ALPHA_MODE_R
- porter_duff_ctrl::S0_GLOBAL_ALPHA_R
- porter_duff_ctrl::S0_S1_FACTOR_MODE_R
- porter_duff_ctrl::S1_ALPHA_MODE_R
- porter_duff_ctrl::S1_COLOR_MODE_R
- porter_duff_ctrl::S1_GLOBAL_ALPHA_MODE_R
- porter_duff_ctrl::S1_GLOBAL_ALPHA_R
- porter_duff_ctrl::S1_S0_FACTOR_MODE_R
- porter_duff_ctrl::W
- power::CTRL_R
- power::R
- power::ROT_MEM_LP_STATE_R
- power::W
- ps_background::COLOR_R
- ps_background::R
- ps_background::RSVD_R
- ps_background::W
- ps_buf::ADDR_R
- ps_buf::R
- ps_buf::W
- ps_clrkeyhigh::PIXEL_R
- ps_clrkeyhigh::R
- ps_clrkeyhigh::RSVD1_R
- ps_clrkeyhigh::W
- ps_clrkeylow::PIXEL_R
- ps_clrkeylow::R
- ps_clrkeylow::RSVD1_R
- ps_clrkeylow::W
- ps_ctrl::DECX_R
- ps_ctrl::DECY_R
- ps_ctrl::FORMAT_R
- ps_ctrl::R
- ps_ctrl::RSVD0_R
- ps_ctrl::RSVD1_R
- ps_ctrl::W
- ps_ctrl::WB_SWAP_R
- ps_ctrl_clr::DECX_R
- ps_ctrl_clr::DECY_R
- ps_ctrl_clr::FORMAT_R
- ps_ctrl_clr::R
- ps_ctrl_clr::RSVD0_R
- ps_ctrl_clr::RSVD1_R
- ps_ctrl_clr::W
- ps_ctrl_clr::WB_SWAP_R
- ps_ctrl_set::DECX_R
- ps_ctrl_set::DECY_R
- ps_ctrl_set::FORMAT_R
- ps_ctrl_set::R
- ps_ctrl_set::RSVD0_R
- ps_ctrl_set::RSVD1_R
- ps_ctrl_set::W
- ps_ctrl_set::WB_SWAP_R
- ps_ctrl_tog::DECX_R
- ps_ctrl_tog::DECY_R
- ps_ctrl_tog::FORMAT_R
- ps_ctrl_tog::R
- ps_ctrl_tog::RSVD0_R
- ps_ctrl_tog::RSVD1_R
- ps_ctrl_tog::W
- ps_ctrl_tog::WB_SWAP_R
- ps_offset::R
- ps_offset::RSVD1_R
- ps_offset::RSVD2_R
- ps_offset::W
- ps_offset::XOFFSET_R
- ps_offset::YOFFSET_R
- ps_pitch::PITCH_R
- ps_pitch::R
- ps_pitch::RSVD_R
- ps_pitch::W
- ps_scale::R
- ps_scale::RSVD1_R
- ps_scale::RSVD2_R
- ps_scale::W
- ps_scale::XSCALE_R
- ps_scale::YSCALE_R
- ps_ubuf::ADDR_R
- ps_ubuf::R
- ps_ubuf::W
- ps_vbuf::ADDR_R
- ps_vbuf::R
- ps_vbuf::W
- stat::AXI_ERROR_ID_R
- stat::AXI_READ_ERROR_R
- stat::AXI_WRITE_ERROR_R
- stat::BLOCKX_R
- stat::BLOCKY_R
- stat::IRQ_R
- stat::LUT_DMA_LOAD_DONE_IRQ_R
- stat::NEXT_IRQ_R
- stat::R
- stat::RSVD2_R
- stat::W
- stat_clr::AXI_ERROR_ID_R
- stat_clr::AXI_READ_ERROR_R
- stat_clr::AXI_WRITE_ERROR_R
- stat_clr::BLOCKX_R
- stat_clr::BLOCKY_R
- stat_clr::IRQ_R
- stat_clr::LUT_DMA_LOAD_DONE_IRQ_R
- stat_clr::NEXT_IRQ_R
- stat_clr::R
- stat_clr::RSVD2_R
- stat_clr::W
- stat_set::AXI_ERROR_ID_R
- stat_set::AXI_READ_ERROR_R
- stat_set::AXI_WRITE_ERROR_R
- stat_set::BLOCKX_R
- stat_set::BLOCKY_R
- stat_set::IRQ_R
- stat_set::LUT_DMA_LOAD_DONE_IRQ_R
- stat_set::NEXT_IRQ_R
- stat_set::R
- stat_set::RSVD2_R
- stat_set::W
- stat_tog::AXI_ERROR_ID_R
- stat_tog::AXI_READ_ERROR_R
- stat_tog::AXI_WRITE_ERROR_R
- stat_tog::BLOCKX_R
- stat_tog::BLOCKY_R
- stat_tog::IRQ_R
- stat_tog::LUT_DMA_LOAD_DONE_IRQ_R
- stat_tog::NEXT_IRQ_R
- stat_tog::R
- stat_tog::RSVD2_R
- stat_tog::W