[−][src]Struct imxrt1062_pwm1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

`impl<U, REG> W<U, REG>`[src]

`pub unsafe fn bits(&mut self, bits: U) -> &mut Self`[src]

Writes raw bits to the register

`impl W<u16, Reg<u16, _SMINIT>>`[src]

`pub fn init(&mut self) -> INIT_W`[src]

Bits 0:15 - Initial Count Register Bits

`impl W<u16, Reg<u16, _SMCTRL2>>`[src]

`pub fn clk_sel(&mut self) -> CLK_SEL_W`[src]

Bits 0:1 - Clock Source Select

`pub fn reload_sel(&mut self) -> RELOAD_SEL_W`[src]

Bit 2 - Reload Source Select

`pub fn force_sel(&mut self) -> FORCE_SEL_W`[src]

Bits 3:5 - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.

`pub fn force(&mut self) -> FORCE_W`[src]

Bit 6 - Force Initialization

`pub fn frcen(&mut self) -> FRCEN_W`[src]

Bit 7 - FRCEN

`pub fn init_sel(&mut self) -> INIT_SEL_W`[src]

Bits 8:9 - Initialization Control Select

`pub fn pwmx_init(&mut self) -> PWMX_INIT_W`[src]

Bit 10 - PWM_X Initial Value

`pub fn pwm45_init(&mut self) -> PWM45_INIT_W`[src]

Bit 11 - PWM45 Initial Value

`pub fn pwm23_init(&mut self) -> PWM23_INIT_W`[src]

Bit 12 - PWM23 Initial Value

`pub fn indep(&mut self) -> INDEP_W`[src]

Bit 13 - Independent or Complementary Pair Operation

`pub fn waiten(&mut self) -> WAITEN_W`[src]

Bit 14 - WAIT Enable

`pub fn dbgen(&mut self) -> DBGEN_W`[src]

Bit 15 - Debug Enable

`impl W<u16, Reg<u16, _SMCTRL>>`[src]

`pub fn dblen(&mut self) -> DBLEN_W`[src]

Bit 0 - Double Switching Enable

`pub fn dblx(&mut self) -> DBLX_W`[src]

Bit 1 - PWMX Double Switching Enable

`pub fn ldmod(&mut self) -> LDMOD_W`[src]

Bit 2 - Load Mode Select

`pub fn split(&mut self) -> SPLIT_W`[src]

Bit 3 - Split the DBLPWM signal to PWMA and PWMB

`pub fn prsc(&mut self) -> PRSC_W`[src]

Bits 4:6 - Prescaler

`pub fn compmode(&mut self) -> COMPMODE_W`[src]

Bit 7 - Compare Mode

`pub fn full(&mut self) -> FULL_W`[src]

Bit 10 - Full Cycle Reload

`pub fn half(&mut self) -> HALF_W`[src]

Bit 11 - Half Cycle Reload

`pub fn ldfq(&mut self) -> LDFQ_W`[src]

Bits 12:15 - Load Frequency

`impl W<u16, Reg<u16, _SMVAL0>>`[src]

`pub fn val0(&mut self) -> VAL0_W`[src]

Bits 0:15 - Value Register 0

`impl W<u16, Reg<u16, _SMFRACVAL1>>`[src]

`pub fn fracval1(&mut self) -> FRACVAL1_W`[src]

Bits 11:15 - Fractional Value 1 Register

`impl W<u16, Reg<u16, _SMVAL1>>`[src]

`pub fn val1(&mut self) -> VAL1_W`[src]

Bits 0:15 - Value Register 1

`impl W<u16, Reg<u16, _SMFRACVAL2>>`[src]

`pub fn fracval2(&mut self) -> FRACVAL2_W`[src]

Bits 11:15 - Fractional Value 2

`impl W<u16, Reg<u16, _SMVAL2>>`[src]

`pub fn val2(&mut self) -> VAL2_W`[src]

Bits 0:15 - Value Register 2

`impl W<u16, Reg<u16, _SMFRACVAL3>>`[src]

`pub fn fracval3(&mut self) -> FRACVAL3_W`[src]

Bits 11:15 - Fractional Value 3

`impl W<u16, Reg<u16, _SMVAL3>>`[src]

`pub fn val3(&mut self) -> VAL3_W`[src]

Bits 0:15 - Value Register 3

`impl W<u16, Reg<u16, _SMFRACVAL4>>`[src]

`pub fn fracval4(&mut self) -> FRACVAL4_W`[src]

Bits 11:15 - Fractional Value 4

`impl W<u16, Reg<u16, _SMVAL4>>`[src]

`pub fn val4(&mut self) -> VAL4_W`[src]

Bits 0:15 - Value Register 4

`impl W<u16, Reg<u16, _SMFRACVAL5>>`[src]

`pub fn fracval5(&mut self) -> FRACVAL5_W`[src]

Bits 11:15 - Fractional Value 5

`impl W<u16, Reg<u16, _SMVAL5>>`[src]

`pub fn val5(&mut self) -> VAL5_W`[src]

Bits 0:15 - Value Register 5

`impl W<u16, Reg<u16, _SMFRCTRL>>`[src]

`pub fn frac1_en(&mut self) -> FRAC1_EN_W`[src]

Bit 1 - Fractional Cycle PWM Period Enable

`pub fn frac23_en(&mut self) -> FRAC23_EN_W`[src]

Bit 2 - Fractional Cycle Placement Enable for PWM_A

`pub fn frac45_en(&mut self) -> FRAC45_EN_W`[src]

Bit 4 - Fractional Cycle Placement Enable for PWM_B

`pub fn frac_pu(&mut self) -> FRAC_PU_W`[src]

Bit 8 - Fractional Delay Circuit Power Up

`impl W<u16, Reg<u16, _SMOCTRL>>`[src]

`pub fn pwmxfs(&mut self) -> PWMXFS_W`[src]

Bits 0:1 - PWM_X Fault State

`pub fn pwmbfs(&mut self) -> PWMBFS_W`[src]

Bits 2:3 - PWM_B Fault State

`pub fn pwmafs(&mut self) -> PWMAFS_W`[src]

Bits 4:5 - PWM_A Fault State

`pub fn polx(&mut self) -> POLX_W`[src]

Bit 8 - PWM_X Output Polarity

`pub fn polb(&mut self) -> POLB_W`[src]

Bit 9 - PWM_B Output Polarity

`pub fn pola(&mut self) -> POLA_W`[src]

Bit 10 - PWM_A Output Polarity

`impl W<u16, Reg<u16, _SMSTS>>`[src]

`pub fn cmpf(&mut self) -> CMPF_W`[src]

Bits 0:5 - Compare Flags

`pub fn cfx0(&mut self) -> CFX0_W`[src]

Bit 6 - Capture Flag X0

`pub fn cfx1(&mut self) -> CFX1_W`[src]

Bit 7 - Capture Flag X1

`pub fn cfb0(&mut self) -> CFB0_W`[src]

Bit 8 - Capture Flag B0

`pub fn cfb1(&mut self) -> CFB1_W`[src]

Bit 9 - Capture Flag B1

`pub fn cfa0(&mut self) -> CFA0_W`[src]

Bit 10 - Capture Flag A0

`pub fn cfa1(&mut self) -> CFA1_W`[src]

Bit 11 - Capture Flag A1

`pub fn rf(&mut self) -> RF_W`[src]

Bit 12 - Reload Flag

`pub fn ref_(&mut self) -> REF_W`[src]

Bit 13 - Reload Error Flag

`impl W<u16, Reg<u16, _SMINTEN>>`[src]

`pub fn cmpie(&mut self) -> CMPIE_W`[src]

Bits 0:5 - Compare Interrupt Enables

`pub fn cx0ie(&mut self) -> CX0IE_W`[src]

Bit 6 - Capture X 0 Interrupt Enable

`pub fn cx1ie(&mut self) -> CX1IE_W`[src]

Bit 7 - Capture X 1 Interrupt Enable

`pub fn cb0ie(&mut self) -> CB0IE_W`[src]

Bit 8 - Capture B 0 Interrupt Enable

`pub fn cb1ie(&mut self) -> CB1IE_W`[src]

Bit 9 - Capture B 1 Interrupt Enable

`pub fn ca0ie(&mut self) -> CA0IE_W`[src]

Bit 10 - Capture A 0 Interrupt Enable

`pub fn ca1ie(&mut self) -> CA1IE_W`[src]

Bit 11 - Capture A 1 Interrupt Enable

`pub fn rie(&mut self) -> RIE_W`[src]

Bit 12 - Reload Interrupt Enable

`pub fn reie(&mut self) -> REIE_W`[src]

Bit 13 - Reload Error Interrupt Enable

`impl W<u16, Reg<u16, _SMDMAEN>>`[src]

`pub fn cx0de(&mut self) -> CX0DE_W`[src]

Bit 0 - Capture X0 FIFO DMA Enable

`pub fn cx1de(&mut self) -> CX1DE_W`[src]

Bit 1 - Capture X1 FIFO DMA Enable

`pub fn cb0de(&mut self) -> CB0DE_W`[src]

Bit 2 - Capture B0 FIFO DMA Enable

`pub fn cb1de(&mut self) -> CB1DE_W`[src]

Bit 3 - Capture B1 FIFO DMA Enable

`pub fn ca0de(&mut self) -> CA0DE_W`[src]

Bit 4 - Capture A0 FIFO DMA Enable

`pub fn ca1de(&mut self) -> CA1DE_W`[src]

Bit 5 - Capture A1 FIFO DMA Enable

`pub fn captde(&mut self) -> CAPTDE_W`[src]

Bits 6:7 - Capture DMA Enable Source Select

`pub fn fand(&mut self) -> FAND_W`[src]

Bit 8 - FIFO Watermark AND Control

`pub fn valde(&mut self) -> VALDE_W`[src]

Bit 9 - Value Registers DMA Enable

`impl W<u16, Reg<u16, _SMTCTRL>>`[src]

`pub fn out_trig_en(&mut self) -> OUT_TRIG_EN_W`[src]

Bits 0:5 - Output Trigger Enables

`pub fn trgfrq(&mut self) -> TRGFRQ_W`[src]

Bit 12 - Trigger frequency

`pub fn pwbot1(&mut self) -> PWBOT1_W`[src]

Bit 14 - Output Trigger 1 Source Select

`pub fn pwaot0(&mut self) -> PWAOT0_W`[src]

Bit 15 - Output Trigger 0 Source Select

`impl W<u16, Reg<u16, _SMDISMAP0>>`[src]

`pub fn dis0a(&mut self) -> DIS0A_W`[src]

Bits 0:3 - PWM_A Fault Disable Mask 0

`pub fn dis0b(&mut self) -> DIS0B_W`[src]

Bits 4:7 - PWM_B Fault Disable Mask 0

`pub fn dis0x(&mut self) -> DIS0X_W`[src]

Bits 8:11 - PWM_X Fault Disable Mask 0

`impl W<u16, Reg<u16, _SMDISMAP1>>`[src]

`pub fn dis1a(&mut self) -> DIS1A_W`[src]

Bits 0:3 - PWM_A Fault Disable Mask 1

`pub fn dis1b(&mut self) -> DIS1B_W`[src]

Bits 4:7 - PWM_B Fault Disable Mask 1

`pub fn dis1x(&mut self) -> DIS1X_W`[src]

Bits 8:11 - PWM_X Fault Disable Mask 1

`impl W<u16, Reg<u16, _SMDTCNT0>>`[src]

`pub fn dtcnt0(&mut self) -> DTCNT0_W`[src]

Bits 0:15 - DTCNT0

`impl W<u16, Reg<u16, _SMDTCNT1>>`[src]

`pub fn dtcnt1(&mut self) -> DTCNT1_W`[src]

Bits 0:15 - DTCNT1

`impl W<u16, Reg<u16, _SMCAPTCTRLA>>`[src]

`pub fn arma(&mut self) -> ARMA_W`[src]

Bit 0 - Arm A

`pub fn oneshota(&mut self) -> ONESHOTA_W`[src]

Bit 1 - One Shot Mode A

`pub fn edga0(&mut self) -> EDGA0_W`[src]

Bits 2:3 - Edge A 0

`pub fn edga1(&mut self) -> EDGA1_W`[src]

Bits 4:5 - Edge A 1

`pub fn inp_sela(&mut self) -> INP_SELA_W`[src]

Bit 6 - Input Select A

`pub fn edgcnta_en(&mut self) -> EDGCNTA_EN_W`[src]

Bit 7 - Edge Counter A Enable

`pub fn cfawm(&mut self) -> CFAWM_W`[src]

Bits 8:9 - Capture A FIFOs Water Mark

`impl W<u16, Reg<u16, _SMCAPTCOMPA>>`[src]

`pub fn edgcmpa(&mut self) -> EDGCMPA_W`[src]

Bits 0:7 - Edge Compare A

`impl W<u16, Reg<u16, _SMCAPTCTRLB>>`[src]

`pub fn armb(&mut self) -> ARMB_W`[src]

Bit 0 - Arm B

`pub fn oneshotb(&mut self) -> ONESHOTB_W`[src]

Bit 1 - One Shot Mode B

`pub fn edgb0(&mut self) -> EDGB0_W`[src]

Bits 2:3 - Edge B 0

`pub fn edgb1(&mut self) -> EDGB1_W`[src]

Bits 4:5 - Edge B 1

`pub fn inp_selb(&mut self) -> INP_SELB_W`[src]

Bit 6 - Input Select B

`pub fn edgcntb_en(&mut self) -> EDGCNTB_EN_W`[src]

Bit 7 - Edge Counter B Enable

`pub fn cfbwm(&mut self) -> CFBWM_W`[src]

Bits 8:9 - Capture B FIFOs Water Mark

`impl W<u16, Reg<u16, _SMCAPTCOMPB>>`[src]

`pub fn edgcmpb(&mut self) -> EDGCMPB_W`[src]

Bits 0:7 - Edge Compare B

`impl W<u16, Reg<u16, _SMCAPTCTRLX>>`[src]

`pub fn armx(&mut self) -> ARMX_W`[src]

Bit 0 - Arm X

`pub fn oneshotx(&mut self) -> ONESHOTX_W`[src]

Bit 1 - One Shot Mode Aux

`pub fn edgx0(&mut self) -> EDGX0_W`[src]

Bits 2:3 - Edge X 0

`pub fn edgx1(&mut self) -> EDGX1_W`[src]

Bits 4:5 - Edge X 1

`pub fn inp_selx(&mut self) -> INP_SELX_W`[src]

Bit 6 - Input Select X

`pub fn edgcntx_en(&mut self) -> EDGCNTX_EN_W`[src]

Bit 7 - Edge Counter X Enable

`pub fn cfxwm(&mut self) -> CFXWM_W`[src]

Bits 8:9 - Capture X FIFOs Water Mark

`impl W<u16, Reg<u16, _SMCAPTCOMPX>>`[src]

`pub fn edgcmpx(&mut self) -> EDGCMPX_W`[src]

Bits 0:7 - Edge Compare X

`impl W<u16, Reg<u16, _OUTEN>>`[src]

`pub fn pwmx_en(&mut self) -> PWMX_EN_W`[src]

Bits 0:3 - PWM_X Output Enables

`pub fn pwmb_en(&mut self) -> PWMB_EN_W`[src]

Bits 4:7 - PWM_B Output Enables

`pub fn pwma_en(&mut self) -> PWMA_EN_W`[src]

Bits 8:11 - PWM_A Output Enables

`impl W<u16, Reg<u16, _MASK>>`[src]

`pub fn maskx(&mut self) -> MASKX_W`[src]

Bits 0:3 - PWM_X Masks

`pub fn maskb(&mut self) -> MASKB_W`[src]

Bits 4:7 - PWM_B Masks

`pub fn maska(&mut self) -> MASKA_W`[src]

Bits 8:11 - PWM_A Masks

`pub fn update_mask(&mut self) -> UPDATE_MASK_W`[src]

Bits 12:15 - Update Mask Bits Immediately

`impl W<u16, Reg<u16, _SWCOUT>>`[src]

`pub fn smout45(&mut self) -> SMOUT45_W`[src]

Bit 0 - Submodule 0 Software Controlled Output 45

`pub fn smout23(&mut self) -> SMOUT23_W`[src]

Bit 1 - Submodule 0 Software Controlled Output 23

`pub fn sm1out45(&mut self) -> SM1OUT45_W`[src]

Bit 2 - Submodule 1 Software Controlled Output 45

`pub fn sm1out23(&mut self) -> SM1OUT23_W`[src]

Bit 3 - Submodule 1 Software Controlled Output 23

`pub fn sm2out45(&mut self) -> SM2OUT45_W`[src]

Bit 4 - Submodule 2 Software Controlled Output 45

`pub fn sm2out23(&mut self) -> SM2OUT23_W`[src]

Bit 5 - Submodule 2 Software Controlled Output 23

`pub fn sm3out45(&mut self) -> SM3OUT45_W`[src]

Bit 6 - Submodule 3 Software Controlled Output 45

`pub fn sm3out23(&mut self) -> SM3OUT23_W`[src]

Bit 7 - Submodule 3 Software Controlled Output 23

`impl W<u16, Reg<u16, _DTSRCSEL>>`[src]

`pub fn smsel45(&mut self) -> SMSEL45_W`[src]

Bits 0:1 - Submodule 0 PWM45 Control Select

`pub fn smsel23(&mut self) -> SMSEL23_W`[src]

Bits 2:3 - Submodule 0 PWM23 Control Select

`pub fn sm1sel45(&mut self) -> SM1SEL45_W`[src]

Bits 4:5 - Submodule 1 PWM45 Control Select

`pub fn sm1sel23(&mut self) -> SM1SEL23_W`[src]

Bits 6:7 - Submodule 1 PWM23 Control Select

`pub fn sm2sel45(&mut self) -> SM2SEL45_W`[src]

Bits 8:9 - Submodule 2 PWM45 Control Select

`pub fn sm2sel23(&mut self) -> SM2SEL23_W`[src]

Bits 10:11 - Submodule 2 PWM23 Control Select

`pub fn sm3sel45(&mut self) -> SM3SEL45_W`[src]

Bits 12:13 - Submodule 3 PWM45 Control Select

`pub fn sm3sel23(&mut self) -> SM3SEL23_W`[src]

Bits 14:15 - Submodule 3 PWM23 Control Select

`impl W<u16, Reg<u16, _MCTRL>>`[src]

`pub fn ldok(&mut self) -> LDOK_W`[src]

Bits 0:3 - Load Okay

`pub fn cldok(&mut self) -> CLDOK_W`[src]

Bits 4:7 - Clear Load Okay

`pub fn run(&mut self) -> RUN_W`[src]

Bits 8:11 - Run

`pub fn ipol(&mut self) -> IPOL_W`[src]

Bits 12:15 - Current Polarity

`impl W<u16, Reg<u16, _MCTRL2>>`[src]

`pub fn monpll(&mut self) -> MONPLL_W`[src]

Bits 0:1 - Monitor PLL State

`impl W<u16, Reg<u16, _FCTRL0>>`[src]

`pub fn fie(&mut self) -> FIE_W`[src]

Bits 0:3 - Fault Interrupt Enables

`pub fn fsafe(&mut self) -> FSAFE_W`[src]

Bits 4:7 - Fault Safety Mode

`pub fn fauto(&mut self) -> FAUTO_W`[src]

Bits 8:11 - Automatic Fault Clearing

`pub fn flvl(&mut self) -> FLVL_W`[src]

Bits 12:15 - Fault Level

`impl W<u16, Reg<u16, _FSTS0>>`[src]

`pub fn fflag(&mut self) -> FFLAG_W`[src]

Bits 0:3 - Fault Flags

`pub fn ffull(&mut self) -> FFULL_W`[src]

Bits 4:7 - Full Cycle

`pub fn fhalf(&mut self) -> FHALF_W`[src]

Bits 12:15 - Half Cycle Fault Recovery

`impl W<u16, Reg<u16, _FFILT0>>`[src]

`pub fn filt_per(&mut self) -> FILT_PER_W`[src]

Bits 0:7 - Fault Filter Period

`pub fn filt_cnt(&mut self) -> FILT_CNT_W`[src]

Bits 8:10 - Fault Filter Count

`pub fn gstr(&mut self) -> GSTR_W`[src]

Bit 15 - Fault Glitch Stretch Enable

`impl W<u16, Reg<u16, _FTST0>>`[src]

`pub fn ftest(&mut self) -> FTEST_W`[src]

Bit 0 - Fault Test

`impl W<u16, Reg<u16, _FCTRL20>>`[src]

`pub fn nocomb(&mut self) -> NOCOMB_W`[src]

Bits 0:3 - No Combinational Path From Fault Input To PWM Output

Auto Trait Implementations

`impl<U, REG> Send for W<U, REG> where REG: Send, U: Send,`

`impl<U, REG> Sync for W<U, REG> where REG: Sync, U: Sync,`

`impl<U, REG> Unpin for W<U, REG> where REG: Unpin, U: Unpin,`

Blanket Implementations

`impl<T> Any for T where T: 'static + ?Sized,` [src]

`fn type_id(&self) -> TypeId`[src]

`impl<T> Borrow<T> for T where T: ?Sized,` [src]

`fn borrow(&self) -> &T`[src]

`impl<T> BorrowMut<T> for T where T: ?Sized,` [src]

`fn borrow_mut(&mut self) -> &mut T`[src]

`impl<T> From<T> for T`[src]

`fn from(t: T) -> T`[src]

`impl<T, U> Into for T where U: From<T>,` [src]

`fn into(self) -> U`[src]

`impl<T, U> TryFrom for T where U: Into<T>,` [src]

`type Error = Infallible`

The type returned in the event of a conversion error.

`fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>`[src]

`impl<T, U> TryInto for T where U: TryFrom<T>,` [src]

`type Error = >::Error`

The type returned in the event of a conversion error.

[−][src]Struct imxrt1062_pwm1::W

Methods

impl<U, REG> W<U, REG>[src]

pub unsafe fn bits(&mut self, bits: U) -> &mut Self[src]

impl W<u16, Reg<u16, _SMINIT>>[src]

pub fn init(&mut self) -> INIT_W[src]

impl W<u16, Reg<u16, _SMCTRL2>>[src]

pub fn clk_sel(&mut self) -> CLK_SEL_W[src]

pub fn reload_sel(&mut self) -> RELOAD_SEL_W[src]

pub fn force_sel(&mut self) -> FORCE_SEL_W[src]

pub fn force(&mut self) -> FORCE_W[src]

pub fn frcen(&mut self) -> FRCEN_W[src]

pub fn init_sel(&mut self) -> INIT_SEL_W[src]

pub fn pwmx_init(&mut self) -> PWMX_INIT_W[src]

pub fn pwm45_init(&mut self) -> PWM45_INIT_W[src]

pub fn pwm23_init(&mut self) -> PWM23_INIT_W[src]

pub fn indep(&mut self) -> INDEP_W[src]

pub fn waiten(&mut self) -> WAITEN_W[src]

pub fn dbgen(&mut self) -> DBGEN_W[src]

impl W<u16, Reg<u16, _SMCTRL>>[src]

pub fn dblen(&mut self) -> DBLEN_W[src]

pub fn dblx(&mut self) -> DBLX_W[src]

pub fn ldmod(&mut self) -> LDMOD_W[src]

pub fn split(&mut self) -> SPLIT_W[src]

pub fn prsc(&mut self) -> PRSC_W[src]

pub fn compmode(&mut self) -> COMPMODE_W[src]

pub fn full(&mut self) -> FULL_W[src]

pub fn half(&mut self) -> HALF_W[src]

pub fn ldfq(&mut self) -> LDFQ_W[src]

impl W<u16, Reg<u16, _SMVAL0>>[src]

pub fn val0(&mut self) -> VAL0_W[src]

impl W<u16, Reg<u16, _SMFRACVAL1>>[src]

pub fn fracval1(&mut self) -> FRACVAL1_W[src]

impl W<u16, Reg<u16, _SMVAL1>>[src]

pub fn val1(&mut self) -> VAL1_W[src]

impl W<u16, Reg<u16, _SMFRACVAL2>>[src]

pub fn fracval2(&mut self) -> FRACVAL2_W[src]

impl W<u16, Reg<u16, _SMVAL2>>[src]

pub fn val2(&mut self) -> VAL2_W[src]

impl W<u16, Reg<u16, _SMFRACVAL3>>[src]

pub fn fracval3(&mut self) -> FRACVAL3_W[src]

impl W<u16, Reg<u16, _SMVAL3>>[src]

pub fn val3(&mut self) -> VAL3_W[src]

impl W<u16, Reg<u16, _SMFRACVAL4>>[src]

pub fn fracval4(&mut self) -> FRACVAL4_W[src]

impl W<u16, Reg<u16, _SMVAL4>>[src]

pub fn val4(&mut self) -> VAL4_W[src]

impl W<u16, Reg<u16, _SMFRACVAL5>>[src]

pub fn fracval5(&mut self) -> FRACVAL5_W[src]

impl W<u16, Reg<u16, _SMVAL5>>[src]

pub fn val5(&mut self) -> VAL5_W[src]

impl W<u16, Reg<u16, _SMFRCTRL>>[src]

pub fn frac1_en(&mut self) -> FRAC1_EN_W[src]

pub fn frac23_en(&mut self) -> FRAC23_EN_W[src]

pub fn frac45_en(&mut self) -> FRAC45_EN_W[src]

pub fn frac_pu(&mut self) -> FRAC_PU_W[src]

impl W<u16, Reg<u16, _SMOCTRL>>[src]

pub fn pwmxfs(&mut self) -> PWMXFS_W[src]

pub fn pwmbfs(&mut self) -> PWMBFS_W[src]

pub fn pwmafs(&mut self) -> PWMAFS_W[src]

pub fn polx(&mut self) -> POLX_W[src]

pub fn polb(&mut self) -> POLB_W[src]

pub fn pola(&mut self) -> POLA_W[src]

impl W<u16, Reg<u16, _SMSTS>>[src]

pub fn cmpf(&mut self) -> CMPF_W[src]

pub fn cfx0(&mut self) -> CFX0_W[src]

pub fn cfx1(&mut self) -> CFX1_W[src]

pub fn cfb0(&mut self) -> CFB0_W[src]

pub fn cfb1(&mut self) -> CFB1_W[src]

pub fn cfa0(&mut self) -> CFA0_W[src]

pub fn cfa1(&mut self) -> CFA1_W[src]

pub fn rf(&mut self) -> RF_W[src]

pub fn ref_(&mut self) -> REF_W[src]

impl W<u16, Reg<u16, _SMINTEN>>[src]

pub fn cmpie(&mut self) -> CMPIE_W[src]

pub fn cx0ie(&mut self) -> CX0IE_W[src]

pub fn cx1ie(&mut self) -> CX1IE_W[src]

pub fn cb0ie(&mut self) -> CB0IE_W[src]

pub fn cb1ie(&mut self) -> CB1IE_W[src]

pub fn ca0ie(&mut self) -> CA0IE_W[src]