Struct imxrt1062_lpuart1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _GLOBAL>>

pub fn rst(&mut self) -> RST_W

Bit 1 - Software Reset

impl W<u32, Reg<u32, _PINCFG>>

pub fn trgsel(&mut self) -> TRGSEL_W

Bits 0:1 - Trigger Select

impl W<u32, Reg<u32, _BAUD>>

pub fn sbr(&mut self) -> SBR_W

Bits 0:12 - Baud Rate Modulo Divisor.

pub fn sbns(&mut self) -> SBNS_W

Bit 13 - Stop Bit Number Select

pub fn rxedgie(&mut self) -> RXEDGIE_W

Bit 14 - RX Input Active Edge Interrupt Enable

pub fn lbkdie(&mut self) -> LBKDIE_W

Bit 15 - LIN Break Detect Interrupt Enable

pub fn resyncdis(&mut self) -> RESYNCDIS_W

Bit 16 - Resynchronization Disable

pub fn bothedge(&mut self) -> BOTHEDGE_W

Bit 17 - Both Edge Sampling

pub fn matcfg(&mut self) -> MATCFG_W

Bits 18:19 - Match Configuration

pub fn ridmae(&mut self) -> RIDMAE_W

Bit 20 - Receiver Idle DMA Enable

pub fn rdmae(&mut self) -> RDMAE_W

Bit 21 - Receiver Full DMA Enable

pub fn tdmae(&mut self) -> TDMAE_W

Bit 23 - Transmitter DMA Enable

pub fn osr(&mut self) -> OSR_W

Bits 24:28 - Oversampling Ratio

pub fn m10(&mut self) -> M10_W

Bit 29 - 10-bit Mode select

pub fn maen2(&mut self) -> MAEN2_W

Bit 30 - Match Address Mode Enable 2

pub fn maen1(&mut self) -> MAEN1_W

Bit 31 - Match Address Mode Enable 1

impl W<u32, Reg<u32, _STAT>>

pub fn ma2f(&mut self) -> MA2F_W

Bit 14 - Match 2 Flag

pub fn ma1f(&mut self) -> MA1F_W

Bit 15 - Match 1 Flag

pub fn pf(&mut self) -> PF_W

Bit 16 - Parity Error Flag

pub fn fe(&mut self) -> FE_W

Bit 17 - Framing Error Flag

pub fn nf(&mut self) -> NF_W

Bit 18 - Noise Flag

pub fn or(&mut self) -> OR_W

Bit 19 - Receiver Overrun Flag

pub fn idle(&mut self) -> IDLE_W

Bit 20 - Idle Line Flag

pub fn lbkde(&mut self) -> LBKDE_W

Bit 25 - LIN Break Detection Enable

pub fn brk13(&mut self) -> BRK13_W

Bit 26 - Break Character Generation Length

pub fn rwuid(&mut self) -> RWUID_W

Bit 27 - Receive Wake Up Idle Detect

pub fn rxinv(&mut self) -> RXINV_W

Bit 28 - Receive Data Inversion

pub fn msbf(&mut self) -> MSBF_W

Bit 29 - MSB First

pub fn rxedgif(&mut self) -> RXEDGIF_W

Bit 30 - RXD Pin Active Edge Interrupt Flag

pub fn lbkdif(&mut self) -> LBKDIF_W

Bit 31 - LIN Break Detect Interrupt Flag

impl W<u32, Reg<u32, _CTRL>>

pub fn pt(&mut self) -> PT_W

Bit 0 - Parity Type

pub fn pe(&mut self) -> PE_W

Bit 1 - Parity Enable

pub fn ilt(&mut self) -> ILT_W

Bit 2 - Idle Line Type Select

pub fn wake(&mut self) -> WAKE_W

Bit 3 - Receiver Wakeup Method Select

pub fn m(&mut self) -> M_W

Bit 4 - 9-Bit or 8-Bit Mode Select

pub fn rsrc(&mut self) -> RSRC_W

Bit 5 - Receiver Source Select

pub fn dozeen(&mut self) -> DOZEEN_W

Bit 6 - Doze Enable

pub fn loops(&mut self) -> LOOPS_W

Bit 7 - Loop Mode Select

pub fn idlecfg(&mut self) -> IDLECFG_W

Bits 8:10 - Idle Configuration

pub fn m7(&mut self) -> M7_W

Bit 11 - 7-Bit Mode Select

pub fn ma2ie(&mut self) -> MA2IE_W

Bit 14 - Match 2 Interrupt Enable

pub fn ma1ie(&mut self) -> MA1IE_W

Bit 15 - Match 1 Interrupt Enable

pub fn sbk(&mut self) -> SBK_W

Bit 16 - Send Break

pub fn rwu(&mut self) -> RWU_W

Bit 17 - Receiver Wakeup Control

pub fn re(&mut self) -> RE_W

Bit 18 - Receiver Enable

pub fn te(&mut self) -> TE_W

Bit 19 - Transmitter Enable

pub fn ilie(&mut self) -> ILIE_W

Bit 20 - Idle Line Interrupt Enable

pub fn rie(&mut self) -> RIE_W

Bit 21 - Receiver Interrupt Enable

pub fn tcie(&mut self) -> TCIE_W

Bit 22 - Transmission Complete Interrupt Enable for

pub fn tie(&mut self) -> TIE_W

Bit 23 - Transmit Interrupt Enable

pub fn peie(&mut self) -> PEIE_W

Bit 24 - Parity Error Interrupt Enable

pub fn feie(&mut self) -> FEIE_W

Bit 25 - Framing Error Interrupt Enable

pub fn neie(&mut self) -> NEIE_W

Bit 26 - Noise Error Interrupt Enable

pub fn orie(&mut self) -> ORIE_W

Bit 27 - Overrun Interrupt Enable

pub fn txinv(&mut self) -> TXINV_W

Bit 28 - Transmit Data Inversion

pub fn txdir(&mut self) -> TXDIR_W

Bit 29 - TXD Pin Direction in Single-Wire Mode

pub fn r9t8(&mut self) -> R9T8_W

Bit 30 - Receive Bit 9 / Transmit Bit 8

pub fn r8t9(&mut self) -> R8T9_W

Bit 31 - Receive Bit 8 / Transmit Bit 9

impl W<u32, Reg<u32, _DATA>>

pub fn r0t0(&mut self) -> R0T0_W

Bit 0 - R0T0

pub fn r1t1(&mut self) -> R1T1_W

Bit 1 - R1T1

pub fn r2t2(&mut self) -> R2T2_W

Bit 2 - R2T2

pub fn r3t3(&mut self) -> R3T3_W

Bit 3 - R3T3

pub fn r4t4(&mut self) -> R4T4_W

Bit 4 - R4T4

pub fn r5t5(&mut self) -> R5T5_W

Bit 5 - R5T5

pub fn r6t6(&mut self) -> R6T6_W

Bit 6 - R6T6

pub fn r7t7(&mut self) -> R7T7_W

Bit 7 - R7T7

pub fn r8t8(&mut self) -> R8T8_W

Bit 8 - R8T8

pub fn r9t9(&mut self) -> R9T9_W

Bit 9 - R9T9

pub fn fretsc(&mut self) -> FRETSC_W

Bit 13 - Frame Error / Transmit Special Character

impl W<u32, Reg<u32, _MATCH>>

pub fn ma1(&mut self) -> MA1_W

Bits 0:9 - Match Address 1

pub fn ma2(&mut self) -> MA2_W

Bits 16:25 - Match Address 2

impl W<u32, Reg<u32, _MODIR>>

pub fn txctse(&mut self) -> TXCTSE_W

Bit 0 - Transmitter clear-to-send enable

pub fn txrtse(&mut self) -> TXRTSE_W

Bit 1 - Transmitter request-to-send enable

pub fn txrtspol(&mut self) -> TXRTSPOL_W

Bit 2 - Transmitter request-to-send polarity

pub fn rxrtse(&mut self) -> RXRTSE_W

Bit 3 - Receiver request-to-send enable

pub fn txctsc(&mut self) -> TXCTSC_W

Bit 4 - Transmit CTS Configuration

pub fn txctssrc(&mut self) -> TXCTSSRC_W

Bit 5 - Transmit CTS Source

pub fn rtswater(&mut self) -> RTSWATER_W

Bits 8:9 - Receive RTS Configuration

pub fn tnp(&mut self) -> TNP_W

Bits 16:17 - Transmitter narrow pulse

pub fn iren(&mut self) -> IREN_W

Bit 18 - Infrared enable

impl W<u32, Reg<u32, _FIFO>>

pub fn rxfe(&mut self) -> RXFE_W

Bit 3 - Receive FIFO Enable

pub fn txfe(&mut self) -> TXFE_W

Bit 7 - Transmit FIFO Enable

pub fn rxufe(&mut self) -> RXUFE_W

Bit 8 - Receive FIFO Underflow Interrupt Enable

pub fn txofe(&mut self) -> TXOFE_W

Bit 9 - Transmit FIFO Overflow Interrupt Enable

pub fn rxiden(&mut self) -> RXIDEN_W

Bits 10:12 - Receiver Idle Empty Enable

pub fn rxflush(&mut self) -> RXFLUSH_W

Bit 14 - Receive FIFO/Buffer Flush

pub fn txflush(&mut self) -> TXFLUSH_W

Bit 15 - Transmit FIFO/Buffer Flush

pub fn rxuf(&mut self) -> RXUF_W

Bit 16 - Receiver Buffer Underflow Flag

pub fn txof(&mut self) -> TXOF_W

Bit 17 - Transmitter Buffer Overflow Flag

impl W<u32, Reg<u32, _WATER>>

pub fn txwater(&mut self) -> TXWATER_W

Bits 0:1 - Transmit Watermark

pub fn rxwater(&mut self) -> RXWATER_W

Bits 16:17 - Receive Watermark