[−][src]Crate imxrt1062_lpspi1
Modules
| ccr | Clock Configuration Register |
| cfgr0 | Configuration Register 0 |
| cfgr1 | Configuration Register 1 |
| cr | Control Register |
| der | DMA Enable Register |
| dmr0 | Data Match Register 0 |
| dmr1 | Data Match Register 1 |
| fcr | FIFO Control Register |
| fsr | FIFO Status Register |
| ier | Interrupt Enable Register |
| param | Parameter Register |
| rdr | Receive Data Register |
| rsr | Receive Status Register |
| sr | Status Register |
| tcr | Transmit Command Register |
| tdr | Transmit Data Register |
| verid | Version ID Register |
Structs
| R | Register/field reader |
| Reg | This structure provides volatile access to register |
| RegisterBlock | Register block |
| W | Register writer |
Enums
| Variant | Used if enumerated values cover not the whole range |
Traits
| Readable | This trait shows that register has |
| ResetValue | Reset value of the register |
| Writable | This trait shows that register has |
Type Definitions
| CCR | Clock Configuration Register |
| CFGR0 | Configuration Register 0 |
| CFGR1 | Configuration Register 1 |
| CR | Control Register |
| DER | DMA Enable Register |
| DMR0 | Data Match Register 0 |
| DMR1 | Data Match Register 1 |
| FCR | FIFO Control Register |
| FSR | FIFO Status Register |
| IER | Interrupt Enable Register |
| PARAM | Parameter Register |
| RDR | Receive Data Register |
| RSR | Receive Status Register |
| SR | Status Register |
| TCR | Transmit Command Register |
| TDR | Transmit Data Register |
| VERID | Version ID Register |