[−][src]Crate imxrt1062_lpi2c1
Modules
| mccr0 | Master Clock Configuration Register 0 |
| mccr1 | Master Clock Configuration Register 1 |
| mcfgr0 | Master Configuration Register 0 |
| mcfgr1 | Master Configuration Register 1 |
| mcfgr2 | Master Configuration Register 2 |
| mcfgr3 | Master Configuration Register 3 |
| mcr | Master Control Register |
| mder | Master DMA Enable Register |
| mdmr | Master Data Match Register |
| mfcr | Master FIFO Control Register |
| mfsr | Master FIFO Status Register |
| mier | Master Interrupt Enable Register |
| mrdr | Master Receive Data Register |
| msr | Master Status Register |
| mtdr | Master Transmit Data Register |
| param | Parameter Register |
| samr | Slave Address Match Register |
| sasr | Slave Address Status Register |
| scfgr1 | Slave Configuration Register 1 |
| scfgr2 | Slave Configuration Register 2 |
| scr | Slave Control Register |
| sder | Slave DMA Enable Register |
| sier | Slave Interrupt Enable Register |
| srdr | Slave Receive Data Register |
| ssr | Slave Status Register |
| star | Slave Transmit ACK Register |
| stdr | Slave Transmit Data Register |
| verid | Version ID Register |
Structs
| R | Register/field reader |
| Reg | This structure provides volatile access to register |
| RegisterBlock | Register block |
| W | Register writer |
Enums
| Variant | Used if enumerated values cover not the whole range |
Traits
| Readable | This trait shows that register has |
| ResetValue | Reset value of the register |
| Writable | This trait shows that register has |
Type Definitions
| MCCR0 | Master Clock Configuration Register 0 |
| MCCR1 | Master Clock Configuration Register 1 |
| MCFGR0 | Master Configuration Register 0 |
| MCFGR1 | Master Configuration Register 1 |
| MCFGR2 | Master Configuration Register 2 |
| MCFGR3 | Master Configuration Register 3 |
| MCR | Master Control Register |
| MDER | Master DMA Enable Register |
| MDMR | Master Data Match Register |
| MFCR | Master FIFO Control Register |
| MFSR | Master FIFO Status Register |
| MIER | Master Interrupt Enable Register |
| MRDR | Master Receive Data Register |
| MSR | Master Status Register |
| MTDR | Master Transmit Data Register |
| PARAM | Parameter Register |
| SAMR | Slave Address Match Register |
| SASR | Slave Address Status Register |
| SCFGR1 | Slave Configuration Register 1 |
| SCFGR2 | Slave Configuration Register 2 |
| SCR | Slave Control Register |
| SDER | Slave DMA Enable Register |
| SIER | Slave Interrupt Enable Register |
| SRDR | Slave Receive Data Register |
| SSR | Slave Status Register |
| STAR | Slave Transmit ACK Register |
| STDR | Slave Transmit Data Register |
| VERID | Version ID Register |