[][src]Struct imxrt1062_dcdc::R

pub struct R<U, T> { /* fields omitted */ }

Register/field reader

Result of the read method of a register. Also it can be used in the modify method

Methods

impl<U, T> R<U, T> where
    U: Copy
[src]

pub fn bits(&self) -> U[src]

Read raw bits from register/field

impl<FI> R<bool, FI>[src]

pub fn bit(&self) -> bool[src]

Value of the field as raw bits

pub fn bit_is_clear(&self) -> bool[src]

Returns true if the bit is clear (0)

pub fn bit_is_set(&self) -> bool[src]

Returns true if the bit is set (1)

impl R<u32, Reg<u32, _REG0>>[src]

pub fn pwd_zcd(&self) -> PWD_ZCD_R[src]

Bit 0 - power down the zero cross detection function for discontinuous conductor mode

pub fn disable_auto_clk_switch(&self) -> DISABLE_AUTO_CLK_SWITCH_R[src]

Bit 1 - Disable automatic clock switch from internal osc to xtal clock.

pub fn sel_clk(&self) -> SEL_CLK_R[src]

Bit 2 - select 24 MHz Crystal clock for DCDC, when dcdc_disable_auto_clk_switch is set.

pub fn pwd_osc_int(&self) -> PWD_OSC_INT_R[src]

Bit 3 - Power down internal osc. Only set this bit, when 24 MHz crystal osc is available

pub fn pwd_cur_sns_cmp(&self) -> PWD_CUR_SNS_CMP_R[src]

Bit 4 - The power down signal of the current detector.

pub fn cur_sns_thrsh(&self) -> CUR_SNS_THRSH_R[src]

Bits 5:7 - Set the threshold of current detector, if the peak current of the inductor exceeds the threshold, the current detector will assert

pub fn pwd_overcur_det(&self) -> PWD_OVERCUR_DET_R[src]

Bit 8 - power down overcurrent detection comparator

pub fn overcur_trig_adj(&self) -> OVERCUR_TRIG_ADJ_R[src]

Bits 9:10 - The threshold of over current detection in run mode and power save mode: run mode power save mode 0x0 1 A 0

pub fn pwd_cmp_batt_det(&self) -> PWD_CMP_BATT_DET_R[src]

Bit 11 - set to "1" to power down the low voltage detection comparator

pub fn adj_poslimit_buck(&self) -> ADJ_POSLIMIT_BUCK_R[src]

Bits 12:15 - adjust value to poslimit_buck register

pub fn en_lp_overload_sns(&self) -> EN_LP_OVERLOAD_SNS_R[src]

Bit 16 - enable the overload detection in power save mode, if current is larger than the overloading threshold (typical value is 50 mA), DCDC will switch to the run mode automatically

pub fn pwd_high_volt_det(&self) -> PWD_HIGH_VOLT_DET_R[src]

Bit 17 - power down overvoltage detection comparator

pub fn lp_overload_thrsh(&self) -> LP_OVERLOAD_THRSH_R[src]

Bits 18:19 - the threshold of the counting number of charging times during the period that lp_overload_freq_sel sets in power save mode

pub fn lp_overload_freq_sel(&self) -> LP_OVERLOAD_FREQ_SEL_R[src]

Bit 20 - the period of counting the charging times in power save mode 0: eight 32k cycle 1: sixteen 32k cycle

pub fn lp_high_hys(&self) -> LP_HIGH_HYS_R[src]

Bit 21 - Adjust hysteretic value in low power from 12.5mV to 25mV

pub fn pwd_cmp_offset(&self) -> PWD_CMP_OFFSET_R[src]

Bit 26 - power down output range comparator

pub fn xtalok_disable(&self) -> XTALOK_DISABLE_R[src]

Bit 27 - 1'b1: Disable xtalok detection circuit 1'b0: Enable xtalok detection circuit

pub fn current_alert_reset(&self) -> CURRENT_ALERT_RESET_R[src]

Bit 28 - reset current alert signal

pub fn xtal_24m_ok(&self) -> XTAL_24M_OK_R[src]

Bit 29 - set to 1 to switch internal ring osc to xtal 24M

pub fn sts_dc_ok(&self) -> STS_DC_OK_R[src]

Bit 31 - Status register to indicate DCDC status. 1'b1: DCDC already settled 1'b0: DCDC is settling

impl R<u32, Reg<u32, _REG1>>[src]

pub fn reg_fbk_sel(&self) -> REG_FBK_SEL_R[src]

Bits 7:8 - select the feedback point of the internal regulator

pub fn reg_rload_sw(&self) -> REG_RLOAD_SW_R[src]

Bit 9 - control the load resistor of the internal regulator of DCDC, the load resistor is connected as default "1", and need set to "0" to disconnect the load resistor

pub fn lp_cmp_isrc_sel(&self) -> LP_CMP_ISRC_SEL_R[src]

Bits 12:13 - set the current bias of low power comparator 0x0: 50 nA 0x1: 100 nA 0x2: 200 nA 0x3: 400 nA

pub fn loopctrl_hst_thresh(&self) -> LOOPCTRL_HST_THRESH_R[src]

Bit 21 - increase the threshold detection for common mode analog comparator

pub fn loopctrl_en_hyst(&self) -> LOOPCTRL_EN_HYST_R[src]

Bit 23 - Enable hysteresis in switching converter common mode analog comparators

pub fn vbg_trim(&self) -> VBG_TRIM_R[src]

Bits 24:28 - trim bandgap voltage

impl R<u32, Reg<u32, _REG2>>[src]

pub fn loopctrl_dc_c(&self) -> LOOPCTRL_DC_C_R[src]

Bits 0:1 - Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter, and can be used to optimize efficiency and loop response

pub fn loopctrl_dc_r(&self) -> LOOPCTRL_DC_R_R[src]

Bits 2:5 - Magnitude of proportional control parameter in the switching DC-DC converter control loop.

pub fn loopctrl_dc_ff(&self) -> LOOPCTRL_DC_FF_R[src]

Bits 6:8 - Two's complement feed forward step in duty cycle in the switching DC-DC converter

pub fn loopctrl_en_rcscale(&self) -> LOOPCTRL_EN_RCSCALE_R[src]

Bits 9:11 - Enable analog circuit of DC-DC converter to respond faster under transient load conditions.

pub fn loopctrl_rcscale_thrsh(&self) -> LOOPCTRL_RCSCALE_THRSH_R[src]

Bit 12 - Increase the threshold detection for RC scale circuit.

pub fn loopctrl_hyst_sign(&self) -> LOOPCTRL_HYST_SIGN_R[src]

Bit 13 - Invert the sign of the hysteresis in DC-DC analog comparators.

pub fn disable_pulse_skip(&self) -> DISABLE_PULSE_SKIP_R[src]

Bit 27 - Set to "0" : stop charging if the duty cycle is lower than what set by dcdc_neglimit_in

pub fn dcm_set_ctrl(&self) -> DCM_SET_CTRL_R[src]

Bit 28 - Set high to improve the transition from heavy load to light load

impl R<u32, Reg<u32, _REG3>>[src]

pub fn trg(&self) -> TRG_R[src]

Bits 0:4 - Target value of VDD_SOC, 25 mV each step 0x0: 0.8V 0xE: 1.15V 0x1F:1.575V

pub fn target_lp(&self) -> TARGET_LP_R[src]

Bits 8:10 - Target value of standby (low power) mode 0x0: 0

pub fn minpwr_dc_halfclk(&self) -> MINPWR_DC_HALFCLK_R[src]

Bit 24 - Set DCDC clock to half freqeuncy for continuous mode

pub fn misc_delay_timing(&self) -> MISC_DELAY_TIMING_R[src]

Bit 27 - Ajust delay to reduce ground noise

pub fn misc_disablefet_logic(&self) -> MISC_DISABLEFET_LOGIC_R[src]

Bit 28 - Reserved

pub fn disable_step(&self) -> DISABLE_STEP_R[src]

Bit 30 - Disable stepping for the output VDD_SOC of DCDC

Trait Implementations

impl<U, T, FI> PartialEq<FI> for R<U, T> where
    U: PartialEq,
    FI: Copy + Into<U>, 
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Auto Trait Implementations

impl<U, T> Send for R<U, T> where
    T: Send,
    U: Send

impl<U, T> Sync for R<U, T> where
    T: Sync,
    U: Sync

impl<U, T> Unpin for R<U, T> where
    T: Unpin,
    U: Unpin

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
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impl<T> Borrow<T> for T where
    T: ?Sized
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impl<T> BorrowMut<T> for T where
    T: ?Sized
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impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
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impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
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type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.