[−][src]Module imxrt1062_ccm_analog::misc2

Miscellaneous Register 2

Structs

AUDIO_DIV_LSB_W	Write proxy for field `AUDIO_DIV_LSB`
AUDIO_DIV_MSB_W	Write proxy for field `AUDIO_DIV_MSB`
PLL3_DISABLE_W	Write proxy for field `PLL3_DISABLE`
REG0_ENABLE_BO_W	Write proxy for field `REG0_ENABLE_BO`
REG0_STEP_TIME_W	Write proxy for field `REG0_STEP_TIME`
REG1_ENABLE_BO_W	Write proxy for field `REG1_ENABLE_BO`
REG1_STEP_TIME_W	Write proxy for field `REG1_STEP_TIME`
REG2_ENABLE_BO_W	Write proxy for field `REG2_ENABLE_BO`
REG2_STEP_TIME_W	Write proxy for field `REG2_STEP_TIME`
VIDEO_DIV_W	Write proxy for field `VIDEO_DIV`

AUDIO_DIV_LSB_A	LSB of Post-divider for Audio PLL
AUDIO_DIV_MSB_A	MSB of Post-divider for Audio PLL
PLL3_DISABLE_A	When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode
REG0_BO_OFFSET_A	This field defines the brown out voltage offset for the CORE power domain
REG0_BO_STATUS_A	Reg0 brownout status bit.Not related to CCM. See Power Management Unit (PMU)
REG0_STEP_TIME_A	Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)
REG1_BO_OFFSET_A	This field defines the brown out voltage offset for the xPU power domain
REG1_BO_STATUS_A	Reg1 brownout status bit. Not related to CCM. See Power Management Unit (PMU)
REG1_STEP_TIME_A	Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)
REG2_BO_OFFSET_A	This field defines the brown out voltage offset for the xPU power domain
REG2_STEP_TIME_A	Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)
VIDEO_DIV_A	Post-divider for video