[−][src]Module imxrt1062_can1::mcr
Module Configuration Register
Structs
| AEN_W | Write proxy for field |
| FRZ_W | Write proxy for field |
| HALT_W | Write proxy for field |
| IDAM_W | Write proxy for field |
| IRMQ_W | Write proxy for field |
| LPRIOEN_W | Write proxy for field |
| MAXMB_W | Write proxy for field |
| MDIS_W | Write proxy for field |
| RFEN_W | Write proxy for field |
| SLFWAK_W | Write proxy for field |
| SOFTRST_W | Write proxy for field |
| SRXDIS_W | Write proxy for field |
| SUPV_W | Write proxy for field |
| WAKMSK_W | Write proxy for field |
| WAKSRC_W | Write proxy for field |
| WRNEN_W | Write proxy for field |
Enums
| AEN_A | This bit is supplied for backwards compatibility reasons |
| FRZACK_A | This read-only bit indicates that FLEXCAN is in Freeze Mode and its prescaler is stopped |
| FRZ_A | The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level |
| HALT_A | Assertion of this bit puts the FLEXCAN module into Freeze Mode |
| IDAM_A | This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below |
| IRMQ_A | This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK |
| LPMACK_A | This read-only bit indicates that FLEXCAN is either in Disable Mode or Stop Mode |
| LPRIOEN_A | This bit is provided for backwards compatibility reasons |
| MDIS_A | This bit controls whether FLEXCAN is enabled or not |
| NOTRDY_A | This read-only bit indicates that FLEXCAN is either in Disable Mode, Stop Mode or Freeze Mode |
| RFEN_A | This bit controls whether the Rx FIFO feature is enabled or not |
| SLFWAK_A | This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode |
| SOFTRST_A | When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers |
| SRXDIS_A | This bit defines whether FlexCAN is allowed to receive frames transmitted by itself |
| SUPV_A | This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode |
| WAKMSK_A | This bit enables the Wake Up Interrupt generation. |
| WAKSRC_A | This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up |
| WRNEN_A | When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register |
Type Definitions
| AEN_R | Reader of field |
| FRZACK_R | Reader of field |
| FRZ_R | Reader of field |
| HALT_R | Reader of field |
| IDAM_R | Reader of field |
| IRMQ_R | Reader of field |
| LPMACK_R | Reader of field |
| LPRIOEN_R | Reader of field |
| MAXMB_R | Reader of field |
| MDIS_R | Reader of field |
| NOTRDY_R | Reader of field |
| R | Reader of register MCR |
| RFEN_R | Reader of field |
| SLFWAK_R | Reader of field |
| SOFTRST_R | Reader of field |
| SRXDIS_R | Reader of field |
| SUPV_R | Reader of field |
| W | Writer for register MCR |
| WAKMSK_R | Reader of field |
| WAKSRC_R | Reader of field |
| WRNEN_R | Reader of field |