Module imxrt_ral::ccm::CCGR5

CCM Clock Gating Register 5

Modules

• CG0
  rom clock (rom_clk_enable)
• CG1
  flexio1 clock (flexio1_clk_enable)
• CG2
  wdog3 clock (wdog3_clk_enable)
• CG3
  dma clock (dma_clk_enable)
• CG4
  kpp clock (kpp_clk_enable)
• CG5
  wdog2 clock (wdog2_clk_enable)
• CG6
  Reserved
• CG7
  spdif clock (spdif_clk_enable)
• CG8
  Reserved
• CG9
  sai1 clock (sai1_clk_enable)
• CG10
  Reserved
• CG11
  sai3 clock (sai3_clk_enable)
• CG12
  lpuart1 clock (lpuart1_clk_enable)
• CG13
  Reserved
• CG14
  snvs_hp clock (snvs_hp_clk_enable)
• CG15
  snvs_lp clock (snvs_lp_clk_enable)