Expand description

Analog Audio PLL control Register

Modules

  • Bypass the PLL.
  • Determines the bypass source.
  • This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.
  • Enable PLL output
  • 1 - PLL is currently locked. 0 - PLL is not currently locked.
  • These bits implement a divider after the PLL, but before the enable and bypass mux.
  • Powers down the PLL.