Module imxrt_ral::ccm_analog::PFD_528

Expand description

528MHz Clock (PLL2) Phase Fractional Divider Control Register

Modules

PFD0_CLKGATE
If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)
PFD0_FRAC
This field controls the fractional divide value
PFD0_STABLE
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
PFD1_CLKGATE
IO Clock Gate
PFD1_FRAC
This field controls the fractional divide value
PFD1_STABLE
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
PFD2_CLKGATE
IO Clock Gate
PFD2_FRAC
This field controls the fractional divide value
PFD2_STABLE
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code
PFD3_CLKGATE
IO Clock Gate
PFD3_FRAC
This field controls the fractional divide value
PFD3_STABLE
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become stable quickly enough that this field will never need to be used by either device driver or application code