Expand description
General purpose timer.
Features
The GPTs are count-up, wrapping timers that run off of the IPG clock or the crystal oscillator (24MHz). Each GPT has three compare registers, called output comparison registers (OCR). When the counter reaches a value in an OCR, the GPT signals the comparison through status flags. A comparison can generate an interrupt.
GPT modes
The table below summarizes the effects of an output comparison operation when in restart mode, and when in free-running mode. See the subsequent sections for a discussion of the two modes.
| GPT Mode | OCR1 | OCR2 | OCR3 |
|---|---|---|---|
| Restart | Resets the counter to zero | No effect; counter continues incrementing | No effect… |
| Free-running | No effect; counter continues incrementing | No effect … | No effect… |
In summary, OCR1 is special in restart mode, as it will reset the value in the GPT counter.
Select a mode with set_mode().
Restart mode
The GPTs default to ‘restart mode.’ In restart mode, a compare on channel 1 will reset the GPT counter to zero. Compare events on channels 2 and 3 will not reset the GPT counter. If you would rather have the GPT counter continue no matter the comparison event, set the GPT to free-running mode.
Free-running mode
The GPTs may be in free-running mode. When a comparion event occurs in free-running mode, the counter continues to increment, eventually wrapping around. Free-running mode treats all channels as equal; that is, channel 1 is no different than channel 2 or 3.
Reset on enable
Reset on enable is a complementary feature to the two modes. When reset on enable is active, the GPT counter will reset to zero each time the timer is enabled. By default, the counter will restart at whatever value is currently in the counter. The default behavior lets a user ‘pause’ the counter by disabling the GPT. On the other hand, reset on enable lets users reset the counter by disabling and re-enabling the GPT.
The table below summarizes the ‘reset on enable’ behaviors. Use
set_reset_on_enable() to configure
the reset on enable behavior.
| State | Behavior |
|---|---|
false | When the GPT is disabled, it maintains its counter value |
true | When the GPT is disabled, the counter resets to zero |
GPTs and system WAIT / STOP
By default, GPTs do not run when the process is in in wait mode. Use
set_wait_mode_enable(true)
to enable GPTs in wait mode.
If the GPT stops counting in WAIT / STOP system states, the counter freezes its counter. When the processor transitions into RUNNING, the counter increments from its previously-frozen value (provided the GPT was enabled).
Example
These examples do not demonstrate how to configure the GPT clock gates or clock root, PERCLK. To configure PERCLK, see the CCM peripheral clock module.
Create, configure, and wait for ticks to elapse:
use imxrt_ral::gpt::GPT1;
use imxrt_hal::gpt;
let mut gpt = gpt::Gpt::new(unsafe { GPT1::instance() });
gpt.set_clock_source(gpt::ClockSource::HighFrequencyReferenceClock);
gpt.set_divider(16);
gpt.set_mode(gpt::Mode::FreeRunning);
gpt.enable();
// Later...
const OCR: gpt::OutputCompareRegister = gpt::OutputCompareRegister::OCR1;
gpt.clear_elapsed(OCR);
let count = gpt.count();
let ticks_to_wait = gpt.count().wrapping_add(40_000);
gpt.set_output_compare_count(OCR, ticks_to_wait);
while !gpt.is_elapsed(OCR) {}
gpt.clear_elapsed(OCR);TODO
- Input capture. Each GPT can capture the value of the counter when a pin state changes. When the pin state changes, the GPT can generate an interrupt.
- Output generation. When one of the three comparison registers match the counter, the GPT can generate a signal on an output pin.
Structs
- A general purpose timer
Enums
- GPT clock source.
- Possible modes of the GPT.
- An output compare register (OCR).
Type Aliases
- GPT1 alias.
- GPT2 alias.