pub fn restart(ccm_analog: &mut CCM_ANALOG, div_sel: u32)
Expand description
Restart PLL1 with a new divider selection.
PLL1 should not be driving any components when this restart happens. You’re responsible for switching over clocks.
The implementation clamps div_sel
between 54 and 108.
When this function returns, PLL1 is running and stable.