Crate i8051 

i8051

A fast, unsafe-free emulator for the i8051 microcontroller.

The 8051 (a.k.a. the MCS-51) is a 8-bit microcontroller that was very common in the 1980s and 1990s, and is still used in many modern devices.

There are a number of different variants of the 8051, and this crate supports a CPU like the original 8051, but with a zero-flag extension.

The 8051/MCS-51 series has a complex architecture, consisting of:

• A program counter (PC), used to store the address of the next instruction to execute and stored in its own dedicated register on-chip.
• Internal RAM (256 bytes), used for the stack, R0-R7 registers, and general-purpose storage.
• SFRs (Special Function Registers), used for internal peripherals and all registers other than R0-R7 and PC. These include:
  • Ports (P0-P3), used for general-purpose I/O. Ports may be bidirectional and use an output latch for read/write control and special-function control.
  • Timers, for timing and counting.
  • Serial UART(s).
  • Interrupt control.
• XDATA (External Memory), used for off-chip RAM and accessed via MOVX opcodes.
• CODE (External Program Memory), used for off-chip ROM and accessed via MOVC opcodes.

See Mnemonic for a list of all supported instructions.

Modules

breakpoint

Breakpoint support for the i8051 microcontroller.

memory

Various memory mapper implementations for the i8051 microcontroller.

peripheral

Peripheral implementations for the i8051 microcontroller.

sfr

SFR (special-function register) addresses for the i8051 microcontroller.

Structs

Cpu

The 8051 CPU.

DefaultPortMapper

The default port mapper, providing access to all SFRs.

Instruction

An instruction decoded from a sequence of bytes.

Operands

Stack-allocated operand list.

Enums

ControlFlow

How execution proceeds after an instruction.

Flag

Flags available in the PSW register.

Interrupt

Mnemonic

8051 instruction mnemonics.

Operand

Register

A register in the 8051 CPU.

Traits

CpuContext

A context for the CPU. This can be implemented by hand, but is most conveniently implemented using a tuple of (PortMapper, MemoryMapper, MemoryMapper) for ports, xdata, and code.

CpuView

A (mostly) read-only view of the CPU state with the ability to trigger interrupts.

MemoryMapper

A trait to provide memory read/write operations.

PortMapper

A trait to provide port read/write operations.

ReadOnlyMemoryMapper

A trait to provide read-only memory read operations.