Module hpm5361_pac::rdc
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RDC
Modules§
- number of accumulation
- number of accumulation
- accumulate result of i_channel
- accumulate result of q_channel
- scaling for accumulation result
- the interrupt state
- the maximum of acc amplitude
- the minimum of acc amplitude
- the control for edge detection
- amplitude offset setting
- period of excitation
- amplitude scaling for excitation
- trigger in delay timming in soc bus cycle
- excitation signal timming setting
- delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data
- delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data
- input channel selection
- the interrupt mask control
- max value of i_channel
- max value of q_channel
- min value of i_channel
- min value of q_channel
- output channel selection
- pwm dead zone control in clock cycle
- amplitude offset setting
- amplitude scaling for excitation
- rdc control
- delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data
- delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data
- sample value on falling edge of rectify signal
- sample value on falling edge of rectify signal
- sample value on rising edge of rectify signal
- sample value on rising edge of rectify signal
- sample counter of opposite sign with rectify signal
- sample counter of opposite sign with rectify signal
- delay setting in clock cycle for synchronous signal
- delay setting in clock cycle for synchronous signal
- synchronize output signal control
- the offset setting for edge detection of the i_channel
- the offset setting for edge detection of the q_channel
- Configuration for trigger out 0 in clock cycle
- Configuration for trigger out 1 in clock cycle
Structs§
- Register block
Type Aliases§
- acc_cnt_i (rw) register accessor: number of accumulation
- acc_cnt_q (rw) register accessor: number of accumulation
- acc_i (rw) register accessor: accumulate result of i_channel
- acc_q (rw) register accessor: accumulate result of q_channel
- acc_scaling (rw) register accessor: scaling for accumulation result
- adc_int_state (rw) register accessor: the interrupt state
- amp_max (rw) register accessor: the maximum of acc amplitude
- amp_min (rw) register accessor: the minimum of acc amplitude
- edg_det_ctl (rw) register accessor: the control for edge detection
- exc_offset (rw) register accessor: amplitude offset setting
- exc_period (rw) register accessor: period of excitation
- exc_scaling (rw) register accessor: amplitude scaling for excitation
- exc_sync_dly (rw) register accessor: trigger in delay timming in soc bus cycle
- exc_timming (rw) register accessor: excitation signal timming setting
- fall_delay_i (rw) register accessor: delay in clock cycle between excitation synchrnous signal and falling edge of i_channel data
- fall_delay_q (rw) register accessor: delay in clock cycle between excitation synchrnous signal and falling edge of q_channel data
- int_en (rw) register accessor: the interrupt mask control
- in_ctl (rw) register accessor: input channel selection
- max_i (rw) register accessor: max value of i_channel
- max_q (rw) register accessor: max value of q_channel
- min_i (rw) register accessor: min value of i_channel
- min_q (rw) register accessor: min value of q_channel
- out_ctl (rw) register accessor: output channel selection
- pwm_dz (rw) register accessor: pwm dead zone control in clock cycle
- pwm_offset (rw) register accessor: amplitude offset setting
- pwm_scaling (rw) register accessor: amplitude scaling for excitation
- rdc_ctl (rw) register accessor: rdc control
- rise_delay_i (rw) register accessor: delay in clock cycle between excitation synchrnous signal and rising edge of i_channel data
- rise_delay_q (rw) register accessor: delay in clock cycle between excitation synchrnous signal and rising edge of q_channel data
- sample_fall_i (rw) register accessor: sample value on falling edge of rectify signal
- sample_fall_q (rw) register accessor: sample value on falling edge of rectify signal
- sample_rise_i (rw) register accessor: sample value on rising edge of rectify signal
- sample_rise_q (rw) register accessor: sample value on rising edge of rectify signal
- sign_cnt_i (rw) register accessor: sample counter of opposite sign with rectify signal
- sign_cnt_q (rw) register accessor: sample counter of opposite sign with rectify signal
- sync_delay_i (rw) register accessor: delay setting in clock cycle for synchronous signal
- sync_delay_q (rw) register accessor: delay setting in clock cycle for synchronous signal
- sync_out_ctrl (rw) register accessor: synchronize output signal control
- thrs_i (rw) register accessor: the offset setting for edge detection of the i_channel
- thrs_q (rw) register accessor: the offset setting for edge detection of the q_channel
- trig_out0_cfg (rw) register accessor: Configuration for trigger out 0 in clock cycle
- trig_out1_cfg (rw) register accessor: Configuration for trigger out 1 in clock cycle