Module hpm5361_pac::mcan0

MCAN0

Modules

• atb
  actual timebase
• atbh
  actual timebase high
• cccr
  CC control register
• crel
  core release register
• dbtp
  data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set
• ecr
  error counter register
• endn
  endian register
• gfc
  global filter configuration
• glb_ctl
  global control
• glb_status
  global status
• hpms
  high priority message status
• ie
  interrupt enable
• ile
  interrupt line enable
• ils
  interrupt line select
• ir
  interrupt register
• nbtp
  nominal bit timing and prescaler register
• ndat1
  new data1
• ndat2
  new data2
• psr
  protocol status register
• rwd
  ram watchdog
• rxbc
  rx buffer configuration
• rxesc
  rx buffer/fifo element size configuration
• rxf0a
  rx fifo0 acknowledge
• rxf0c
  rx fifo 0 configuration
• rxf0s
  rx fifo 0 status
• rxf1a
  rx fifo 1 acknowledge
• rxf1c
  rx fifo1 configuration
• rxf1s
  rx fifo1 status
• sidfc
  standard ID filter configuration
• tdcr
  transmitter delay compensation
• test
  test register
• tocc
  timeout counter configuration
• tocv
  timeout counter value
• ts_sel
  no description available
• tscc
  timestamp counter configuration
• tscfg
  timestamp configuration
• tscv
  timestamp counter value
• tss1
  timestamp status1
• tss2
  timestamp status2
• txbar
  tx buffer add request
• txbc
  tx buffer configuration
• txbcf
  tx buffer cancellation finished
• txbcie
  tx buffer cancellation finished interrupt enable
• txbcr
  tx buffer cancellation request
• txbrp
  tx buffer request pending
• txbtie
  tx buffer transmission interrupt enable
• txbto
  tx buffer transmission occurred
• txefa
  tx event fifo acknowledge
• txefc
  tx event fifo configuration
• txefs
  tx event fifo status
• txesc
  tx buffer element size configuration
• txfqs
  tx fifo/queue status
• xidam
  extended id and mask
• xidfc
  extended ID filter configuration

Structs

• RegisterBlock
  Register block

Type Aliases

• ATB
  ATB (rw) register accessor: actual timebase
• ATBH
  ATBH (rw) register accessor: actual timebase high
• CCCR
  CCCR (rw) register accessor: CC control register
• CREL
  CREL (rw) register accessor: core release register
• DBTP
  DBTP (rw) register accessor: data bit timing and prescaler, writeable when CCCR.CCE and CCCR.INT are set
• ECR
  ECR (rw) register accessor: error counter register
• ENDN
  ENDN (rw) register accessor: endian register
• GFC
  GFC (rw) register accessor: global filter configuration
• GLB_CTL
  GLB_CTL (rw) register accessor: global control
• GLB_STATUS
  GLB_STATUS (rw) register accessor: global status
• HPMS
  HPMS (rw) register accessor: high priority message status
• IE
  IE (rw) register accessor: interrupt enable
• ILE
  ILE (rw) register accessor: interrupt line enable
• ILS
  ILS (rw) register accessor: interrupt line select
• IR
  IR (rw) register accessor: interrupt register
• NBTP
  NBTP (rw) register accessor: nominal bit timing and prescaler register
• NDAT1
  NDAT1 (rw) register accessor: new data1
• NDAT2
  NDAT2 (rw) register accessor: new data2
• PSR
  PSR (rw) register accessor: protocol status register
• RWD
  RWD (rw) register accessor: ram watchdog
• RXBC
  RXBC (rw) register accessor: rx buffer configuration
• RXESC
  RXESC (rw) register accessor: rx buffer/fifo element size configuration
• RXF0A
  RXF0A (rw) register accessor: rx fifo0 acknowledge
• RXF0C
  RXF0C (rw) register accessor: rx fifo 0 configuration
• RXF0S
  RXF0S (rw) register accessor: rx fifo 0 status
• RXF1A
  RXF1A (rw) register accessor: rx fifo 1 acknowledge
• RXF1C
  RXF1C (rw) register accessor: rx fifo1 configuration
• RXF1S
  RXF1S (rw) register accessor: rx fifo1 status
• SIDFC
  SIDFC (rw) register accessor: standard ID filter configuration
• TDCR
  TDCR (rw) register accessor: transmitter delay compensation
• TEST
  TEST (rw) register accessor: test register
• TOCC
  TOCC (rw) register accessor: timeout counter configuration
• TOCV
  TOCV (rw) register accessor: timeout counter value
• TSCC
  TSCC (rw) register accessor: timestamp counter configuration
• TSCFG
  TSCFG (rw) register accessor: timestamp configuration
• TSCV
  TSCV (rw) register accessor: timestamp counter value
• TSS1
  TSS1 (rw) register accessor: timestamp status1
• TSS2
  TSS2 (rw) register accessor: timestamp status2
• TS_SEL
  TS_SEL (rw) register accessor: no description available
• TXBAR
  TXBAR (rw) register accessor: tx buffer add request
• TXBC
  TXBC (rw) register accessor: tx buffer configuration
• TXBCF
  TXBCF (rw) register accessor: tx buffer cancellation finished
• TXBCIE
  TXBCIE (rw) register accessor: tx buffer cancellation finished interrupt enable
• TXBCR
  TXBCR (rw) register accessor: tx buffer cancellation request
• TXBRP
  TXBRP (rw) register accessor: tx buffer request pending
• TXBTIE
  TXBTIE (rw) register accessor: tx buffer transmission interrupt enable
• TXBTO
  TXBTO (rw) register accessor: tx buffer transmission occurred
• TXEFA
  TXEFA (rw) register accessor: tx event fifo acknowledge
• TXEFC
  TXEFC (rw) register accessor: tx event fifo configuration
• TXEFS
  TXEFS (rw) register accessor: tx event fifo status
• TXESC
  TXESC (rw) register accessor: tx buffer element size configuration
• TXFQS
  TXFQS (rw) register accessor: tx fifo/queue status
• XIDAM
  XIDAM (rw) register accessor: extended id and mask
• XIDFC
  XIDFC (rw) register accessor: extended ID filter configuration