Module gd32vf103_pac::timer0::ctl1

control register 1

Structs

• CTL1_SPEC
  control register 1
• R
  Register CTL1 reader
• W
  Register CTL1 writer

Type Definitions

• CCSE_R
  Field CCSE reader - Commutation control shadow enable
• CCSE_W
  Field CCSE writer - Commutation control shadow enable
• CCUC_R
  Field CCUC reader - Commutation control shadow register update control
• CCUC_W
  Field CCUC writer - Commutation control shadow register update control
• DMAS_R
  Field DMAS reader - DMA request source selection
• DMAS_W
  Field DMAS writer - DMA request source selection
• ISO0N_R
  Field ISO0N reader - Idle state of channel 0 complementary output
• ISO0N_W
  Field ISO0N writer - Idle state of channel 0 complementary output
• ISO0_R
  Field ISO0 reader - Idle state of channel 0 output
• ISO0_W
  Field ISO0 writer - Idle state of channel 0 output
• ISO1N_R
  Field ISO1N reader - Idle state of channel 1 complementary output
• ISO1N_W
  Field ISO1N writer - Idle state of channel 1 complementary output
• ISO1_R
  Field ISO1 reader - Idle state of channel 1 output
• ISO1_W
  Field ISO1 writer - Idle state of channel 1 output
• ISO2N_R
  Field ISO2N reader - Idle state of channel 2 complementary output
• ISO2N_W
  Field ISO2N writer - Idle state of channel 2 complementary output
• ISO2_R
  Field ISO2 reader - Idle state of channel 2 output
• ISO2_W
  Field ISO2 writer - Idle state of channel 2 output
• ISO3_R
  Field ISO3 reader - Idle state of channel 3 output
• ISO3_W
  Field ISO3 writer - Idle state of channel 3 output
• MMC_R
  Field MMC reader - Master mode control
• MMC_W
  Field MMC writer - Master mode control
• TI0S_R
  Field TI0S reader - Channel 0 trigger input selection
• TI0S_W
  Field TI0S writer - Channel 0 trigger input selection