Module gd32vf103_pac::timer1::dmainten
source · Expand description
DMA/Interrupt enable register
Structs
- DMA/Interrupt enable register
- Register
DMAINTEN
reader - Register
DMAINTEN
writer
Type Definitions
- Field
CH0DEN
reader - Channel 0 capture/compare DMA request enable - Field
CH0DEN
writer - Channel 0 capture/compare DMA request enable - Field
CH0IE
reader - Channel 0 capture/compare interrupt enable - Field
CH0IE
writer - Channel 0 capture/compare interrupt enable - Field
CH1DEN
reader - Channel 1 capture/compare DMA request enable - Field
CH1DEN
writer - Channel 1 capture/compare DMA request enable - Field
CH1IE
reader - Channel 1 capture/compare interrupt enable - Field
CH1IE
writer - Channel 1 capture/compare interrupt enable - Field
CH2DEN
reader - Channel 2 capture/compare DMA request enable - Field
CH2DEN
writer - Channel 2 capture/compare DMA request enable - Field
CH2IE
reader - Channel 2 capture/compare interrupt enable - Field
CH2IE
writer - Channel 2 capture/compare interrupt enable - Field
CH3DEN
reader - Channel 3 capture/compare DMA request enable - Field
CH3DEN
writer - Channel 3 capture/compare DMA request enable - Field
CH3IE
reader - Channel 3 capture/compare interrupt enable - Field
CH3IE
writer - Channel 3 capture/compare interrupt enable - Field
TRGDEN
reader - Trigger DMA request enable - Field
TRGDEN
writer - Trigger DMA request enable - Field
TRGIE
reader - Trigger interrupt enable - Field
TRGIE
writer - Trigger interrupt enable - Field
UPDEN
reader - Update DMA request enable - Field
UPDEN
writer - Update DMA request enable - Field
UPIE
reader - Update interrupt enable - Field
UPIE
writer - Update interrupt enable