Module gd32vf103_pac::timer1::chctl2

Channel control register 2

Structs

• CHCTL2_SPEC
  Channel control register 2
• R
  Register CHCTL2 reader
• W
  Register CHCTL2 writer

Type Definitions

• CH0EN_R
  Field CH0EN reader - Channel 0 capture/compare function enable
• CH0EN_W
  Field CH0EN writer - Channel 0 capture/compare function enable
• CH0P_R
  Field CH0P reader - Channel 0 capture/compare function polarity
• CH0P_W
  Field CH0P writer - Channel 0 capture/compare function polarity
• CH1EN_R
  Field CH1EN reader - Channel 1 capture/compare function enable
• CH1EN_W
  Field CH1EN writer - Channel 1 capture/compare function enable
• CH1P_R
  Field CH1P reader - Channel 1 capture/compare function polarity
• CH1P_W
  Field CH1P writer - Channel 1 capture/compare function polarity
• CH2EN_R
  Field CH2EN reader - Channel 2 capture/compare function enable
• CH2EN_W
  Field CH2EN writer - Channel 2 capture/compare function enable
• CH2P_R
  Field CH2P reader - Channel 2 capture/compare function polarity
• CH2P_W
  Field CH2P writer - Channel 2 capture/compare function polarity
• CH3EN_R
  Field CH3EN reader - Channel 3 capture/compare function enable
• CH3EN_W
  Field CH3EN writer - Channel 3 capture/compare function enable
• CH3P_R
  Field CH3P reader - Channel 3 capture/compare function polarity
• CH3P_W
  Field CH3P writer - Channel 3 capture/compare function polarity