Module gd32vf103_pac::timer1::chctl1_output

source ·
Expand description

Channel control register 1 (output mode)

Structs

  • CHCTL1_OUTPUT_SPEC
    Channel control register 1 (output mode)
  • R
    Register CHCTL1_Output reader
  • W
    Register CHCTL1_Output writer

Type Definitions

  • CH2COMCEN_R
    Field CH2COMCEN reader - Channel 2 output compare clear enable
  • CH2COMCEN_W
    Field CH2COMCEN writer - Channel 2 output compare clear enable
  • CH2COMCTL_R
    Field CH2COMCTL reader - Channel 2 compare output control
  • CH2COMCTL_W
    Field CH2COMCTL writer - Channel 2 compare output control
  • CH2COMFEN_R
    Field CH2COMFEN reader - Channel 2 output compare fast enable
  • CH2COMFEN_W
    Field CH2COMFEN writer - Channel 2 output compare fast enable
  • CH2COMSEN_R
    Field CH2COMSEN reader - Channel 2 compare output shadow enable
  • CH2COMSEN_W
    Field CH2COMSEN writer - Channel 2 compare output shadow enable
  • CH2MS_R
    Field CH2MS reader - Channel 2 I/O mode selection
  • CH2MS_W
    Field CH2MS writer - Channel 2 I/O mode selection
  • CH3COMCEN_R
    Field CH3COMCEN reader - Channel 3 output compare clear enable
  • CH3COMCEN_W
    Field CH3COMCEN writer - Channel 3 output compare clear enable
  • CH3COMCTL_R
    Field CH3COMCTL reader - Channel 3 compare output control
  • CH3COMCTL_W
    Field CH3COMCTL writer - Channel 3 compare output control
  • CH3COMFEN_R
    Field CH3COMFEN reader - Channel 3 output compare fast enable
  • CH3COMFEN_W
    Field CH3COMFEN writer - Channel 3 output compare fast enable
  • CH3COMSEN_R
    Field CH3COMSEN reader - Channel 3 output compare shadow enable
  • CH3COMSEN_W
    Field CH3COMSEN writer - Channel 3 output compare shadow enable
  • CH3MS_R
    Field CH3MS reader - Channel 3 mode selection
  • CH3MS_W
    Field CH3MS writer - Channel 3 mode selection