Module gd32vf103_pac::timer1::chctl0_output

source ·
Expand description

Channel control register 0 (output mode)

Structs

  • CHCTL0_OUTPUT_SPEC
    Channel control register 0 (output mode)
  • R
    Register CHCTL0_Output reader
  • W
    Register CHCTL0_Output writer

Type Definitions

  • CH0COMCEN_R
    Field CH0COMCEN reader - Channel 0 output compare clear enable
  • CH0COMCEN_W
    Field CH0COMCEN writer - Channel 0 output compare clear enable
  • CH0COMCTL_R
    Field CH0COMCTL reader - Channel 0 compare output control
  • CH0COMCTL_W
    Field CH0COMCTL writer - Channel 0 compare output control
  • CH0COMFEN_R
    Field CH0COMFEN reader - Channel 0 output compare fast enable
  • CH0COMFEN_W
    Field CH0COMFEN writer - Channel 0 output compare fast enable
  • CH0COMSEN_R
    Field CH0COMSEN reader - Channel 0 compare output shadow enable
  • CH0COMSEN_W
    Field CH0COMSEN writer - Channel 0 compare output shadow enable
  • CH0MS_R
    Field CH0MS reader - Channel 0 I/O mode selection
  • CH0MS_W
    Field CH0MS writer - Channel 0 I/O mode selection
  • CH1COMCEN_R
    Field CH1COMCEN reader - Channel 1 output compare clear enable
  • CH1COMCEN_W
    Field CH1COMCEN writer - Channel 1 output compare clear enable
  • CH1COMCTL_R
    Field CH1COMCTL reader - Channel 1 compare output control
  • CH1COMCTL_W
    Field CH1COMCTL writer - Channel 1 compare output control
  • CH1COMFEN_R
    Field CH1COMFEN reader - Channel 1 output compare fast enable
  • CH1COMFEN_W
    Field CH1COMFEN writer - Channel 1 output compare fast enable
  • CH1COMSEN_R
    Field CH1COMSEN reader - Channel 1 output compare shadow enable
  • CH1COMSEN_W
    Field CH1COMSEN writer - Channel 1 output compare shadow enable
  • CH1MS_R
    Field CH1MS reader - Channel 1 mode selection
  • CH1MS_W
    Field CH1MS writer - Channel 1 mode selection