Module gd32vf103_pac::timer0::chctl0_input

source ·
Expand description

Channel control register 0 (input mode)

Structs

  • CHCTL0_INPUT_SPEC
    Channel control register 0 (input mode)
  • R
    Register CHCTL0_Input reader
  • W
    Register CHCTL0_Input writer

Type Definitions

  • CH0CAPFLT_R
    Field CH0CAPFLT reader - Channel 0 input capture filter control
  • CH0CAPFLT_W
    Field CH0CAPFLT writer - Channel 0 input capture filter control
  • CH0CAPPSC_R
    Field CH0CAPPSC reader - Channel 0 input capture prescaler
  • CH0CAPPSC_W
    Field CH0CAPPSC writer - Channel 0 input capture prescaler
  • CH0MS_R
    Field CH0MS reader - Channel 0 mode selection
  • CH0MS_W
    Field CH0MS writer - Channel 0 mode selection
  • CH1CAPFLT_R
    Field CH1CAPFLT reader - Channel 1 input capture filter control
  • CH1CAPFLT_W
    Field CH1CAPFLT writer - Channel 1 input capture filter control
  • CH1CAPPSC_R
    Field CH1CAPPSC reader - Channel 1 input capture prescaler
  • CH1CAPPSC_W
    Field CH1CAPPSC writer - Channel 1 input capture prescaler
  • CH1MS_R
    Field CH1MS reader - Channel 1 mode selection
  • CH1MS_W
    Field CH1MS writer - Channel 1 mode selection